85 Threads found on edaboard.com: 0 13um Technology
I want to design LNA with below requirements. Can anyone please help in designing LNA? I am using 0.13um technology and Synopsis hspicerf simulator. I am quite beginner so I am not sure where to start and how to proceed. I looked an example in Thomas Lee book and other online but not getting clear idea.
Rin = 50 ohm
RF, Microwave, Antennas and Optics :: 03.06.2012 07:30 :: brjaiswal :: Replies: 2 :: Views: 529
Hi can any body send me the model file of 0.13um technology or give me link where i can get it?u r help is greatly appreciated
Analog Circuit Design :: 05.02.2006 01:35 :: sureshbabu_movva :: Replies: 1 :: Views: 645
In a 0.13um process are the caps MIM caps? If so, you can NOT stack them
With a 1fF/(?m)? cap value I suppose it's a MOM cap. They can be stacked.
Analog IC Design and Layout :: 15.11.2010 05:16 :: erikl :: Replies: 7 :: Views: 943
Iam designing VCO using UMC0.13um technology in cadence .Iam getting the results with pinductor from analog library.But when i replace this inductor with technology inductor simulator showing error "unable to oscillate swing at the output node is very small".can any one explain.Thanks in advance.
Analog IC Design and Layout :: 21.11.2010 05:17 :: sureshnaidu :: Replies: 1 :: Views: 374
I am working on design of CMOS second generation current controlled current conveyors (CCCII+). I am working in 0.13um CMOS technology. I am stuck with the design of W/L ratios of the transistors. Can anyone please help me how to design the W/L ratios of the design in this technology. If you have any link that can help me, please post it. If (...)
Analog Circuit Design :: 27.06.2012 05:23 :: udaykumarreddy456 :: Replies: 1 :: Views: 371
0.13um actually means poly pitch
i.e half width of a minimum poly allowed in the technology + min distance between the two min width poys
Analog Circuit Design :: 12.01.2005 08:13 :: venkatesh :: Replies: 18 :: Views: 4376
10.x um^2 (5.0x * 1.9x)in tsmc/umc/csm/smic .18 technology
ASIC Design Methodologies and Tools (Digital) :: 08.11.2004 11:04 :: CatKing :: Replies: 6 :: Views: 1843
I am looking for process information on CMOS 0.13um process technologies for RF and Analog Circuits. Questions like why I would use 0.13 vs. 0.18, any documentation anyone has on these processes, papers, thesis or whatever, inductors, capacitors, varactors, and so on.
Analog IC Design and Layout :: 10.12.2004 17:52 :: Puppet1 :: Replies: 8 :: Views: 2125
25 -- > 18 -- > 13 -- > 09 --> 065
All the previous number is around 1.41 times of hte next number.
Does that trigger you any thoughts?? (hints: 1.41^2 = 2)
ASIC Design Methodologies and Tools (Digital) :: 15.03.2005 02:56 :: sandusty :: Replies: 1 :: Views: 521
I think it is also up to the LDO SPEC, most people like to use 0.6u~0.25um to design power management circuit.
Analog IC Design and Layout :: 24.05.2005 10:59 :: piao :: Replies: 6 :: Views: 1158
I am desigining some circuit which is highly dependent on the parasitic capacitance, esp. the matching of the capacitance at different location. I am wondering how reliable is the parasitic extracted cap of the cadence.
Is there any special layout technique to improve the reliability?
Since I am using 0.13um technology, I need to add some fi
Analog IC Design and Layout :: 07.09.2005 15:53 :: danda821 :: Replies: 2 :: Views: 675
Hi, has anyone used cmrf8sf tech before?
I am stucked with nfet transistor (nfet_inh and nfet_rf are okay). How can I connect the B-terminal to ground in layout? Do I use nTiedown?
I have tried subc, nTiedown, not working.
Any suggestions? Thanks!
Analog IC Design and Layout :: 29.11.2005 00:07 :: jerrymelb :: Replies: 18 :: Views: 4100
If two identical digital core circuits, which are, implemented in 0.18um
and 0.13um, respectively. What's the power consumption relation between
the two implementations?
Any rule of thumb or simple calculation?
ASIC Design Methodologies and Tools (Digital) :: 29.11.2005 08:42 :: hebu :: Replies: 5 :: Views: 1328
i was working on 0.18um, now i want to design the first 0.13um chip for me.
i want to know what are different. thanks.
Analog IC Design and Layout :: 07.12.2005 00:12 :: beabroad :: Replies: 8 :: Views: 895
0.13um technology and technology under 0.13um have bigger percentage of leakage power. multiple Vt std library( low, normal, high Vt) are used for reducing leakage power .
They have same area.
low Vt ( fast, bigger leakage) , high Vt ( slow, smaller leakage)
ASIC Design Methodologies and Tools (Digital) :: 25.12.2005 12:41 :: johnz :: Replies: 10 :: Views: 1179
Don't worry 65nm is almost the same as 90nm and up.
Analog IC Design and Layout :: 11.03.2006 23:57 :: yaxazaa :: Replies: 9 :: Views: 1621
Is the flicker noise corner frequency at 65nm higher than the bandwidth for most communication standards? So between 10-50MHz depending on on device size.
Is the gm variability of the minimum length devices about 50%?
Is the threshold voltage shift after 1year and 70°C 10-20%?
Who models all these effects?
Who take care of these effects
Analog IC Design and Layout :: 15.03.2006 10:23 :: rfsystem :: Replies: 5 :: Views: 682
can someone tell me the least technology used in the industry today for analog/RF design. I had heard that 0.13um is the least for analog/RF design. Is it true?
has anyone done any design on analog/RF at technology lesser than 0.13um.
Thanx in advance
Analog Circuit Design :: 14.03.2006 00:14 :: Chethan :: Replies: 1 :: Views: 450
Micron tehcnology ==> 1um, 2um, 3um, etc
sub-micron techology ==> 0.8um, 0.6um, 0.35um 0.25um etc
deep sub-micro technology ==> 0.18um, 0.13um
nanotechnoogy ==> 90nm, 65nm etc
Basically, use the words "sub" and "deep" as in the English defination of the words.
ASIC Design Methodologies and Tools (Digital) :: 14.04.2006 05:37 :: leeenghan :: Replies: 5 :: Views: 5651
I work with 0.13um tech and I can confirm to you that in this tech, there is 6 layer metal Level.
I still ready to answer for particular questions
ASIC Design Methodologies and Tools (Digital) :: 24.03.2006 04:31 :: gafsos :: Replies: 2 :: Views: 782
Has anyone used mimcap with the chartered 0.13um RF technology?
If so did you have any problems?
Analog IC Design and Layout :: 03.05.2006 21:27 :: franck :: Replies: 0 :: Views: 951
A problem on hot carriers effect of 0.13um CMOS technology
The process used is 0.13um CMOS technology, and the analog nmos and pmos used have the min. channel length about 0.4um and the tox is about 5.2nm. During the I-V simulation of the NMOS(1um/0.4um) and it is found that the output resistance have the four region: (...)
Analog IC Design and Layout :: 08.08.2006 01:26 :: STMicro :: Replies: 2 :: Views: 815
I am trying to simulate some circuits on my home PC using WinSpice. I was wondering if someone could direct me to spice models in 0.13 micron technology.
There are models available for MOSFETS but no models for resistors and capacitors. I don't wish to use ideal elements. Please help
Analog IC Design and Layout :: 25.08.2006 08:46 :: bunda_bindaas :: Replies: 1 :: Views: 828
Not 100% sure but BSIM 3.3 should model gate leakge. Note that in HSPICE it will not show in the OP statement listing - you will have to place 0 voltage source in series with gate voltage to measure it. BTW: in 0.13 gate leakage is not that big but already significant for some applications - like LPF for low jitter PLL.
Analog IC Design and Layout :: 09.10.2006 18:06 :: janziobro :: Replies: 4 :: Views: 988
Any one can tell me there are what differences between 0.13um and 0.18um, when I run Astro.
ASIC Design Methodologies and Tools (Digital) :: 13.11.2006 21:35 :: blueant :: Replies: 5 :: Views: 644
standard CMOS is logic CMOS
except that there are
Mix-Signal CMOS tech.
The diference is that:
1. MIM capacitor
2. Thick top metal
3. Deep N well
4. VTH tuned mos
has also to be considered.
ASIC Design Methodologies and Tools (Digital) :: 14.12.2006 08:32 :: wkong_zhu :: Replies: 1 :: Views: 637
hii...i'm chaitanya ...i'm doin my B.E 3RD in E.C.E.....i'm doing a mini project on designing a 114ghz vco in 0.13um cmos technology ....plz can anyone help regarding this..i've some prob in designing the attaching the file regarding this..
Hobby Circuits and Small Projects Problems :: 30.03.2007 08:33 :: chaitanyadeepak :: Replies: 0 :: Views: 652
I am using 0.13um UMC rf technology files
I wonder how to know Vdd & Cox for that technology and Vt for every transistor
I mean how to know the values of the parameter of that technology
Any one can help ??
send me the values if he know or tell me how to know it
Analog IC Design and Layout :: 20.06.2007 12:06 :: salem_eng1 :: Replies: 5 :: Views: 986
flxrouter4400, I am using SMIC0.13um technology.
What is the simple method to slot?
Analog IC Design and Layout :: 19.08.2007 10:19 :: longstar :: Replies: 7 :: Views: 971
It depend on your what technology and process you use .
The thickness of 300mm wafer is about 650-780um.
the conductivity is different for Bipolar and cMOS technology.
for cmos tech it mostly use high resistance p- substrate .
for bipolar tech it mostly use low resistance substrate(heavily doped n+/p+).
if you think this helps ,plz press the "
Analog IC Design and Layout :: 05.06.2008 22:38 :: freelancer :: Replies: 1 :: Views: 438
We know the channel noise of MOSFET can be expressed as 4kTγgd0(γ=2/3 for long channel). When it comes to deep sub-micro technology,its value is much higher than 2/3.
The question is when I simulate the LNA noise figure in spectre RF, according to the simulated results, I found γ is much closer with 2/3. I wonder how the simulat
RF, Microwave, Antennas and Optics :: 31.05.2008 22:20 :: freewisp :: Replies: 2 :: Views: 868
i need cadence Ic Design 0.18um &0.13um library.if you have this files please send
Analog Circuit Design :: 14.09.2008 05:32 :: mahdimbayat :: Replies: 2 :: Views: 671
90nm or .13um
Analog IC Design and Layout :: 16.11.2008 09:16 :: leo_o2 :: Replies: 6 :: Views: 1116
I am planing to learn ckt design at home. i have managed to get cadence pspice a/d simulator. Now i need some device models to start. where can i get ? can i use it with this tool ?
Analog IC Design and Layout :: 13.06.2009 06:25 :: sakthiprashanth :: Replies: 4 :: Views: 2217
the straps are used to reduce the IR drop!
with 0.13um technology , hou much voltage will the 1400um length wire bring on ?
Analog IC Design and Layout :: 24.09.2009 01:41 :: visualart :: Replies: 4 :: Views: 685
I'm gonna design a bandgap voltage reference in 0.13um technology with 1.2V supply.
can any one tell me how to start?.
which topology i should choose?
and if there is a numerical example it would be great.
thnanks in advance,
Analog Circuit Design :: 04.04.2010 11:49 :: banosey :: Replies: 1 :: Views: 573
Input/output delay can be easily seen at 4 GHz. The only way to overcome that is to use minimum transistor sizes. I dont think also that there is a way to have a 50% duty cycle directly from the DFFs. My idea is to use a simple clock adjuster that ANDs the Clock with itself delayed by Δt.
Analog Circuit Design :: 22.06.2010 10:16 :: AdvaRes :: Replies: 4 :: Views: 1576
I am drawing the layout for my design using IBM 0.13um CMOS technology (virtouso). This is my first time using the IBM process so I have a few questions about the layout drawing.
1/ what is the different between pin and pad? When I insert input and output pins in my layout, the LVS can recognize them as IO Ports.
2/ Are the pads requi
Analog IC Design and Layout :: 25.08.2010 04:16 :: hhnn :: Replies: 5 :: Views: 1284
A simple clock generator would be a constant current feeding into a cap and using a comparator to look at cap slope to Vref ~ compare and reset cap and repeat. This comparator then just flips a D flip flop which then generates your 50K clock. Then you make an non overlapping nand latch to make your phi1 and phi2.
hope this helps
Analog IC Design and Layout :: 21.03.2011 14:40 :: jgk2004 :: Replies: 5 :: Views: 694
i am working on a sigma delta modulator using .13um technology and i want an output from the DAC ranging from .225 to 1.575 and my Vdd=1.8 so i can't do that as my common mode input is .9 how can i do this big swing DAC
ASIC Design Methodologies and Tools (Digital) :: 11.04.2011 04:49 :: hoka_89 :: Replies: 1 :: Views: 292
i m bit new to T-spice..
when i searched for 0.13um technology file from MOSIS, i came to know across such words and whatever file i have downloaded could not worked with my netlist which was generated with tspice 0.18um cmos...
can anyone explain why?? what are such things??
Analog IC Design and Layout :: 28.01.2012 04:32 :: jigisha :: Replies: 3 :: Views: 362
Iam doing a layout on Low Noise Ampifier in 0.13um technology using Assura Layout XL. I have encountered with DRC errors such as
1. Minimum DIFFUSION Density over 500x500 um^2 is 20%
2. Minimum PO1 density over 1000x1000 um^2 is 15%.
Can anyone please give me a solution to solve these errors.
And also, I want to know the reason, why d
Analog IC Design and Layout :: 24.02.2012 00:07 :: Maithreyi :: Replies: 4 :: Views: 600
I an new here and this is my first post. I am a newbie to ASIC and as part of my semester project I am implementing a 3TDRAM. I am using 0.13um technology and Cadence Hspice and Spectre tools. I am running into some simulator issues.
1. I initially started in hspice but realised I had to do monte Carlo so i switched to Spectre. But w
ASIC Design Methodologies and Tools (Digital) :: 24.03.2012 18:10 :: nincredible :: Replies: 0 :: Views: 257
I have used the ideal Gm cell and capacitor to compose a 3rd order chebychev Gm_C low pass
filter.The simulation results are as follows: voltage gain=20dB, -1dB BW=10MHz,the steepness
of 20MHz is 21dB.
But when I design the circuits with TSMC 0.13um technology, using the same Gm and capacitor
values and filter structure, voltage gain
Analog Circuit Design :: 21.05.2012 09:53 :: weihuiting :: Replies: 0 :: Views: 263
I need to estimate the power of my designed circuit in Synopsys power compiler(of design compiler). I have .db file(library) for TSMC 0.18um technology, but it doesn't include SRAM , and it recognize all of my SRAMS(about 3Kbit) block as DFF, which cause a lot of extra power consumption. I am looking for another library to use in power
ASIC Design Methodologies and Tools (Digital) :: 28.07.2012 08:59 :: sea_mist :: Replies: 4 :: Views: 672
What are the advantages and disadvantages of the 0.5um and 0.13um technology ?
Analog Circuit Design :: 29.11.2012 21:18 :: Mmensah :: Replies: 2 :: Views: 175
I am using UMC 0.13um RF technology to design a TIA. I am facing problems with Assura QRC verification. An error message appears:
ERROR (ASSREXT-88016): cap ground signal 'agnd' cannot be found.
Check if net 'agnd' exists in design ad has the correct ?netNameSpace (Schematic, Layout) specified in RSF.
if the ground signal name c
Analog IC Design and Layout :: 26.04.2013 15:58 :: afp2008 :: Replies: 0 :: Views: 303
Anyone have 90 nm cmos models ?
Analog IC Design and Layout :: 29.06.2004 03:30 :: Puppet1 :: Replies: 5 :: Views: 1853
Can anybody share me some information about the average or approximate gate count numbers for following ASIC building blocks?
1)16*16 booth multiplier
2) two 16bit inputs ALU, traditional arithmetic(add,sub....) and logic (and,or,xor....) operations supported
3)16bit Barrel shifter,supporting traditional logic shift and arithmetic shift
ASIC Design Methodologies and Tools (Digital) :: 12.10.2004 09:43 :: eexuke :: Replies: 2 :: Views: 1113
Careful though. For standby conditions 0.13um can be worse than 0.18um because the off-state leakage of the mos devices is higher.
ASIC Design Methodologies and Tools (Digital) :: 05.11.2004 03:01 :: Colbhaidh :: Replies: 5 :: Views: 949