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16 1 Mux Using 4 1 Mux

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1000 Threads found on 16 1 Mux Using 4 1 Mux
Can any one can send me right verilog code for designing 16 by 1 mux using 4 by1 mux in structural modellng?
How to implement a 4:1 mux using just 2 4-input LUTs? Does each 4-input LUT independently use four inputs to select one of 16 design-time-configured "fuses"? So each LUT generates an independent function of four inputs? Under those conditions, the problem is solvable with the caveat that switching between (...)
Hi friends I want implement a 4:1 mux using 8:1 mux. I have a solution. whether it is correct? I attached the Logic, see to it and reply. Thanks & Regards....
Hi, I am a new member of this site. I start with a simple question - How we can implement a 5:1 mux using any number of 4:1 mux?What about unused ports?
hi , anyone help me to implement mux using XOR gate? Note: its not xor using mux thanks in advance
Any one please give me circuit digram of "8:1 mux using Transmission gates"
Can anyone send me a material on NOT ,AND ,XOR,XNOR,NAND,INVERTER using mux ??? Plz its urgent send me a material i will give u 20 points
Hi all, Below is the verilog code for posedge and negedge flipflops using mux. I have also attached the pictorial representation of the circuit. Verilog code : module mux_ff( clk, in, out_pos, out_neg ); input clk; input in; output out_pos; output (...)
how to design 2x1 mux using half adders
hello all, i designed 2x1 mux using transmission gate in 65nm node. i am getting 40ps delay from mux. any one can suggest me method to reduce delay. i knw the delay depends upon the o/p and i/p load. i want to knw any one have ans for the load optimization also. i want to thank you in advance for ur (...)
Hi, I want to draw a module diagram for 32 bit RZ encoder using mux or state machine in ARINC 429 Transmitter block. Please help me to draw this. Thanks
Hi, what are the input and output pin description to rz encoder using mux in arinc 429 protocol. Pls reply to my question. Thanks
Hi all! what is the difference between PAM using mux/demux for 1 link/ 2 link/ 3link. We had performed all three in lab. But I don't understand the significance of doing it in three ways. Which one is better?
In scan insertion, tool convert the design flip-flop in Scan flip-flop. Already we have bunch of flops in design. So no need to insert extra flops. Is it same for mux also if i am using mux-D flops scan cells. Have we enough amount of mux such that we don't need to insert (...)
want to implement a cascaded stages of mux using system generator?
Hello all :) I need some help please in getting the theoritical BER curve of 16-QAM using MATLAB Your help is much appreciated :D Thank you very much
Hi all I want to design custom LCD "2 line*16 char" using Hd44780U & HD44100 any reference schematic :idea: Thanks S 8O RAT
hi friends, i need to implement a vhdl code for a 4 to 16 decoder using 2 to 4 decoder in xilinx.plz can any one help me with the details relating to it or forward links related to my requirement.. thanks in advance
You can see the attached image, which shows how to construct a 4:16 decoder using 1:2
Need a verilog structural code for Extend the four-bit ripple carry adder to 16 bits using four of the four bit adders
Can simulate in Orcad 16 lcd using pic and display the letters that appear in the display the same way as in Proteus?
can any one tell me which cpld is suitable with minimum no of i/o in which i can implement four 16:1 mux,means 64X1 mux using 16x1 as a component? also give me specification?because i want to implement it ith PLCC package? for that which cpld i will use?
Design a barrel shifter for 16 bit words in VHDL. This barrel shifter is capable of logical shifting input toward left and right direction. Two different architecture designs of the same barrel shifter must be implemented and tested with the testbench you also need to develop. One architecture (e.g., structural) must use a 16-bit multiplexer (M
Can anyone tell me how to design a XOR gate using 2:1 mux and an inverter. I have tried all ways and couldnt find a solution. Thx radhika
hi, well i could give u the logic its up to you to write the code... say A3 A2 A1 A0 are your select lines with A3 being the msb and A0 the lsb. say d0-d15 are your inputs. so use 4 4X1 multiplexers at the input . such that the u have d0-d3 connected to the input of the mux1, d4-d7 as i/p to the mux2, d8-d11 i/p to (...)
Hi friends, To design 4-bit 2's complementer using minimum number of 2:1 mux. I tryed and got a result, First I found the boolean equation's using K'Map. The equations are If A,B,C,D are inputs and W,X,Y,Z are outputs W=A xor (B+C+D) X=B xor (C+D) Y=C xor D Z= D After that I implemented these equation (...)
hai guys can any body solve this one ..?????
can any one design D flip flop and T flip flop using 2:1 mux
Implement a two input and gate using 2-1 mux ??? pls help in this regard..................
F(A,B,C,D)=SOP(0,1,3,4,8,9,15) Use a 8X1 mux and implement using (i)A,C,D (ii)A,B,D as Select lines! URGENT! :-|
do you mean 16 inputs and 4 outputs? or 16 inputs and 1x4bit output? For the first case, that would just be 4x 16x1 muxes.
hello every one can any one explain the implementation of 8:1 mux only using 2:1 mux Thanqs in Advance RGR
Please help me. Which is better ?......I don't how to use in my design. and why to use that. Txh
Hello! First you have to learn what is a multiplexer: A multiplexer is a device that selects one of many data-sources and outputs that source into a single channel. Hi, I would like to know what does 256 * 2 mux 8 mean? I know that 256 numbr of bits and 2 words which makes the memory size. This sounds amb
Hi this is a 8x1 mux... you can make 16x1 from it... LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY mux IS port(s:in std_logic_vector(2 downto 0); inp:in std_logic_vector(7 downto 0); op: out std_logic); END ENTITY mux; -- ARCHITECTURE (...)
need urgent help ..... how to built 8:1 mux with 2GHz frequency
Hi All, Please suggest possible ways for Possible ways of Designing Flip Flop from Latch and mux along with waveforms
Hi All, If anyone has material on E123 mux, Please will you upload for me. What is E123 mux? E123 mux: The E123mux is a VLSI core that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal (...)
Hello, I would like to find or build an analog signal multiplexer to serve as the front-end to an ultra-low bias current op-amp, for example the LMP7721. This amp has 3fA typical, 20fA max input bias current. This is the lowest amp I've found, but there are several other amps that are within 10X higher. However, I am having a really hard tim
Let us wrte the verilog RTL for 4:1 mux using a cse statement. Suppose the default clause is not specified in the case statement but all other options of cases are provided. What will the verilog code then synthesize to? Will it be synthesize a 4:1 mux or a latch? Can you draw that latch if it synthesize to (...)
Can anybody give me insight about 6:2 mux? I am aware of simple x:1 mux, but have never thought about more than one output mux. In an interview i was told to implement 6:2 mux using 2:1 mux. Please share (...)
Hello all (First post on forum) I understand that I have yet to contribute anything to this community and therefore you will be unlikely to help me, but I'm hoping someone will find it in their heart to offer assistance. Basically I am revising for a University resit exam that's coming up for a Computer Systems module. For the most part, I can
Please tell me how construct 8:1 mux using 2:1 mux?
How can one implement a 10 to 1 mux using any number of 4 to 1 mux
Method1: assign y = sel ? a : b; Method2: case sel 1'b0: y = b; 1'b1: y = a; endcase Method3: if (sel) y = a; else y = b; What is the difference between the implementation of mux using these three different methods ? How do these methods treat 'x' and 'z' on sel input ? After synthesi
I'm trying to sample from 8 channels using my dspic33fj128gp802 chip. I've had four channels working fine up until now, but trying to use the alternative mux switch isn't going to plan. I've tried to change the settings so that the DMA interrupt is polled after each second sample/conversion, in a hope that I can fill an eight word DMA (...)
Hi guys, Summary of Q's :D In cadence RC, upon clock gating, clock multiplexing or clock division, should I define the output clock from these modules in the synthesis script ? ---------------------- Detailed: I implemented a module with multiple clock inputs which I need to synthesize. say I have clk1_in &
dear sir, thanks for the was really informative. sir, my project is little bit complex. I have around 128 LED'S and all these LEDS have to be connected to FPGA/CPLD pins through suitable resisters directly. as you said all these 128 LED'S are arranged in 16 * 8 fasion. i start feeding data from first column and then second column and t
5 X 4-to-1 mux will have more control loading (loading on select pins) compare to 16-to-1 mux also the input to output delay will be more. If ur using descrete chips for muxex then PCB cost will be more in case of 5 X 4-to-1 mux. Any (...)
hi, i got the same problem too. i want to create 4-to1-package mux to built 16-to-1 mux. i've read some tutorial from quartus but could not find the answer. but i've read from google groups that previous version of quartus did not support the vhdl package. but i'm not sure about the latest version. anyone know how (...)