9 Threads found on edaboard.com: 16 1 Mux Using 4 1 Mux
i am interfacing GSM Module Sim 900 and GPS Module Holux M89 with Atmega32A using 74157 Multiplexer and select pin of mux is connected with pin 16 of Atmega32A. The Problem is that mux is not passing gps and gsm data to microcontroller. i have checked the continuity of traces all are ok. a (...)
Microcontrollers :: 07-12-2013 16:36 :: nauman_mrd :: Replies: 2 :: Views: 342
Can any one can send me right verilog code for designing 16 by 1 mux using 4 by1 mux in structural modellng?
Elementary Electronic Questions :: 10-31-2012 22:30 :: YASWANTH_802 :: Replies: 0 :: Views: 933
Design a barrel shifter for 16 bit words in VHDL. This barrel shifter is capable of
logical shifting input toward left and right direction. Two different architecture
designs of the same barrel shifter must be implemented and tested with the
testbench you also need to develop. One architecture (e.g., structural) must use a
16-bit multiplexer (M
Elementary Electronic Questions :: 03-12-2011 21:15 :: Anand Bhattar :: Replies: 1 :: Views: 2472
Hi there. I need to do the attach circuit. Can anyone help me?
Thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-29-2010 15:01 :: Vivasso :: Replies: 2 :: Views: 919
i want to convert my signal from the output of fifo from 16 bit to 8 bit because i need to transmit it via the rS232 that support only the 8 bit
so who can help me to do this task
if it is possible a logic circuit because i m working with block diagram in quartus software of altera
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-18-2008 09:53 :: heythem2008 :: Replies: 6 :: Views: 1757
5 X 4-to-1 mux will have more control loading (loading on select pins)
compare to 16-to-1 mux also the input to output delay will be more.
If ur using descrete chips for muxex then PCB cost will be more in case of
5 X 4-to-1 mux.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-06-2006 00:45 :: nand_gates :: Replies: 3 :: Views: 1681
can any one tell me which cpld is suitable with minimum no of i/o in which i can implement four 16:1 mux,means 64X1 mux using 16x1 as a component?
also give me specification?because i want to implement it ith PLCC package?
for that which cpld i will use?
ASIC Design Methodologies and Tools (Digital) :: 10-20-2005 07:46 :: abhineet22 :: Replies: 0 :: Views: 826
in order to save the i/o pin used, i want to cascade 16 signal lines by using 16-to-1 selector(multiplexer) but the problem is my signal lines are bidirectional. so how to solve it ??
Embedded Systems and Real-Time OS :: 04-01-2005 23:17 :: syteh82 :: Replies: 1 :: Views: 1068
Is the output delay corresponding to input is permittable in the design?
I guess its not , unless your design is sequential..
You can achieve the same results by using a combinational 16:1 mux with 16 bit inputs and 4 bit select. But ur code needs to be changed.
Please post ur NETLIST for omre comments..
ASIC Design Methodologies and Tools (Digital) :: 02-01-2005 10:06 :: eda_wiz :: Replies: 5 :: Views: 1211