35 Threads found on edaboard.com: 16 1 Mux Using 4 1 Mux
well i could give u the logic its up to you to write the code...
say A3 A2 A1 A0 are your select lines with A3 being the msb and A0 the lsb.
say d0-d15 are your inputs.
so use 4 4X1 multiplexers at the input . such that the u have d0-d3 connected to the input of the mux1, d4-d7 as i/p to the mux2, d8-d11 i/p to (...)
Electronic Elementary Questions :: 07.09.2005 01:17 :: rogger123 :: Replies: 1 :: Views: 5747
can any one tell me which cpld is suitable with minimum no of i/o in which i can implement four 16:1 mux,means 64X1 mux using 16x1 as a component?
also give me specification?because i want to implement it ith PLCC package?
for that which cpld i will use?
ASIC Design Methodologies and Tools (Digital) :: 20.10.2005 07:46 :: abhineet22 :: Replies: 0 :: Views: 639
How to implement a 4:1 mux using just 2 4-input LUTs?
Does each 4-input LUT independently use four inputs to select one of 16 design-time-configured "fuses"? So each LUT generates an independent function of four inputs?
Under those conditions, the problem is solvable with the caveat that switching between (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.07.2010 11:43 :: supercat :: Replies: 5 :: Views: 4401
Design a barrel shifter for 16 bit words in VHDL. This barrel shifter is capable of
logical shifting input toward left and right direction. Two different architecture
designs of the same barrel shifter must be implemented and tested with the
testbench you also need to develop. One architecture (e.g., structural) must use a
16-bit multiplexer (M
Electronic Elementary Questions :: 12.03.2011 21:15 :: Anand Bhattar :: Replies: 1 :: Views: 2067
do you mean 16 inputs and 4 outputs? or 16 inputs and 1x4bit output?
For the first case, that would just be 4x 16x1 muxes.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.09.2012 13:20 :: TrickyDicky :: Replies: 3 :: Views: 925
Can any one can send me right verilog code for designing 16 by 1 mux using 4 by1 mux in structural modellng?
Electronic Elementary Questions :: 31.10.2012 22:30 :: YASWANTH_802 :: Replies: 0 :: Views: 463
i am interfacing GSM Module Sim 900 and GPS Module Holux M89 with Atmega32A using 74157 Multiplexer and select pin of mux is connected with pin 16 of Atmega32A. The Problem is that mux is not passing gps and gsm data to microcontroller. i have checked the continuity of traces all are ok. a (...)
Microcontrollers :: 12.07.2013 16:36 :: nauman_mrd :: Replies: 2 :: Views: 204
in order to save the i/o pin used, i want to cascade 16 signal lines by using 16-to-1 selector(multiplexer) but the problem is my signal lines are bidirectional. so how to solve it ??
Embedded Systems and Real-Time OS :: 01.04.2005 23:17 :: syteh82 :: Replies: 1 :: Views: 923
I need to find a 16 bit device which has at least 12 analog inputs (12 channel mux) plus 6 pwm outputs (my application is a 6 channel maximum power point tracker) and a few other more common features (i2c, a multiplier, risc architecture and so on).
I would very much appreciate any comments as I don't even know well the different manu
Microcontrollers :: 09.06.2006 05:29 :: Alex Max :: Replies: 6 :: Views: 1040
5 X 4-to-1 mux will have more control loading (loading on select pins)
compare to 16-to-1 mux also the input to output delay will be more.
If ur using descrete chips for muxex then PCB cost will be more in case of
5 X 4-to-1 mux.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.09.2006 00:45 :: nand_gates :: Replies: 3 :: Views: 1530
im trying to run a package i'd created using quartus tools but when i run the compilation, an error with the following appear in the message box.
the following is the package header of simple full adder (fulladd_package.vhd):
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE fulladd_package IS
PORT ( Cin, x, y
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.12.2006 07:46 :: sora5563 :: Replies: 3 :: Views: 1401
Without knowing what light sensors are you using it is a little bit a guess work ..
Usually chips have pins called /CS (chip select), /OE (output enable, or similar ..
You can connect all data bits of all 8 sensors together to one 8-bit port, P0, for example, and use another 8 8051's general purpose I/O pins to control /CS (/OE) pins ..
Microcontrollers :: 20.02.2007 23:59 :: IanP :: Replies: 3 :: Views: 2393
Thanks for the reply vipin. But I need to use components in virtex4 fpga and build a up down counter. so I need to use a 16:1 mux and a D FF (D FF if needed). But in the link there are gates I need it with a 16:1 mux. So any help in this direction is really helpful.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.08.2012 20:20 :: pgadde1 :: Replies: 14 :: Views: 1506
Let me look at the problem from a straight fwd perspective.
One output Y, may get a value from either of 4 inputs a0, a1, a2, a3,
depending upon 4 other inputs w0, w1, w2 ,w3. OK?
ok 4to1 mux, but you have 4 lines to select(instead 2, which you normally have), i.e 16 input combinations to decide 4 choices for y i.e a0, a1, a2,
ASIC Design Methodologies and Tools (Digital) :: 21.09.2007 09:40 :: avimit :: Replies: 10 :: Views: 961
Just for building a dual clock FIFO.
But BRAM based dual clock FIFO is big, I only need 16 byte deep.
Instead of BRAM, use Distributed RAM based FIFO. It is synthesized as LUT only and does not consume any of BRAM on FPGA chip.
If you are using Xilinx FPGA, please refer XILINX Core Generator IP COR
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.12.2007 14:32 :: mpatel :: Replies: 3 :: Views: 1294
i want to convert my signal from the output of fifo from 16 bit to 8 bit because i need to transmit it via the rS232 that support only the 8 bit
so who can help me to do this task
if it is possible a logic circuit because i m working with block diagram in quartus software of altera
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.07.2008 09:53 :: heythem2008 :: Replies: 6 :: Views: 1534
ASA to ALL
im eorking on led matrix display consists of 16X16 led matrix can any body tel me what will the appropriate timmer1 relode value for this..... and why if you explain so i clear my concpts for scanning
your input will be highly apprictaed
Microcontrollers :: 25.10.2008 11:53 :: drbizzarow :: Replies: 4 :: Views: 1353
I am working on xilix ISE webpack AND sPARTAN 3E KIT
I want to know how a 16 bit input is passed tested on spartan 3e kit i.e where will the 16 input 4 are switches and rest???
where will be the 16 output are seen only 8 are given for leds
presently iam not having any code
I hav an idea which requires these
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.04.2009 06:04 :: ramesh441 :: Replies: 14 :: Views: 925
Hi there. I need to do the attach circuit. Can anyone help me?
Thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.10.2010 15:01 :: Vivasso :: Replies: 2 :: Views: 709
The voltage signal of a thermocouple type T is aproximately 40uV \ °C for a temperature range of 0 to 100 °C.
I want to read 15 type T thermocouples, all of them have same reference (ground reference, negative wire, minus wire).
I want to use an analog muliplexer (16:1 mux, model 74hc4067, it will be powered from a +3.3V rail)
Analog Circuit Design :: 25.01.2012 20:17 :: esm. :: Replies: 1 :: Views: 429
Specify more about what resolution you have, or how many characters you will display, etc.
I think easys way to do it, is using 5x8 led dot array, you must put 16 together, and control it with a few logic and a microcontroler like PIC, to control and comunicate it with a PC using serial port.
Hobby Circuits and Small Projects Problems :: 11.12.2002 08:32 :: penrico :: Replies: 18 :: Views: 14189
SOP = Sum Of product.
You can implement any logic circuit by draw it's truth table then from the truth table you can find equation for the o/p using AND & OR gates only.
CPLD uses these tech. It uses programmable AND & OR Gates array.
Note: this in simple, but actually it the Logic Cell contain Flip-Flops and mux for handle (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.11.2004 08:10 :: SphinX :: Replies: 5 :: Views: 979
Is the output delay corresponding to input is permittable in the design?
I guess its not , unless your design is sequential..
You can achieve the same results by using a combinational 16:1 mux with 16 bit inputs and 4 bit select. But ur code needs to be changed.
Please post ur NETLIST for omre comments..
ASIC Design Methodologies and Tools (Digital) :: 01.02.2005 10:06 :: eda_wiz :: Replies: 5 :: Views: 968
we have problems with analog multiplexer (dg406), becouse of crosstalk between chanels. at the imput, there are lf358 operation amplifiers, but they are disturbed with "parasitic switch" inside multiplexer which one short circuit input to negative voltage at channel change.
we solve some this using 1k resistor in series with opamp output.
Analog Circuit Design :: 20.06.2005 06:45 :: Mazi3 :: Replies: 3 :: Views: 981
I have a simulink model which consists of a parallel
blocks(filters)the outputs of which are muxed and plotted using
spectrum scope(B FFT).
the problem is the x axis is getting multiplied with the number of
i have 16 parallel blocks and each is a filter sampled at
the figure plotted is from 0
Digital Signal Processing :: 12.12.2006 04:31 :: rsrinivas :: Replies: 1 :: Views: 1766
I want to save a string/...
I'm not sure if I understand the requirement correctly ...
if you mean:
"i want to store 4/8/16/? bytes in a memory as a
parallel word and then read them out byte by byte"
- create a mux at the output of the memory;
- push byte by byte of your test word to a fifo usin
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.08.2008 04:51 :: j_andr :: Replies: 6 :: Views: 656
The pdf of your schematic is too coarse to be readable - what I figured out is a mux and an adc controlled by the PP.
The Stellaris? Family of ARM? Cortex™-M3 - LM3S2608 from TI supports 8 PWM; Freescale Semiconductor MAC7101 supports 16, STMicroelectronics STM32F103RC but these are all ARM devices. Infineon has a 8051 device - C509-L but I'
Microcontrollers :: 27.01.2010 14:43 :: egeorgiev :: Replies: 3 :: Views: 1356
I am planning to implement a 32-bit comparator on Xilinx FPGA, but the Xilinx FPGA has only 16 bit comparators only, is there any method to implement the 32-bit comparision using 2 16-bit comparisions
I want to use a 32-bit comparision in my RTL, so that it operates at high frequency range(more than 300Mhz). Can any one let me know t
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.02.2010 23:53 :: kalyansumankv :: Replies: 5 :: Views: 2997
you have 16 bit ADC so your range is 0-FFFF (0-65535) so you need only 5 digit 7-segment display
to display it
1> convert the hex code to decimal
2> break this in to individual fig (e.g. 12345 to 1,2,3,4,5) and save it in different reg.
3> write code to interface 5 digit 7-seg. display in mux fashion
4> convert the decimal code to 7-segmen
Microcontrollers :: 22.04.2010 02:55 :: piyush manavar :: Replies: 3 :: Views: 1151
The number of parameters doesn't match. According to the component declaration of mux8, 16 more bits are expected before the bit vector.
No idea what you are doing there.
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.03.2011 08:52 :: FvM :: Replies: 9 :: Views: 642
Hi guys, Im trying to implement Analogue FDM on top of my single carrier modulation (eg: QAM and QPSK) or Multi carrier modulation (eg: OFDM). For an example, I have two different pair of I and Q channels, where first pair is upconverted at 2.2 GHz and the next pair at say 2.7 GHz and them mux them together as in FDM.
I model them in matlab. The
Digital Signal Processing :: 26.04.2011 06:54 :: thavamaran :: Replies: 0 :: Views: 319
having built it in Quartus, it actually uses 16-1 muxes. as is. It isnt any better if you use an intermediate signal that is (counter-1)
You get much better/tidier results with a select. Directly using a select creates 8-1 muxes. using the intermediate counter-1 values uses only 4-1 (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.01.2012 11:50 :: TrickyDicky :: Replies: 6 :: Views: 562
69564 We are attempting to implement a 6-bit Flash ADC in 90nm CMOS technology using CADENCE. We require a 4-bit and 16-bit analog multiplexer (switch) but do not know the internal architecture of the same. Can someone please provide us with some help regarding the schematic of these components.
Electronic Elementary Questions :: 23.02.2012 01:18 :: ecatist :: Replies: 3 :: Views: 386
I believe the K70 supports 800x600 with high speed DAC so its parallel data in many formats. but 16 bit rgb
Embedded Systems and Real-Time OS :: 16.05.2012 05:17 :: SunnySkyguy :: Replies: 11 :: Views: 516
I am using Virtex 4 ML403 Evaluation Platform FPGA kit, on this kit a product of TI is used for audio data converting named LM4550. This IC work on the AC 97 CODEC which take serial data as an input and output. This IC work on different 16 bit registers to route data either through the ADC to DAC or connect input to the output.
ASIC Design Methodologies and Tools (Digital) :: 04.06.2013 03:45 :: muneebziaa :: Replies: 0 :: Views: 196