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What is the clock frequency which you have used in the project? One idea I can think of is, If you have a 2 MHz clock ( 0.5 us period) you can write the code for a two-bit counter and generate the pulses accordingly. So you'll transmit when count==0 and receive otherwise.
For your 2nd question the output is always 8 bits(from one of the 2 counters). This means that the lower 8 bits of the 16 bit counter are not used. For driving 8 bits of the output, you will need 8 2:1 muxes. Each mux will take one input from the 8 bit (...)
Step 1: Read the Fine Manual: Step 2: Actually read it.
Sir, I have generated netlist for a 16 bit counter using Encounter RTL the synthesis I set the clock as define_clock -period 3500 -name clk and in the timing report generated a have a positive slack - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk) capture
Initialization 1. set timer 0 as counter by using T0CKI clock input 2. set the corresponding bit in TRISx register which connects to T0CKI external clock to 1. 3. set an interrupt for timer0 in interrupt routine. Normal operation 1. when interrupt occurs add one to a static or global variable 2. update it to a LCD display or on UART or reset timer
Hello, Ill try to answer a question as I seem to only leech off the boards :D so forgive me if this isn't that helpful. I'm not that well versed in Verilog, I've mostly used VHDL but this might help you. 1) yes you are quite right you will need some denouncing for your switch these are common and you can find some code for it online. 2) have a po
1. The original code doesn't work as a counter in real hardware. 2. A state-of the art synthesis tool recognizes that the counter'high is restricted to 12 by the code, thus the fifth FF will be discarded and replaced by a constant 0 bit. Only 4 Latches, respectively D-FFs if using the working code suggested by shaiko. - -
Hi. I'm using Cadence Virtuoso with verilog ams. I pretend to build a counter with a 9 bit word. How can I check the value of the counter? Regards.
hi, Look at this image, it suggests a external asynchronous 1imer clock period of 60nanosec, ~16MHz. Use timer0 in conjunction with a timer0 interrupt clocked software counter to give a precise 1 second period for reading the Timer1 count. Also use timer1 interrupt to clock a software counter, this will give a 24 bit value [ (...)
Hi, 8bit vs 16 bit counter. An 8 bit counter counts 0...255 then overflows and restars with 0... A 16 bit counter counst 0...65535 then overflows and restars with 0... That's the difference. ********* What max counter frequency... Tells you (...)
This will end up being slower than the internal PWM hardware. Have you tried to see what F you need and what pre-scaler changes can be made to default counter clock? For standard Arduinos the system clock is 16MHz so that the timers are clocking at 250kHz by default. Phase correct 8-bit PWM mode takes 510 clocks to cycle and fast 8-bit (...)
hello, if you don't use interrupt , you can count number of elementary MCU Cycles. 1 cycle duration= 4/ (Fosc in MHz) in ?sec // if Fosc=16MHz void Tempo_1mS() { asm{ MOVLW 210 ; MOVWF _N1; // 8 bit counter ici: nop ; //1 nop ; nop ; nop ; nop ;
Guys, I'm beginner on VHDL and playing with VGA, I want to flip green to red with one statement of VHDL, is that possible ? I tried with combining : red <= '1' when vert_scan > 10 and vert_scan < 515 and horz_scan >= 100 and horz_scan < 350 else '0'; grn <= '1' when vert_scan > 20 and vert_scan < 525 and horz_scan >= 200 and horz_s
Hi I have one module like revolution counter which will count the revolution of motor.for that module 3 I/p are there clk,reset,motor angle of 15 bit when motor angle crosses 0 degrees in positive direction the count value increments one and it crosses 0 in neg direction it decrements 1....can u suggest logic or vhdl code for dis p.s there is
Hi I have one module like revolution counter which will count the revolution of motor.for that module 3 I/p are there clk,reset,motor angle of 15 bit when motor angle crosses 0 degrees in positive direction the count value increments one and it crosses 0 in neg direction it decrements 1....can u suggest logic or vhdl code for dis p.s there is n
Well, this is really not an easy task. First, there are two address counter: one for the DDRAM and the other for CGRAM. The above code reads that was written (modified) before. Other problem is that the first line end address and the second line start address are not consecutive (an so on). For example (16x2 LCD) the first line adresses are 00..
How to know the program counter value in any microcontroller? As I have read, Atmega8 have 12-bit program counter and PIC18F452 have 21-bit program counter. Program counter is one which holds the address of next instruction to be executed.but How to read the value of program (...)
i have made a sequential with 555 and 4017 and it has worked perfectly but i have problems with output the leds just pulse only but i want the led to be on till the circuit is complete i.e till last led and again the cycle will go on Unmesh You can either do it by adding SCR to the outputs of the 4017 like he
i ran lvs after placement... it showed open circuit error for output port ... those outputs which were instantiated in particular submodule... i had 1000 bit counter.. of 1000 bit nearly 40 bit were used to instantiate in particular submodule...y nly those output ports show open circuit error...netlist had no problems...but (...)
Hello fellow engineers/enthusiasts! I wrote the following program for an 8-bit modula N-bit counter, where N was a specified constant. I had to alter it a little bit due to my friend helping me, but what he altered I am confused about. My question is, why does he assign my cout to din within my for loop? Din isn't (...)
sorry for my basic question, but i am not entirely sure of capability of a CPLD. let's say i have two incoming signals and i want to know how much time passes between the two. so, when signal_1 goes high, it could trigger an 8-bit synchronous counter and the counter would stop when signal_2 goes high thus the measurement how how much (...)
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PORTA=%11011111 This takes pin A5 low. Digit zero common is on A0, so I would expect:PORTA=%11111110 (I assume that your BASIC compiler accepts binary numbers with bit 0 last, but I am not familiar with that compiler) You are probably over-driving the PIC outputs. Properly designed circuits have current limiting
Hello there, I have a FPGA board which has 4 seven segment elements having all the elements connected in parallel ie. element 'a' of all four units are in parallel and so on. I wanted to display four distinct characters in the four units viz 'F.P.g.A.'. Is there any way to do so. I tried the following way: Described a process A which is
well, the main problem is you havent included an arithmatic library that does arithmatic with std_ulogic_vector. There is no standard library that can do this. For a VHDL standard way of doing it, you need to used the unsigned type. Std_logic_vector or std_ulogic was not intended to be a numerical representation of a number- just a collection of B
Yes it is possible bt dividing the clock and count less is better approach to count higher counts.. I dont quite understand the message? Generating clocks from counters should always be avoided.
It seems to be a 2-bit counter with reset. In the CPLD's, each register is normally associated with a pin. gives the current value at the pins. .FB gives the current output at the internal register. This is much faster, so the timing will be better. It also works even if the associated pins are used as inputs.
Just to give you a hint, don't do one-hot, but use two-hot (if that's a thing). 11111100 11111001 11110011 etc That way if there is some metastability when you are crossing clock domains you can still get a meaningful result. The use case? The counter counts on a clock from one clock domain, but the count result is used in another clock
Your code doesn't describe a 4-bit Johnson counter. This is it QS(3 downto 0) <= Q(2 downto 0) & not (Q3);
I am using Atmega 8 16 bit counter. It works fine with the internal clock. But when tryin to use a signal as external clock on T1 pin on the uC the pin stays high all the time. DDRD &= ~(1 << DDD5); // Clear the PD5 pin // PD5 is now an input PORTD |= (1 << PORTD5); // turn On the Pull-up //
I have a 4bit counter in my vhdl code. when the count<8, I load data to a MS 8-bits of a registers and when the count>8, I load data to LS 8-bits of the register. In the synthesis report, why are 2 5-bit comparators inferred - one for less than and the other for greater/equal.
Hi, I'm an analogue engineer with no expeirnce in VHDL so i've grabbed a couple of books from the library and borrowed a terasic DE0 board to have a play around with. What I fundamentally want to do at this stage is to have a input pulse which is coming from a de bounced push button switch. On every rising edge of the s
Can any help me to design a 4 bit counter in vhdl.I want that counter gives 0 for count 0 t0 7 and 1 for 8 to 15.please reply fast
Storage devices 24xx have 2 communication modes built in I2C protocol: single byte ou Block. Decision about which to choose depends on data amount, but I suggest you start with the simplest one. For addressing each data on 24xx device you must access individually each byte. Just to check: The external processor you mentioned, work with C language
Use INT0 interrupt. When first rising edge is detected start timer and clear INT0IF bit. On 2nd rising interrupt stop timer. Use a counter inside isr which increments on every timerx interrupt. If timer interrupt you used was for say 20 us then counter will have number of timerx interrupts and the remaining time after the last timerx (...)
Can any one clearly define the address bus and data bus width required for a 32 bit processor? What about the program counter size?
I am trying to convert this vhdl testbench code to verilog testbench, kindly help me to convert this part of code slave_clkedge <= '1' when SLAVE_CPHA = SLAVE_CPOL else '0'; -- Define a 3-bit counter to count SCK edges and data into register so that parallel -- register is loaded. Use same clock edge tha
You can use some small MOSFET like si2301-sot23 or something like this to control the backlight. Arrange in your program some counter that will be erased every time when key is pressed. In case the counter reaches some value (value equals to desired delay) the backlight turns off. Another way to do it is by hardware delay.
hi all I'm want description of the timer counter avr which this timer counter 8 bit and consist of 3 part 1.counter 2.comprison system 3.waveform generation system by pwm designed in verilog help me thanks
In mikroC if counter is a 16 bit variable then _counter+0 ;low-byte _counter+1 ;high-byte I used MPLAB So : counter_1+1 and counter_1+0 ? how can I decrement them ? thanks
I want to store some values and then i want to retrieve first clock cycle, the output of a johnson counter is xor with the first seed bit and store these in consecutive location.then the johnson codewords xor with the second seed bit.This is repeated for all seed bits.Each one corresponds to a scan chain.This is given as the (...)
I am trying to build a 4-bit counter using LEDS. The count should update about every second. The up and down buttons on the board to control the direction of the count. The clock frequency is 100MHz therefore a clock divider should be used to slow it down. I am confused on how to implement the actual clock divider, I believe that I have the (...)
This is binary counter output sequence: 0000, 0001, 0010, 0011, 0100,... 0 , 1 , 2 , 3 , 4 ,... Just add a bit after LSB of the counter above, and tie it to 0. 00000, 00010, 00100, 00110, 01000,... 0 , 2 , 4 , 6 , 8 ,...
The ATtiny88 offers a clock prescaler which divides the system clock frequency by 8, 64, 256 or 1024 before input to Timer0 or Timer1. Reference: ATtiny48/88 Datasheet, Section: 13.1 Internal Clock Source, Page: 117 13.1 Internal Clock Source The Timer/counter can be clocke
I need to create a test bench for a mod 3 counter, however i am new to verilog and i have run into some problems... i already designed the circuit implementation and it compiled fine. The mod 3 counter is supposed to accept one input, and output the input % 3, treating the first input as the least siginificant bit. I'm not sure how (...)
Guys, How can I add 16 bits value into the memory, I have : LedTimer RES 2 movlw .255 movwf LedTimer how can I enter .300 into LedTimer ? Is it splitted into .150 ? Thanks
I have generated 0.5 Mhz clock from 50Mhz incoming clock by using synchronous counter clock enable and detecting the 00110001 pattern on the din input data and dout (output) I am getting is sync pulse as shown in image . but I want dout (output) to be at the same time as it detects the last bit in the pattern. Please check my
Hi guys I need 2GHZ 32 bit Synchronous Binary Up counter ( IC ) for my project . but I haven't found it yet then I decide to make it by myself . I need to know : Is it possible ? How much does it cost ? :roll: if you don't know ... than how you can build it?
If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse? A. 11101011 B. 00010111 C. 11110000 D. 00000000 When I did this, I got an answer A. What i did is right?? can anyone explain me? 1. For the 1st clk pulse, it would be, 01011111 2. For the 2nd clk pulse, it would be, 10101111 3. For