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414 Threads found on edaboard.com: 2 Bit Counter
dear all I have designed following code in verilog using Xilinx and it is not giving me the results. i have a 16 bit vector bit_s_row. i want to calculate 1's from index i = 0 up to the index B_addr. Please help me in resolving the issue. if(ibits_s_row==1) pop_count = pop_count +1'b1; else
I could not understand why they took the 18 bit counter because that would divide the frequency by 2^18 and not 2^16. I agree with your calculation. The refresh rate with an 18 bit counter is 200 Hz, not 800 Hz.
As mentioned in the title, which one has a larger area? What I am intended to do is to use shift register as a counter. E.g. If I want to count 8 times of certain operation, a 9-bit shift register is used to shift a binary '1' from index 0 to index 8. The operation stops when '1' reaches index 8. I can also do it with a 3-bit (...)
hello, I need a counter in verilogA that count the number of pulses in a window of 30KHz. So every 30KHz i need to visualize the number of pulses and reset the counter. Thanks for your help.
i need microcontroller with 3, 32 bit counter qei module, kindly suggest which can i go . regards kalyan
Hi , I'm trying to make a digital circuit that implements a 5-bit Gray code counter with priority reset. I've tried simulating the circuit on ISP lever Classic Project and doesn't work.I have to use GALp16v8 :( I have the following errors: Input file: 'gray.tt2' Device 'p16v8' Note 4161: Using device architecture type P16V8R. Warning 4034:Unab
4 Flip-flops means a 4-bit binary number. A 4-bit binary number can display numbers from 0b0000 (0) to 0b1111 (15). The prime numbers that are below 15 are: 1, 2, 3, 5, 7, 11, and 13. Build a truth table that has each of those as the input and the output is the next value in the sequence. Convert that truth table to a circuit using the JK flip-flo
the output assignment is 1 bit shorter than counter_WIDTH. Hence the error. BinaryCount(counter_WIDTH-1) = 1 bit BinaryCount(counter_WIDTH-2 downto 0) xor BinaryCount(counter_WIDTH-1 downto 1) = counter_WIDTH-2 bits hence length of output = (...)
Will there is be power and area difference for an 6 bit upcounter and 6 bit updown counter?
For a near constant frequency I would recommend a ring with large per-stage non-junction, non-MOS capacitors (as these will vary with temp and voltage as well) and a current starved inverter (i.e. current controlled). Then your transition is all about I=CdV/dt and I, C are fixed (to the quality of your current reference). Now if you had a low-TCR
Disclaimer: this is schoolwork, so I'm not sure if it's in the right segment. I need to write a frequency counter for a PIC16F870 microcontroller that can read frequencies from 0 to 255hz (8 bit, at least they had some mercy there...). This is for a school project where we have to build a capacitive pick-up and then output the RPM of a DC motor
hello i am working on an900 code but i am not getting exact frequency from formula as mention in an900 app note formula is CALCULATING TIMER0 RELOAD VALUE imer0 Reload Value = FFFFh ? but i am getting 35hz even i am compute the equation for 50hz thanks in advance
What is the clock frequency which you have used in the project? One idea I can think of is, If you have a 2 MHz clock ( 0.5 us period) you can write the code for a two-bit counter and generate the pulses accordingly. So you'll transmit when count==0 and receive otherwise.
For your 2nd question the output is always 8 bits(from one of the 2 counters). This means that the lower 8 bits of the 16 bit counter are not used. For driving 8 bits of the output, you will need 8 2:1 muxes. Each mux will take one input from the 8 bit (...)
Step 1: Read the Fine Manual: Step 2: Actually read it.
Sir, I have generated netlist for a 16 bit counter using Encounter RTL the synthesis I set the clock as define_clock -period 3500 -name clk and in the timing report generated a have a positive slack - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk) capture
Initialization 1. set timer 0 as counter by using T0CKI clock input 2. set the corresponding bit in TRISx register which connects to T0CKI external clock to 1. 3. set an interrupt for timer0 in interrupt routine. Normal operation 1. when interrupt occurs add one to a static or global variable 2. update it to a LCD display or on UART or reset timer
Hello, Ill try to answer a question as I seem to only leech off the boards :D so forgive me if this isn't that helpful. I'm not that well versed in Verilog, I've mostly used VHDL but this might help you. 1) yes you are quite right you will need some denouncing for your switch these are common and you can find some code for it online. 2) have a po
1. The original code doesn't work as a counter in real hardware. 2. A state-of the art synthesis tool recognizes that the counter'high is restricted to 12 by the code, thus the fifth FF will be discarded and replaced by a constant 0 bit. Only 4 Latches, respectively D-FFs if using the working code suggested by shaiko. - -
Hi. I'm using Cadence Virtuoso with verilog ams. I pretend to build a counter with a 9 bit word. How can I check the value of the counter? Regards.
hi, Look at this image, it suggests a external asynchronous 1imer clock period of 60nanosec, ~16MHz. Use timer0 in conjunction with a timer0 interrupt clocked software counter to give a precise 1 second period for reading the Timer1 count. Also use timer1 interrupt to clock a software counter, this will give a 24 bit value [ (...)
Hi, 8bit vs 16 bit counter. An 8 bit counter counts 0...255 then overflows and restars with 0... A 16 bit counter counst 0...65535 then overflows and restars with 0... That's the difference. ********* What max counter frequency... Tells you (...)
This will end up being slower than the internal PWM hardware. Have you tried to see what F you need and what pre-scaler changes can be made to default counter clock? For standard Arduinos the system clock is 16MHz so that the timers are clocking at 250kHz by default. Phase correct 8-bit PWM mode takes 510 clocks to cycle and fast 8-bit (...)
hello, if you don't use interrupt , you can count number of elementary MCU Cycles. 1 cycle duration= 4/ (Fosc in MHz) in ?sec // if Fosc=16MHz void Tempo_1mS() { asm{ MOVLW 210 ; MOVWF _N1; // 8 bit counter ici: nop ; //1 nop ; nop ; nop ; nop ;
Guys, I'm beginner on VHDL and playing with VGA, I want to flip green to red with one statement of VHDL, is that possible ? I tried with combining : red <= '1' when vert_scan > 10 and vert_scan < 515 and horz_scan >= 100 and horz_scan < 350 else '0'; grn <= '1' when vert_scan > 20 and vert_scan < 525 and horz_scan >= 200 and horz_s
Hi I have one module like revolution counter which will count the revolution of motor.for that module 3 I/p are there clk,reset,motor angle of 15 bit when motor angle crosses 0 degrees in positive direction the count value increments one and it crosses 0 in neg direction it decrements 1....can u suggest logic or vhdl code for dis p.s there is
Hi I have one module like revolution counter which will count the revolution of motor.for that module 3 I/p are there clk,reset,motor angle of 15 bit when motor angle crosses 0 degrees in positive direction the count value increments one and it crosses 0 in neg direction it decrements 1....can u suggest logic or vhdl code for dis p.s there is n
Well, this is really not an easy task. First, there are two address counter: one for the DDRAM and the other for CGRAM. The above code reads that was written (modified) before. Other problem is that the first line end address and the second line start address are not consecutive (an so on). For example (16x2 LCD) the first line adresses are 00..
How to know the program counter value in any microcontroller? As I have read, Atmega8 have 12-bit program counter and PIC18F452 have 21-bit program counter. Program counter is one which holds the address of next instruction to be executed.but How to read the value of program (...)
i have made a sequential with 555 and 4017 and it has worked perfectly but i have problems with output the leds just pulse only but i want the led to be on till the circuit is complete i.e till last led and again the cycle will go on Unmesh You can either do it by adding SCR to the outputs of the 4017 like he
i ran lvs after placement... it showed open circuit error for output port ... those outputs which were instantiated in particular submodule... i had 1000 bit counter.. of 1000 bit nearly 40 bit were used to instantiate in particular submodule...y nly those output ports show open circuit error...netlist had no problems...but (...)
Hello fellow engineers/enthusiasts! I wrote the following program for an 8-bit modula N-bit counter, where N was a specified constant. I had to alter it a little bit due to my friend helping me, but what he altered I am confused about. My question is, why does he assign my cout to din within my for loop? Din isn't (...)
sorry for my basic question, but i am not entirely sure of capability of a CPLD. let's say i have two incoming signals and i want to know how much time passes between the two. so, when signal_1 goes high, it could trigger an 8-bit synchronous counter and the counter would stop when signal_2 goes high thus the measurement how how much (...)
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PORTA=%11011111 This takes pin A5 low. Digit zero common is on A0, so I would expect:PORTA=%11111110 (I assume that your BASIC compiler accepts binary numbers with bit 0 last, but I am not familiar with that compiler) You are probably over-driving the PIC outputs. Properly designed circuits have current limiting
Hello there, I have a FPGA board which has 4 seven segment elements having all the elements connected in parallel ie. element 'a' of all four units are in parallel and so on. I wanted to display four distinct characters in the four units viz 'F.P.g.A.'. Is there any way to do so. I tried the following way: Described a process A which is
well, the main problem is you havent included an arithmatic library that does arithmatic with std_ulogic_vector. There is no standard library that can do this. For a VHDL standard way of doing it, you need to used the unsigned type. Std_logic_vector or std_ulogic was not intended to be a numerical representation of a number- just a collection of B
Yes it is possible bt dividing the clock and count less is better approach to count higher counts.. I dont quite understand the message? Generating clocks from counters should always be avoided.
It seems to be a 2-bit counter with reset. In the CPLD's, each register is normally associated with a pin. gives the current value at the pins. .FB gives the current output at the internal register. This is much faster, so the timing will be better. It also works even if the associated pins are used as inputs.
Just to give you a hint, don't do one-hot, but use two-hot (if that's a thing). 11111100 11111001 11110011 etc That way if there is some metastability when you are crossing clock domains you can still get a meaningful result. The use case? The counter counts on a clock from one clock domain, but the count result is used in another clock
Your code doesn't describe a 4-bit Johnson counter. This is it QS(3 downto 0) <= Q(2 downto 0) & not (Q3);
I am using Atmega 8 16 bit counter. It works fine with the internal clock. But when tryin to use a signal as external clock on T1 pin on the uC the pin stays high all the time. DDRD &= ~(1 << DDD5); // Clear the PD5 pin // PD5 is now an input PORTD |= (1 << PORTD5); // turn On the Pull-up //
I have a 4bit counter in my vhdl code. when the count<8, I load data to a MS 8-bits of a registers and when the count>8, I load data to LS 8-bits of the register. In the synthesis report, why are 2 5-bit comparators inferred - one for less than and the other for greater/equal.
Hi, I'm an analogue engineer with no expeirnce in VHDL so i've grabbed a couple of books from the library and borrowed a terasic DE0 board to have a play around with. What I fundamentally want to do at this stage is to have a input pulse which is coming from a de bounced push button switch. On every rising edge of the s
Can any help me to design a 4 bit counter in vhdl.I want that counter gives 0 for count 0 t0 7 and 1 for 8 to 15.please reply fast
Storage devices 24xx have 2 communication modes built in I2C protocol: single byte ou Block. Decision about which to choose depends on data amount, but I suggest you start with the simplest one. For addressing each data on 24xx device you must access individually each byte. Just to check: The external processor you mentioned, work with C language
Use INT0 interrupt. When first rising edge is detected start timer and clear INT0IF bit. On 2nd rising interrupt stop timer. Use a counter inside isr which increments on every timerx interrupt. If timer interrupt you used was for say 20 us then counter will have number of timerx interrupts and the remaining time after the last timerx (...)
Can any one clearly define the address bus and data bus width required for a 32 bit processor? What about the program counter size?
I am trying to convert this vhdl testbench code to verilog testbench, kindly help me to convert this part of code slave_clkedge <= '1' when SLAVE_CPHA = SLAVE_CPOL else '0'; -- Define a 3-bit counter to count SCK edges and data into register so that parallel -- register is loaded. Use same clock edge tha