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815 Threads found on edaboard.com: 2 Bit Counter
Hello nice guys, I am looking for VHDL source of the 24-bit counter for MAX3000A. I am a newbie in VHDL and MAX3000A, I just downloaded MAXplus II Basic from Altera web site. I will appreciate any help. visioneer
I'm trying to implement (in VHDL) a simple 3-bit counter that is loaded asynchronously. The CPU writes to an 8-bit register, in which 3 of those bits are the ones that are loaded into the counter. These 3-bits determine the duty cycle for the PWM output that is gated on the TC of the (...)
i think your mean is use short vector to test whole counter. synchronous or asynchronous counter? for asynchronous counter, maybe you need a 'select' pin for gated clock. for synchronous counter, perhaps you would separate it to 2 or 4 part, & gated 'enable' pin.
So your problem is "how to display", but you should give the information of your LCD driving method. Your LCD is spot-array type? then 2*16 is not sufficient to display digital numbers
I don't know verilog but asynchronous counter using JK FF shouldn't be too hard. Use 4 JK FF, all inputs 1. Clk0 <= Clock Clk1 <= Q0 Clk2 <= Q1 Clk3 <= Q2
In Verilog 2001: reg counter = 0; always @ (posedge clock) counter <= counter + 1;
i looking for an 8 bit counter ic. please help me.
Hi friends, I am wtiting VHDL code for one application. In that application, Two 8-bit Registers and one 16-bit counter will be there. The counter is a DOWN counter. The Register is loaded from external 8-bit Micro Processor(MP) and each Register is referenced with a separate (...)
Hi friends, I am writing VHDL code for one application. In that application, Two 8-bit Registers and one 16-bit counter will be there. The counter is a DOWN counter. The Register is loaded from external 8-bit Micro Processor(MP) and each Register is referenced with a separate (...)
//want a vhdl code for 16 bit counter with uprange and low rangei.e input are reset,count enable,considering with up range and low range. // SAME DESIGN IS MODIFIED ------ with same inputs but one more input is added mode IF mode then ....increment order by 1 if mode.....increment by2 if mode......increment by3 if mode
I need to design a 5 bit counter using 180nm Technology, the design should work at 2 GHz. How to divide the propagation delays among the various sub blocks of the counter so that my design meets the specification of 2GHz ? second question is : Suppose if the delay of a single D FF is 100ps (pico seconds) how to size the pmos and nmos (...)
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter4 is port(count:out std_logic_vector(3 downto 0); clk:in std_logic; reset:in std_logic); end counter4; architecture behav_counter4 of counter4 is component ha port (a: in std_logic; b: (...)
hi guys, i need to design a mod n bit counter for my project. how to reset the counter when the desired count. help me. thank you
Hi everyone Can anyone send/recommend me a Multisim model of a JK FF ripple 3-bit counter, prefereably with a RC reset switch? Is there any sample/example or even a similar 3bit JK FF ripple counter where i can refer to? I want to stimulate my workings in Multisim. Please help me, really appreciate. I really need an (...)
Have to do a 4-bit counter code in VHDL. It hads a 4 line input (A) a 10Hz CLK input a load input which is asynchronous a UP/Down (Down is Not down) and is synchronous a Reset input which is asynchronous a 2 line setect input line (x) a 2 line setect input line (y) a 4 line output (count) a one line output called (xeq Y) Does anyone kn
Have to do a 4-bit counter code in VHDL. It hads a 4 line input (A) a 10Hz CLK input a load input which is asynchronous a UP/Down (Down is Not down) and is synchronous a Reset input which is asynchronous a 2 line setect input line (x) a 2 line setect input line (y) a 4 line output (count) a one line output called (xeq Y) Does
hello can any one please help me with this problem: A verilog code for 4-bit up/down counter with jk flipflop that counts with step of 3,it means that it counts 0-3-6-9-12-15. I know this problem has got a very easy answer without using JK ff,but i just want to know the answer using JK flipflps. thanx
my only constraint is that the counter consists of 4 d flip flops and any 3 logic gates I will try to implement it to count to 1100 as you told me I hope it works Thanks alot :-) Added after 45 minutes: I am really sorry but can a counter count only even numbers?? I am really sorry for the disturb
hi can any body help me in writing 8 bit counter with carry and borrow. Please..... thanks
hi , I need VHDL code...for implementing a 4 bit binary counter from 2 bit binary counters. Basically when the terminal counter of 1st 2 bit binary counter is 11,then the 2nd 2 bit binary counter should start counting. I understnd tht (...)
Hello, I am trying to test a 4 bit counter eg 74160 for open/shorts and leakage currents Here is what I am thinking For the open shorts I ground the vcc and ground pins, I apply a 100uA current and measure the voltage on the pins For short/open to vcc I was thinking if the voltage stays between .2V and 1.5V, there is no short or open less t
Hi Can someone help me on how would you code the following: A synchronous 4 bit counter up performs the counting and the loading on the falling edge of the clock. The clear is an asynchronous input which resets the counter. The counter generates a carry Cout in state 15 if T = '1'. The counter (...)
Hello, I'm new to VHDL. I have designed the 2 bit up counter using JK flip flop. But the test bench is not producing the results i need. Please find attached the vhdl code and the test bench. --- 2 bit counter with JK FF library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment (...)
Hi guys...I have 4 bit synchronous counter that counts from 0000 to 1111. I want to make it truly random so that it may generate random number with no sequence... I don't want to any use programmable device to do the job.... So please tell me what can I do with this 4 bit counter to generate truly random number...
hi, Can any body help me to darw a state machine diagram for bit counter and 32bit shift register . Wher bit counter is connected to shift register and shift register get a data from fifo
first of all, there are syntax errors in the posted code. Secondly, the clock will be stuck at 'U' with the posted code. Please fix the code first, and come back with a clearer question. Done my code is working already i need a code that can monitor the output(count) making sure it increase by 1 and able to
Hello i am supposed to construct a precision 3ms gate time. My idea is to use four cascaded synchronous counters of the type sn74als161b. The CLK input is a 16MHz precision clock. here are my questions: Q#1: How do I calculate the overall propagation delay for the n-bit counter? 87813 Is it a summa of every s
process(clk,reset) begin if reset = '1' then q <= (others => '0'); elsif(rising_edge(clk))then if sel = '0' then q <= q+1; else q <= q+2; end if; end if; end process; Why q<=q+2 is doesn't make any sense... else part is not required in your code...OR apply high impedance when sel='1'. About your question...I think you nee
I would guess you can use 2- 74(XX)190 or 74(XX)191. Just replace XX with whatever IC technology your using ex. XX = LS. These are 4-bit up/down counters. Just have output of one input the other and you can go up to 8-bit. As far as the display? You can use 2- 74(XX)47's These are BCD to 7 segment decoders. You will need one for (...)
Try CD4521. It is 24-stage counter, but also provides outputs for 17, 18, 19, 20, 21, 22 and 23. Regards, IanP
Hi, AlexWan: My counter should work up to 2.5GHz
you can use the conventional phase frequency detector consisting of 2 flipflops and an and gate. you can find the information on it in most of the books. when you design digital gates, let's say an inverter, make the pmos 3 almost 3 times larger than the nmos so that you'll have same delays for 0>1 and 1>0 transitions and a threshold voltage of VDD
Use 74193 up/down counters and connect 4 of them in a cascade .. An example of 12-bit counter is below .. Regards, IanP
Make your own card counter. Take down the house with this gadget. Handheld card counter. It works by adding or subtracting manually-entered "event" counts to a common 8-bit counter No pass
HOw to implement a Progrmmable 8 bit counter using the Verilog HDL simulation . please send me any material or ebook which explains about its use and implmentation in verilog tool
Hi Maynor, this thread will help you anyway you can follow OR yourself. Just google
hi I wanna design "asynchronous" binary 8bit counter & 6 bit counter.8 bit counter will reset after 240(in hex-F0) & 6 bit counter will reset 40 bytes(28in hex).Can any1 plz give me VHDL code for it.it's very urgent. regards shraddha
Hello, there is a Parallel to serial block in my system which i make it with a 64*1 mux and 6-bit counter . I want the counter to stop when it reach "111111" and start again from "000000" when the input changed. I've tried many methods, something like that : process (data_in) begin if x2="111111" then --o/p of (...)
Because of the use of 2's complement, unsigned and signed counters are the exact same circuit. The difference will appear when the counter outputs are compared (<, <=, >, >=) in the same architecture.
Hi All, I have a question . I am searching to buy a scada and in its features says "32 bit counter". What exactly do a counter in scada systems ? Thank u in advance!!!
i want a vhdl code for 16 bit counter with uprange and low rangei.e input are reset,count enable,considering with up range and low range.
,upper_en,lower_en output:count
vhdl code for 8 bit counter with enable and terminal counter vhdl code for 16 bit counter using 8 bit counter whose terminal count will act as enable for 2nd counter
Hi friends, I was asked few questions in interview. 1. what is the difference between synthesis structure of 8 bit counter with signal and with variable? 2. How to design a circuit to detect a increment value (DO D1 D2 D3...) at rising_edge and falling_edge? mean at rising_edge Do, at falling edge D1 and so on... 3. Is it possible to d
hi all! Can anyone help me analyze this problem? I'm confused with this. Design a 3 bit counterlike circuit controlled by the input w. If w=1 then the counter adds 2 to its contents, wrapping around if the count reaches 8 or 9. Thus if the present state is 8 or 9, then the next state becomes 0 or 1, respectively. If w = 0 then the (...)
i want to make counter which have 2 inputs one is 4mhz clock secon is one bit input which keeps on set and reset at output i want only one bit our now if my input is low for 12 pulses thn my output shuld go low ,,, how can i do this???
Here is a 4 bit counter. No problem to remove the two lower flipflops to get a 2 bit counter.
I am designing a 4-bit counter with enable, load, reset, input data, output Y, and an overflow flag RCA. Here is my code: module counter(clk, data, Y, RCA, load, reset, enable); input clk; input data; input load; input reset; input enable; output Y = 4'b0000; output RCA = 0; reg Y;
hi i want to design a pll for three bands to get lock to the three differnt bands i have to get the divide ration as 64 to 148 for that i am using the dual modulas counters with prescalar 8/9 program counter as 5 bit counter and swallow counter as 3 bit counter can (...)
Hi I have problem: question: 4 bit binary counter(0 to 3) , counts increments from 0 to 15 in clock A domain. now the count has to be communicated in the other clock domain clock B using edge detection circuits. what will be the ciruit will it use to detect count 2-3 . & what will be the ciruit will it use to detect count 15-0 .