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Hello nice guys, I am looking for VHDL source of the 24-bit counter for MAX3000A. I am a newbie in VHDL and MAX3000A, I just downloaded MAXplus II Basic from Altera web site. I will appreciate any help. visioneer
I'm trying to implement (in VHDL) a simple 3-bit counter that is loaded asynchronously. The CPU writes to an 8-bit register, in which 3 of those bits are the ones that are loaded into the counter. These 3-bits determine the duty cycle for the PWM output that is gated on the TC of the (...)
i think your mean is use short vector to test whole counter. synchronous or asynchronous counter? for asynchronous counter, maybe you need a 'select' pin for gated clock. for synchronous counter, perhaps you would separate it to 2 or 4 part, & gated 'enable' pin.
So your problem is "how to display", but you should give the information of your LCD driving method. Your LCD is spot-array type? then 2*16 is not sufficient to display digital numbers
I don't know verilog but asynchronous counter using JK FF shouldn't be too hard. Use 4 JK FF, all inputs 1. Clk0 <= Clock Clk1 <= Q0 Clk2 <= Q1 Clk3 <= Q2
In Verilog 2001: reg counter = 0; always @ (posedge clock) counter <= counter + 1;
i looking for an 8 bit counter ic. please help me.
Hi friends, I am wtiting VHDL code for one application. In that application, Two 8-bit Registers and one 16-bit counter will be there. The counter is a DOWN counter. The Register is loaded from external 8-bit Micro Processor(MP) and each Register is referenced with a separate (...)
Hi friends, I am writing VHDL code for one application. In that application, Two 8-bit Registers and one 16-bit counter will be there. The counter is a DOWN counter. The Register is loaded from external 8-bit Micro Processor(MP) and each Register is referenced with a separate (...)
//want a vhdl code for 16 bit counter with uprange and low rangei.e input are reset,count enable,considering with up range and low range. // SAME DESIGN IS MODIFIED ------ with same inputs but one more input is added mode IF mode then ....increment order by 1 if mode.....increment by2 if mode......increment by3 if mode
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter4 is port(count:out std_logic_vector(3 downto 0); clk:in std_logic; reset:in std_logic); end counter4; architecture behav_counter4 of counter4 is component ha port (a: in std_logic; b: (...)
hi guys, i need to design a mod n bit counter for my project. how to reset the counter when the desired count. help me. thank you
Hi everyone Can anyone send/recommend me a Multisim model of a JK FF ripple 3-bit counter, prefereably with a RC reset switch? Is there any sample/example or even a similar 3bit JK FF ripple counter where i can refer to? I want to stimulate my workings in Multisim. Please help me, really appreciate. I really need an (...)
Have to do a 4-bit counter code in VHDL. It hads a 4 line input (A) a 10Hz CLK input a load input which is asynchronous a UP/Down (Down is Not down) and is synchronous a Reset input which is asynchronous a 2 line setect input line (x) a 2 line setect input line (y) a 4 line output (count) a one line output called (xeq Y) Does anyone kn
Have to do a 4-bit counter code in VHDL. It hads a 4 line input (A) a 10Hz CLK input a load input which is asynchronous a UP/Down (Down is Not down) and is synchronous a Reset input which is asynchronous a 2 line setect input line (x) a 2 line setect input line (y) a 4 line output (count) a one line output called (xeq Y) Does
hello can any one please help me with this problem: A verilog code for 4-bit up/down counter with jk flipflop that counts with step of 3,it means that it counts 0-3-6-9-12-15. I know this problem has got a very easy answer without using JK ff,but i just want to know the answer using JK flipflps. thanx
my only constraint is that the counter consists of 4 d flip flops and any 3 logic gates I will try to implement it to count to 1100 as you told me I hope it works Thanks alot :-) Added after 45 minutes: I am really sorry but can a counter count only even numbers?? I am really sorry for the disturb
hi can any body help me in writing 8 bit counter with carry and borrow. Please..... thanks
hi , I need VHDL code...for implementing a 4 bit binary counter from 2 bit binary counters. Basically when the terminal counter of 1st 2 bit binary counter is 11,then the 2nd 2 bit binary counter should start counting. I understnd tht (...)
Hello, I am trying to test a 4 bit counter eg 74160 for open/shorts and leakage currents Here is what I am thinking For the open shorts I ground the vcc and ground pins, I apply a 100uA current and measure the voltage on the pins For short/open to vcc I was thinking if the voltage stays between .2V and 1.5V, there is no short or open less t
Hi Can someone help me on how would you code the following: A synchronous 4 bit counter up performs the counting and the loading on the falling edge of the clock. The clear is an asynchronous input which resets the counter. The counter generates a carry Cout in state 15 if T = '1'. The counter (...)
Hello, I'm new to VHDL. I have designed the 2 bit up counter using JK flip flop. But the test bench is not producing the results i need. Please find attached the vhdl code and the test bench. --- 2 bit counter with JK FF library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment (...)
Hi guys...I have 4 bit synchronous counter that counts from 0000 to 1111. I want to make it truly random so that it may generate random number with no sequence... I don't want to any use programmable device to do the job.... So please tell me what can I do with this 4 bit counter to generate truly random number...
hi, Can any body help me to darw a state machine diagram for bit counter and 32bit shift register . Wher bit counter is connected to shift register and shift register get a data from fifo
first of all, there are syntax errors in the posted code. Secondly, the clock will be stuck at 'U' with the posted code. Please fix the code first, and come back with a clearer question. Done my code is working already i need a code that can monitor the output(count) making sure it increase by 1 and able to
Hello i am supposed to construct a precision 3ms gate time. My idea is to use four cascaded synchronous counters of the type sn74als161b. The CLK input is a 16MHz precision clock. here are my questions: Q#1: How do I calculate the overall propagation delay for the n-bit counter? 87813 Is it a summa of every s
process(clk,reset) begin if reset = '1' then q <= (others => '0'); elsif(rising_edge(clk))then if sel = '0' then q <= q+1; else q <= q+2; end if; end if; end process; Why q<=q+2 is doesn't make any sense... else part is not required in your code...OR apply high impedance when sel='1'. About your question...I think you nee
I am trying to build a 4-bit counter using LEDS. The count should update about every second. The up and down buttons on the board to control the direction of the count. The clock frequency is 100MHz therefore a clock divider should be used to slow it down. I am confused on how to implement the actual clock divider, I believe that I have the (...)
I am using Atmega 8 16 bit counter. It works fine with the internal clock. But when tryin to use a signal as external clock on T1 pin on the uC the pin stays high all the time. DDRD &= ~(1 << DDD5); // Clear the PD5 pin // PD5 is now an input PORTD |= (1 << PORTD5); // turn On the Pull-up //
Use 74193 up/down counters and connect 4 of them in a cascade .. An example of 12-bit counter is below .. Regards, IanP
i want a vhdl code for 16 bit counter with uprange and low rangei.e input are reset,count enable,considering with up range and low range.
hi all! Can anyone help me analyze this problem? I'm confused with this. Design a 3 bit counterlike circuit controlled by the input w. If w=1 then the counter adds 2 to its contents, wrapping around if the count reaches 8 or 9. Thus if the present state is 8 or 9, then the next state becomes 0 or 1, respectively. If w = 0 then the (...)
hi i want to design a pll for three bands to get lock to the three differnt bands i have to get the divide ration as 64 to 148 for that i am using the dual modulas counters with prescalar 8/9 program counter as 5 bit counter and swallow counter as 3 bit counter can (...)
I need to convert a 50 MHz / 27 MHz clock to a 1 Hz clock using cascading counters. I have to use the DE2 board to build a counter of transitions. The counter increments its count at the clock every time the input changes from 1 in the previous cycle to zero in the current cycle. The out- put is the highest bit. The inputs (...)
These links may help 555 Oscillator and Decade counter - doc00020 The 4017B Decade counter Alex
Hi All, Can anybody help me in answering this question. How can i design 3-bit Binary counter From 2-bit Binary counter.
Have you check Altera's website: Verilog HDL: Parameterized counter Join the Verilog HDL Group there are numerous links to free and open source cores.
I am corrently trying to solve the question "So far so good. The general thinking was OK, but there was a major problem with the circuit, can you discover what it was?" The problem can be seen here: Real World Examples #5 – Clock Divider by 5
Can any help me to design a 4 bit counter in vhdl.I want that counter gives 0 for count 0 t0 7 and 1 for 8 to 15.please reply fast
Hi, I'm an analogue engineer with no expeirnce in VHDL so i've grabbed a couple of books from the library and borrowed a terasic DE0 board to have a play around with. What I fundamentally want to do at this stage is to have a input pulse which is coming from a de bounced push button switch. On every rising edge of the s
I would guess you can use 2- 74(XX)190 or 74(XX)191. Just replace XX with whatever IC technology your using ex. XX = LS. These are 4-bit up/down counters. Just have output of one input the other and you can go up to 8-bit. As far as the display? You can use 2- 74(XX)47's These are BCD to 7 segment decoders. You will need one for (...)
Try CD4521. It is 24-stage counter, but also provides outputs for 17, 18, 19, 20, 21, 22 and 23. Regards, IanP
Hi, AlexWan: My counter should work up to 2.5GHz
you can use the conventional phase frequency detector consisting of 2 flipflops and an and gate. you can find the information on it in most of the books. when you design digital gates, let's say an inverter, make the pmos 3 almost 3 times larger than the nmos so that you'll have same delays for 0>1 and 1>0 transitions and a threshold voltage of VDD
Make your own card counter. Take down the house with this gadget. Handheld card counter. It works by adding or subtracting manually-entered "event" counts to a common 8-bit counter No pass
HOw to implement a Progrmmable 8 bit counter using the Verilog HDL simulation . please send me any material or ebook which explains about its use and implmentation in verilog tool
Hi Maynor, this thread will help you anyway you can follow OR yourself. Just google
hi I wanna design "asynchronous" binary 8bit counter & 6 bit counter.8 bit counter will reset after 240(in hex-F0) & 6 bit counter will reset 40 bytes(28in hex).Can any1 plz give me VHDL code for it.it's very urgent. regards shraddha
Try to change your code to this : if x2 <= "111111" then x3 <= '1';
Because of the use of 2's complement, unsigned and signed counters are the exact same circuit. The difference will appear when the counter outputs are compared (<, <=, >, >=) in the same architecture.