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426 Threads found on 2 Bit Counter
Assuming P3.0-P3.3 is a binary number (with P3.0 as the MSB) then the MOD value would be defined as: P3.0 * 2^3 + P3.1 * 2^2 + P3.2 * 2^1 + P3.3 2^0
Hi KlausST, Actually I captured values from capture buffer (IC2BUF) and then I made the calculations as per my code. Here is my input capture function unsigned int timePeriod; float freq = 0; /************************** main function *********************************/ main() { uart1_init(); timer_init(); IC_INIT();
Hello! :-) I am a just-graduated engineer and right now I am doing an internship in Japan. My task is to develop a SMPTE time code decoder on a FPGA ALTERA DE0 TERASIC and display the time-code on the 7-segment displays. I have attended two courses at the university about digital design, but up to now I have no practical experience and unfortunat
Hi. I'd like to make a 10-bit Up/Down counter using Verilog in Altera DE1. It's a decimal counter that counts from 0-1023 with DIR, LOAD and RESET. Reset will get the counter back to 0. DIR will specify if it's going up or down. I have here a code where it will simply count from 0-15(F). How do you think I can modify (...)
Hi everyone, I am designing a 4 bit up and down counter that when counting up has a programmable modulo value. Here is my code for the whole counter with modulo but I keep getting errors that I don't know how to solve. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.A
Hi everyone, I am making a 4 bit counter that can count up or down to a modulo value I can set using switches on the board. Here is my code and the errors I am getting. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter4bit is port( (...)
I need to write a testbench for any example netlist so for this i need a netlist with sdf file.Any links for the netlist and sdf files download will be of great help.
You can find information about debouncing block debouncing block from that link has 3 FF's (registers) plus a 19-bit counter, in total 22 registers, per input. It is important to
You could try to use a 74HC5555, it is a 555 with a internal divider for long time periods. If you set it to 17 bit (131,072) and use a 1 KHz oscillator you would get 2.184 hours, 1.1 KHz would be 1.96 hours. You would use the Q output to drive Bradtherad's decade counter and use the 74HC5555 non-retriggerable mode. Meaning that the 2 hour per
hi i want to get 16 bit data from timer/counter1 (as event counter) to portb and c in CCS. how can i do it? i did it by timer 0 as counter. by following SETUP_TIMER_0(RTCC_EXT_H_TO_L|RTCC_8_bit|RTCC_DIV_2); SET_TIMER0(0); WHILE(1) { OUTPUT_B(GET_TIMER0()); } one (...)
hello guys i have been implementing radix2^2 sdf, i have given butterfly input as 16 bit counter for the 1st stage, my expected ans are 24,28.....8-16j,10-18j, these are my expected ans,,, but im getting real part as 24, 28.....-8,-8. imag part is -8,-8.....24,28, are my values a valid one??? what should i expect in imag part if there is no imag p
The code in post #1 isn't related to UART, just sending 8-bit words. It's neither implementing a 32-bit counter. Apparently you copied a third parties code that is loosely related to the thread topic, but doesn't actually help to solve it. Writing a programmable logic design starts with a specification: - input and output signals - (...)
Please elaborate... The write clock domain is 10 times faster than the read clock domain. Suppose no writes occurred for a long time (the value of the counter on the write domain is the same as in the read domain) and it's decimal 3 (which is 00000010 in code gray) Now, 2 consecutive writes occur - the counter value on the write side increments ver
dear all I have designed following code in verilog using Xilinx and it is not giving me the results. i have a 16 bit vector bit_s_row. i want to calculate 1's from index i = 0 up to the index B_addr. Please help me in resolving the issue. if(ibits_s_row==1) pop_count = pop_count +1'b1; else
I was going through a verilog code for time multiplexing with LED patterns. I am attaching the screenshot of the problem. I could not understand why they took the 18 bit counter because that would divide the frequency by 2^18 and not 2^16.
As mentioned in the title, which one has a larger area? What I am intended to do is to use shift register as a counter. E.g. If I want to count 8 times of certain operation, a 9-bit shift register is used to shift a binary '1' from index 0 to index 8. The operation stops when '1' reaches index 8. I can also do it with a 3-bit (...)
hello, I need a counter in verilogA that count the number of pulses in a window of 30KHz. So every 30KHz i need to visualize the number of pulses and reset the counter. Thanks for your help.
i need microcontroller with 3, 32 bit counter qei module, kindly suggest which can i go . regards kalyan
4 Flip-flops means a 4-bit binary number. A 4-bit binary number can display numbers from 0b0000 (0) to 0b1111 (15). The prime numbers that are below 15 are: 1, 2, 3, 5, 7, 11, and 13. Build a truth table that has each of those as the input and the output is the next value in the sequence. Convert that truth table to a circuit using the JK flip-flo
the output assignment is 1 bit shorter than counter_WIDTH. Hence the error. BinaryCount(counter_WIDTH-1) = 1 bit BinaryCount(counter_WIDTH-2 downto 0) xor BinaryCount(counter_WIDTH-1 downto 1) = counter_WIDTH-2 bits hence length of output = (...)
Will there is be power and area difference for an 6 bit upcounter and 6 bit updown counter?
For a near constant frequency I would recommend a ring with large per-stage non-junction, non-MOS capacitors (as these will vary with temp and voltage as well) and a current starved inverter (i.e. current controlled). Then your transition is all about I=CdV/dt and I, C are fixed (to the quality of your current reference). Now if you had a low-TCR
Disclaimer: this is schoolwork, so I'm not sure if it's in the right segment. I need to write a frequency counter for a PIC16F870 microcontroller that can read frequencies from 0 to 255hz (8 bit, at least they had some mercy there...). This is for a school project where we have to build a capacitive pick-up and then output the RPM of a DC motor
hello i am working on an900 code but i am not getting exact frequency from formula as mention in an900 app note formula is CALCULATING TIMER0 RELOAD VALUE imer0 Reload Value = FFFFh ? but i am getting 35hz even i am compute the equation for 50hz thanks in advance
What is the clock frequency which you have used in the project? One idea I can think of is, If you have a 2 MHz clock ( 0.5 us period) you can write the code for a two-bit counter and generate the pulses accordingly. So you'll transmit when count==0 and receive otherwise.
For your 2nd question the output is always 8 bits(from one of the 2 counters). This means that the lower 8 bits of the 16 bit counter are not used. For driving 8 bits of the output, you will need 8 2:1 muxes. Each mux will take one input from the 8 bit (...)
Step 1: Read the Fine Manual: Step 2: Actually read it.
Sir, I have generated netlist for a 16 bit counter using Encounter RTL the synthesis I set the clock as define_clock -period 3500 -name clk and in the timing report generated a have a positive slack - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk) capture
Initialization 1. set timer 0 as counter by using T0CKI clock input 2. set the corresponding bit in TRISx register which connects to T0CKI external clock to 1. 3. set an interrupt for timer0 in interrupt routine. Normal operation 1. when interrupt occurs add one to a static or global variable 2. update it to a LCD display or on UART or reset timer
Hello, Ill try to answer a question as I seem to only leech off the boards :D so forgive me if this isn't that helpful. I'm not that well versed in Verilog, I've mostly used VHDL but this might help you. 1) yes you are quite right you will need some denouncing for your switch these are common and you can find some code for it online. 2) have a po
1. The original code doesn't work as a counter in real hardware. 2. A state-of the art synthesis tool recognizes that the counter'high is restricted to 12 by the code, thus the fifth FF will be discarded and replaced by a constant 0 bit. Only 4 Latches, respectively D-FFs if using the working code suggested by shaiko. - -
Hi. I'm using Cadence Virtuoso with verilog ams. I pretend to build a counter with a 9 bit word. How can I check the value of the counter? Regards.
hi, Look at this image, it suggests a external asynchronous 1imer clock period of 60nanosec, ~16MHz. Use timer0 in conjunction with a timer0 interrupt clocked software counter to give a precise 1 second period for reading the Timer1 count. Also use timer1 interrupt to clock a software counter, this will give a 24 bit value [ (...)
Hi, 8bit vs 16 bit counter. An 8 bit counter counts 0...255 then overflows and restars with 0... A 16 bit counter counst 0...65535 then overflows and restars with 0... That's the difference. ********* What max counter frequency... Tells you (...)
I want to write a code in C for microcontroller ATMEGA128L so that i can replace the complete functionality of TL494 IC with the code. . Data sheet of Being a beginner in embedded programming i am a bit confused how and where to sta
hello, if you don't use interrupt , you can count number of elementary MCU Cycles. 1 cycle duration= 4/ (Fosc in MHz) in ?sec // if Fosc=16MHz void Tempo_1mS() { asm{ MOVLW 210 ; MOVWF _N1; // 8 bit counter ici: nop ; //1 nop ; nop ; nop ; nop ;
Guys, I'm beginner on VHDL and playing with VGA, I want to flip green to red with one statement of VHDL, is that possible ? I tried with combining : red <= '1' when vert_scan > 10 and vert_scan < 515 and horz_scan >= 100 and horz_scan < 350 else '0'; grn <= '1' when vert_scan > 20 and vert_scan < 525 and horz_scan >= 200 and horz_s
Hi I have one module like revolution counter which will count the revolution of motor.for that module 3 I/p are there clk,reset,motor angle of 15 bit when motor angle crosses 0 degrees in positive direction the count value increments one and it crosses 0 in neg direction it decrements 1....can u suggest logic or vhdl code for dis p.s there is
Hi I have one module like revolution counter which will count the revolution of motor.for that module 3 I/p are there clk,reset,motor angle of 15 bit when motor angle crosses 0 degrees in positive direction the count value increments one and it crosses 0 in neg direction it decrements 1....can u suggest logic or vhdl code for dis p.s there is n
Well, this is really not an easy task. First, there are two address counter: one for the DDRAM and the other for CGRAM. The above code reads that was written (modified) before. Other problem is that the first line end address and the second line start address are not consecutive (an so on). For example (16x2 LCD) the first line adresses are 00..
How to know the program counter value in any microcontroller? As I have read, Atmega8 have 12-bit program counter and PIC18F452 have 21-bit program counter. Program counter is one which holds the address of next instruction to be executed.but How to read the value of program (...)
i have made a sequential with 555 and 4017 and it has worked perfectly but i have problems with output the leds just pulse only but i want the led to be on till the circuit is complete i.e till last led and again the cycle will go on Unmesh You can either do it by adding SCR to the outputs of the 4017 like he
i ran lvs after placement... it showed open circuit error for output port ... those outputs which were instantiated in particular submodule... i had 1000 bit counter.. of 1000 bit nearly 40 bit were used to instantiate in particular submodule...y nly those output ports show open circuit error...netlist had no problems...but (...)
Hello fellow engineers/enthusiasts! I wrote the following program for an 8-bit modula N-bit counter, where N was a specified constant. I had to alter it a little bit due to my friend helping me, but what he altered I am confused about. My question is, why does he assign my cout to din within my for loop? Din isn't (...)
sorry for my basic question, but i am not entirely sure of capability of a CPLD. let's say i have two incoming signals and i want to know how much time passes between the two. so, when signal_1 goes high, it could trigger an 8-bit synchronous counter and the counter would stop when signal_2 goes high thus the measurement how how much (...)
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PORTA=%11011111 This takes pin A5 low. Digit zero common is on A0, so I would expect:PORTA=%11111110 (I assume that your BASIC compiler accepts binary numbers with bit 0 last, but I am not familiar with that compiler) You are probably over-driving the PIC outputs. Properly designed circuits have current limiting
Hello there, I have a FPGA board which has 4 seven segment elements having all the elements connected in parallel ie. element 'a' of all four units are in parallel and so on. I wanted to display four distinct characters in the four units viz 'F.P.g.A.'. Is there any way to do so. I tried the following way: Described a process A which is
well, the main problem is you havent included an arithmatic library that does arithmatic with std_ulogic_vector. There is no standard library that can do this. For a VHDL standard way of doing it, you need to used the unsigned type. Std_logic_vector or std_ulogic was not intended to be a numerical representation of a number- just a collection of B