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436 Threads found on 2 Bit Counter
I am wondering how to draw a state transition diagram for a two bit counter with the same reset capabilities of a register. I am also wondering if this reset signal is asynchronous what does this change about the output function and is it a Mealy Machine?
Hi, I am trying to debug my ALU design in FPGA. I am using trigger immediate option after downloading the bit stream to FPGA. But the chipscope never displays the signal values starting from program counter=0 and the waveform starts from some other value of program counter. How to resolve this issue, I need to capture rea
the normal method for dealing with pushbutton IO in FPGAs would be to write a debouncing circuit. This works by sampling the button with a clock. Typically two registers in a row to form a "synchronizer". This dramatically reduces the chance of "metastability" -- that the button will be changing at the exact instant of the clock edge. The actua
When assigning integer literals to bit vectors in Verilog, you'll usually get a warning that a 32 bit value has been truncated. Personally, I won't expect the "lazy" assignment in a tutorial.
Hi I am trying to design a Mod 6 3-bit D-type asynchronous down counter using Pspice and I am having difficulty with the Nand gate in order to make the count go from 5-0. In its present state it is counting from 7-0 and I know with the addition of adding a NAND gate I can reduce the count to the desire 5-0 but I have no idea how to connect the g
For clarification: are you using two 74192 and two 7447 devices? One counter can only reach 15 maximum and the 7447 can only drive one digit. We would have to know how you have them connected to be sure but the principle is to gate together the bits that make the number 19 (0001 1001) and when that bit pattern is matched, drive the "load" (...)
I had a time running finesim. This tool allows me to do confirm a timing violation on STA report whether we can ignore or not. You can try it because it can produce the waveform, and you can add detailed command to get the logic level ( voltage ) of any signal/node anytime. Sorry, I can not recall all scripting and syntax
There are 2 ways to design synchronous FIFO that I know: 1. Using n+1 bit counters for write pointer and read pointer. In this case, since it is 8 location FIFO, you can use 3+1 = 4 bit counter. To detect full and empty is simple: FULL: WP-RP = 4'b1000 EMPTY: WP-RP=4'b0000 We cannot decide full and empty conditions (...)
Hello,there I am working on a project taking measurement of -DC Voltage -DC Current -AC Voltage -AC voltage frequency I have used the Timer O for reading the frequency but the problem now is that I can`t read the frequency using Timer O(T0CKI pin of the PIC16F877A). Could you please help me to deal with codes so that I can read that par
It will count from 0x0000 to 0x0FFF three times, then jump to 0x3000, and go from there to 0x3FFF and on to 0x0000. It's as if bit 12 is stuck to bit 13. Clarifies that the counter is counting correct internally, but you don't see bit 12 and 13 unless both are one. That's unlikely to happen by logic operation, more likely (...)
Assuming P3.0-P3.3 is a binary number (with P3.0 as the MSB) then the MOD value would be defined as: P3.0 * 2^3 + P3.1 * 2^2 + P3.2 * 2^1 + P3.3 2^0
Hi KlausST, Actually I captured values from capture buffer (IC2BUF) and then I made the calculations as per my code. Here is my input capture function unsigned int timePeriod; float freq = 0; /************************** main function *********************************/ main() { uart1_init(); timer_init(); IC_INIT();
You should probably have range checks on the CNT value. Maybe SHORT = 2-4 and LONG = 5-7. Restart the decoder if you get a value outside of these ranges. Do the development and debugging with a simulator and a test bench (the Altera version of Modelsim). It is a waste of time to do all of the debugging on the real hardware. When you go to the
How do you think I can modify it to make it count from 0-1023 and make it an up/down counter? Not at all. The actual counter code is in module cntXXM, not shown in your post. The posted code is unrelated to your question. Google gives pretty much hits for "Verilog up-down counter", I believe examples can be found also in many Ver
Hi everyone, I am designing a 4 bit up and down counter that when counting up has a programmable modulo value. Here is my code for the whole counter with modulo but I keep getting errors that I don't know how to solve. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.A
Hi everyone, I am making a 4 bit counter that can count up or down to a modulo value I can set using switches on the board. Here is my code and the errors I am getting. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter4bit is port( (...)
I need to write a testbench for any example netlist so for this i need a netlist with sdf file.Any links for the netlist and sdf files download will be of great help.
You can find information about debouncing block debouncing block from that link has 3 FF's (registers) plus a 19-bit counter, in total 22 registers, per input. It is important to
You could try to use a 74HC5555, it is a 555 with a internal divider for long time periods. If you set it to 17 bit (131,072) and use a 1 KHz oscillator you would get 2.184 hours, 1.1 KHz would be 1.96 hours. You would use the Q output to drive Bradtherad's decade counter and use the 74HC5555 non-retriggerable mode. Meaning that the 2 hour per
hi i want to get 16 bit data from timer/counter1 (as event counter) to portb and c in CCS. how can i do it? i did it by timer 0 as counter. by following SETUP_TIMER_0(RTCC_EXT_H_TO_L|RTCC_8_bit|RTCC_DIV_2); SET_TIMER0(0); WHILE(1) { OUTPUT_B(GET_TIMER0()); } one (...)
hello guys i have been implementing radix2^2 sdf, i have given butterfly input as 16 bit counter for the 1st stage, my expected ans are 24,28.....8-16j,10-18j, these are my expected ans,,, but im getting real part as 24, 28.....-8,-8. imag part is -8,-8.....24,28, are my values a valid one??? what should i expect in imag part if there is no imag p
The code in post #1 isn't related to UART, just sending 8-bit words. It's neither implementing a 32-bit counter. Apparently you copied a third parties code that is loosely related to the thread topic, but doesn't actually help to solve it. Writing a programmable logic design starts with a specification: - input and output signals - (...)
In the present example, transition from 3 (gray 010) to 5 (gray 111), the problem is that you may also see an intermediate gray code of 011 (value 2), which is outside the transition range.
dear all I have designed following code in verilog using Xilinx and it is not giving me the results. i have a 16 bit vector bit_s_row. i want to calculate 1's from index i = 0 up to the index B_addr. Please help me in resolving the issue. if(ibits_s_row==1) pop_count = pop_count +1'b1; else
I could not understand why they took the 18 bit counter because that would divide the frequency by 2^18 and not 2^16. I agree with your calculation. The refresh rate with an 18 bit counter is 200 Hz, not 800 Hz.
As mentioned in the title, which one has a larger area? What I am intended to do is to use shift register as a counter. E.g. If I want to count 8 times of certain operation, a 9-bit shift register is used to shift a binary '1' from index 0 to index 8. The operation stops when '1' reaches index 8. I can also do it with a 3-bit (...)
hello, I need a counter in verilogA that count the number of pulses in a window of 30KHz. So every 30KHz i need to visualize the number of pulses and reset the counter. Thanks for your help.
i need microcontroller with 3, 32 bit counter qei module, kindly suggest which can i go . regards kalyan
4 Flip-flops means a 4-bit binary number. A 4-bit binary number can display numbers from 0b0000 (0) to 0b1111 (15). The prime numbers that are below 15 are: 1, 2, 3, 5, 7, 11, and 13. Build a truth table that has each of those as the input and the output is the next value in the sequence. Convert that truth table to a circuit using the JK flip-flo
the output assignment is 1 bit shorter than counter_WIDTH. Hence the error. BinaryCount(counter_WIDTH-1) = 1 bit BinaryCount(counter_WIDTH-2 downto 0) xor BinaryCount(counter_WIDTH-1 downto 1) = counter_WIDTH-2 bits hence length of output = (...)
Will there is be power and area difference for an 6 bit upcounter and 6 bit updown counter?
For a near constant frequency I would recommend a ring with large per-stage non-junction, non-MOS capacitors (as these will vary with temp and voltage as well) and a current starved inverter (i.e. current controlled). Then your transition is all about I=CdV/dt and I, C are fixed (to the quality of your current reference). Now if you had a low-TCR
Disclaimer: this is schoolwork, so I'm not sure if it's in the right segment. I need to write a frequency counter for a PIC16F870 microcontroller that can read frequencies from 0 to 255hz (8 bit, at least they had some mercy there...). This is for a school project where we have to build a capacitive pick-up and then output the RPM of a DC motor
hello i am working on an900 code but i am not getting exact frequency from formula as mention in an900 app note formula is CALCULATING TIMER0 RELOAD VALUE imer0 Reload Value = FFFFh ? but i am getting 35hz even i am compute the equation for 50hz thanks in advance
What is the clock frequency which you have used in the project? One idea I can think of is, If you have a 2 MHz clock ( 0.5 us period) you can write the code for a two-bit counter and generate the pulses accordingly. So you'll transmit when count==0 and receive otherwise.
For your 2nd question the output is always 8 bits(from one of the 2 counters). This means that the lower 8 bits of the 16 bit counter are not used. For driving 8 bits of the output, you will need 8 2:1 muxes. Each mux will take one input from the 8 bit (...)
Step 1: Read the Fine Manual: Step 2: Actually read it.
Sir, I have generated netlist for a 16 bit counter using Encounter RTL the synthesis I set the clock as define_clock -period 3500 -name clk and in the timing report generated a have a positive slack - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk) capture
Initialization 1. set timer 0 as counter by using T0CKI clock input 2. set the corresponding bit in TRISx register which connects to T0CKI external clock to 1. 3. set an interrupt for timer0 in interrupt routine. Normal operation 1. when interrupt occurs add one to a static or global variable 2. update it to a LCD display or on UART or reset timer
Hello, Ill try to answer a question as I seem to only leech off the boards :D so forgive me if this isn't that helpful. I'm not that well versed in Verilog, I've mostly used VHDL but this might help you. 1) yes you are quite right you will need some denouncing for your switch these are common and you can find some code for it online. 2) have a po
1. The original code doesn't work as a counter in real hardware. 2. A state-of the art synthesis tool recognizes that the counter'high is restricted to 12 by the code, thus the fifth FF will be discarded and replaced by a constant 0 bit. Only 4 Latches, respectively D-FFs if using the working code suggested by shaiko. - -
Hi. I'm using Cadence Virtuoso with verilog ams. I pretend to build a counter with a 9 bit word. How can I check the value of the counter? Regards.
hi, Look at this image, it suggests a external asynchronous 1imer clock period of 60nanosec, ~16MHz. Use timer0 in conjunction with a timer0 interrupt clocked software counter to give a precise 1 second period for reading the Timer1 count. Also use timer1 interrupt to clock a software counter, this will give a 24 bit value [ (...)
Hi, 8bit vs 16 bit counter. An 8 bit counter counts 0...255 then overflows and restars with 0... A 16 bit counter counst 0...65535 then overflows and restars with 0... That's the difference. ********* What max counter frequency... Tells you (...)
This will end up being slower than the internal PWM hardware. Have you tried to see what F you need and what pre-scaler changes can be made to default counter clock? For standard Arduinos the system clock is 16MHz so that the timers are clocking at 250kHz by default. Phase correct 8-bit PWM mode takes 510 clocks to cycle and fast 8-bit (...)
hello, if you don't use interrupt , you can count number of elementary MCU Cycles. 1 cycle duration= 4/ (Fosc in MHz) in ?sec // if Fosc=16MHz void Tempo_1mS() { asm{ MOVLW 210 ; MOVWF _N1; // 8 bit counter ici: nop ; //1 nop ; nop ; nop ; nop ;
Guys, I'm beginner on VHDL and playing with VGA, I want to flip green to red with one statement of VHDL, is that possible ? I tried with combining : red <= '1' when vert_scan > 10 and vert_scan < 515 and horz_scan >= 100 and horz_scan < 350 else '0'; grn <= '1' when vert_scan > 20 and vert_scan < 525 and horz_scan >= 200 and horz_s
Hi I have one module like revolution counter which will count the revolution of motor.for that module 3 I/p are there clk,reset,motor angle of 15 bit when motor angle crosses 0 degrees in positive direction the count value increments one and it crosses 0 in neg direction it decrements 1....can u suggest logic or vhdl code for dis p.s there is
Hi I have one module like revolution counter which will count the revolution of motor.for that module 3 I/p are there clk,reset,motor angle of 15 bit when motor angle crosses 0 degrees in positive direction the count value increments one and it crosses 0 in neg direction it decrements 1....can u suggest logic or vhdl code for dis p.s there is n