438 Threads found on edaboard.com: 2 Bit Counter
I want to find a way, to controll rgb led color (specific color for example 5 or ten specified color) with a tact switch and without micro-controller. on the other hand want to use simple and cheap material.
thanks for your help
Analog Circuit Design :: 01-09-2017 07:36 :: farhang_760 :: Replies: 3 :: Views: 674
I need to write a code of a calculator that divide two 8-bit binary numbers, the first 4 bits of each number represent the integer part and the second 4 bits represent the fraction part.
I don't know much about coding in Verilog, please help me with the code. :sad:
I really appreciate it.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-24-2016 08:46 :: dipin :: Replies: 10 :: Views: 1436
I am wondering how to draw a state transition diagram for a two bit counter with the same reset capabilities of a register.
I am also wondering if this reset signal is asynchronous what does this change about the output function and is it a Mealy Machine?
Elementary Electronic Questions :: 10-24-2016 07:28 :: pricet123 :: Replies: 0 :: Views: 313
I am trying to debug my ALU design in FPGA. I am using trigger immediate option after downloading the bit stream to FPGA. But the chipscope never displays the signal values starting from program counter=0 and the waveform starts from some other value of program counter. How to resolve this issue, I need to capture rea
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-14-2016 15:16 :: ads-ee :: Replies: 5 :: Views: 634
the normal method for dealing with pushbutton IO in FPGAs would be to write a debouncing circuit.
This works by sampling the button with a clock. Typically two registers in a row to form a "synchronizer". This dramatically reduces the chance of "metastability" -- that the button will be changing at the exact instant of the clock edge. The actua
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-13-2016 08:13 :: vGoodtimes :: Replies: 5 :: Views: 624
When assigning integer literals to bit vectors in Verilog, you'll usually get a warning that a 32 bit value has been truncated.
Personally, I won't expect the "lazy" assignment in a tutorial.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-09-2016 08:21 :: FvM :: Replies: 6 :: Views: 600
I am trying to design a Mod 6 3-bit D-type asynchronous down counter using Pspice and I am having difficulty with the Nand gate in order to make the count go from 5-0. In its present state it is counting from 7-0 and I know with the addition of adding a NAND gate I can reduce the count to the desire 5-0 but I have no idea how to connect the g
Elementary Electronic Questions :: 09-01-2016 20:36 :: TunerPhish :: Replies: 7 :: Views: 1995
For clarification: are you using two 74192 and two 7447 devices? One counter can only reach 15 maximum and the 7447 can only drive one digit. We would have to know how you have them connected to be sure but the principle is to gate together the bits that make the number 19 (0001 1001) and when that bit pattern is matched, drive the "load" (...)
Hobby Circuits and Small Projects Problems :: 08-26-2016 13:25 :: betwixt :: Replies: 1 :: Views: 448
I had a time running finesim. This tool allows me to do confirm a timing violation on STA report whether we can ignore or not.
You can try it because it can produce the waveform, and you can add detailed command to get the logic level ( voltage ) of any signal/node anytime.
Sorry, I can not recall all scripting and syntax
ASIC Design Methodologies and Tools (Digital) :: 07-14-2016 01:31 :: maestroharsh :: Replies: 4 :: Views: 566
There are 2 ways to design synchronous FIFO that I know:
1. Using n+1 bit counters for write pointer and read pointer. In this case, since it is 8 location FIFO, you can use 3+1 = 4 bit counter. To detect full and empty is simple:
FULL: WP-RP = 4'b1000
We cannot decide full and empty conditions (...)
ASIC Design Methodologies and Tools (Digital) :: 06-21-2016 18:55 :: abhiverma812 :: Replies: 2 :: Views: 1447
Hello,there I am working on a project taking measurement of
-AC voltage frequency
I have used the Timer O for reading the frequency but the problem now is that I can`t read the frequency using Timer O(T0CKI pin of the PIC16F877A).
Could you please help me to deal with codes so that I can read that par
Microcontrollers :: 06-04-2016 10:52 :: jean12 :: Replies: 3 :: Views: 505
It will count from 0x0000 to 0x0FFF three times, then jump to 0x3000, and go from there to 0x3FFF and on to 0x0000. It's as if bit 12 is stuck to bit 13.
Clarifies that the counter is counting correct internally, but you don't see bit 12 and 13 unless both are one. That's unlikely to happen by logic operation, more likely (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-01-2016 17:28 :: FvM :: Replies: 13 :: Views: 667
Assuming P3.0-P3.3 is a binary number (with P3.0 as the MSB) then the MOD value would be defined as:
P3.0 * 2^3 + P3.1 * 2^2 + P3.2 * 2^1 + P3.3 2^0
Microcontrollers :: 05-20-2016 21:00 :: ads-ee :: Replies: 4 :: Views: 915
I don´t understand.
With 32 bit timer and 1:1 prescaler I can't handle the 16 bit lsb and 16 bit msb values.
What´s wrong with it?
I bit more detailes, please.
Microcontrollers :: 04-11-2016 08:14 :: KlausST :: Replies: 26 :: Views: 1553
You should probably have range checks on the CNT value. Maybe SHORT = 2-4 and LONG = 5-7.
Restart the decoder if you get a value outside of these ranges.
Do the development and debugging with a simulator and a test bench (the Altera version of Modelsim). It is a waste of time to do all of the debugging on the real hardware.
When you go to the
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-07-2016 07:48 :: std_match :: Replies: 9 :: Views: 1331
I'd like to make a 10-bit Up/Down counter using Verilog in Altera DE1. It's a decimal counter that counts from 0-1023 with DIR, LOAD and RESET. Reset will get the counter back to 0. DIR will specify if it's going up or down.
I have here a code where it will simply count from 0-15(F). How do you think I can modify (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-13-2016 12:42 :: nizdom :: Replies: 6 :: Views: 1204
You can't call out each individual bit of the bus in an instantiation you connect the entire bus with one named association. This is why the tools complain about too many actuals.
Yes you can - as long as you connect every bit of the bus, you can slice it however you want:
my_inst : entity work.Regist
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-10-2016 07:21 :: TrickyDicky :: Replies: 18 :: Views: 1646
I am making a 4 bit counter that can count up or down to a modulo value I can set using switches on the board.
Here is my code and the errors I am getting.
entity counter4bit is
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-09-2016 15:08 :: amd1416 :: Replies: 0 :: Views: 2
I need to write a testbench for any example netlist so for this i need a netlist with sdf file.Any links for the netlist and sdf files download will be of great help.
Software Links :: 02-23-2016 04:32 :: Vaibhav12 :: Replies: 3 :: Views: 44
You can find information about debouncing block debouncing block from that link has 3 FF's (registers) plus a 19-bit counter, in total 22 registers, per input.
It is important to
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-22-2016 14:31 :: std_match :: Replies: 5 :: Views: 667
You could try to use a 74HC5555, it is a 555 with a internal divider for long time periods. If you set it to 17 bit (131,072) and use a 1 KHz oscillator you would get 2.184 hours, 1.1 KHz would be 1.96 hours.
You would use the Q output to drive Bradtherad's decade counter and use the 74HC5555 non-retriggerable mode. Meaning that the 2 hour per
Hobby Circuits and Small Projects Problems :: 01-06-2016 23:33 :: FlapJack :: Replies: 3 :: Views: 571
18f252 t0 8 or 16bits
Microcontrollers :: 01-03-2016 10:53 :: necati :: Replies: 6 :: Views: 844
hello guys i have been implementing radix2^2 sdf, i have given butterfly input as 16 bit counter for the 1st stage, my expected ans are 24,28.....8-16j,10-18j, these are my expected ans,,, but im getting real part as 24, 28.....-8,-8. imag part is -8,-8.....24,28, are my values a valid one??? what should i expect in imag part if there is no imag p
Digital Signal Processing :: 12-18-2015 07:55 :: prashanthi999 :: Replies: 0 :: Views: 412
The code in post #1 isn't related to UART, just sending 8-bit words. It's neither implementing a 32-bit counter.
Apparently you copied a third parties code that is loosely related to the thread topic, but doesn't actually help to solve it.
Writing a programmable logic design starts with a specification:
- input and output signals
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-18-2015 07:46 :: FvM :: Replies: 4 :: Views: 542
In the present example, transition from 3 (gray 010) to 5 (gray 111), the problem is that you may also see an intermediate gray code of 011 (value 2), which is outside the transition range.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-28-2015 14:31 :: FvM :: Replies: 8 :: Views: 565
I have designed following code in verilog using Xilinx and it is not giving me the results. i have a 16 bit vector bit_s_row. i want to calculate 1's from index i = 0 up to the index B_addr. Please help me in resolving the issue.
pop_count = pop_count +1'b1;
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-16-2015 06:29 :: QMA :: Replies: 2 :: Views: 515
I could not understand why they took the 18 bit counter because that would divide the frequency by 2^18 and not 2^16.
I agree with your calculation. The refresh rate with an 18 bit counter is 200 Hz, not 800 Hz.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-14-2015 11:48 :: FvM :: Replies: 3 :: Views: 565
As mentioned in the title, which one has a larger area?
What I am intended to do is to use shift register as a counter. E.g. If I want to count 8 times of certain operation, a 9-bit shift register is used to shift a binary '1' from index 0 to index 8. The operation stops when '1' reaches index 8. I can also do it with a 3-bit (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-04-2015 06:29 :: alexpanrui :: Replies: 4 :: Views: 580
I need a counter in verilogA that count the number of pulses in a window of 30KHz. So every 30KHz i need to visualize the number of pulses and reset the counter.
Thanks for your help.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-16-2015 08:52 :: justanengineer :: Replies: 0 :: Views: 766
i need microcontroller with 3, 32 bit counter qei module, kindly suggest which can i go .
Microcontrollers :: 05-26-2015 19:30 :: raman00084 :: Replies: 2 :: Views: 485
4 Flip-flops means a 4-bit binary number. A 4-bit binary number can display numbers from 0b0000 (0) to 0b1111 (15). The prime numbers that are below 15 are: 1, 2, 3, 5, 7, 11, and 13.
Build a truth table that has each of those as the input and the output is the next value in the sequence. Convert that truth table to a circuit using the JK flip-flo
Elementary Electronic Questions :: 05-12-2015 19:57 :: ads-ee :: Replies: 5 :: Views: 2485
the output assignment is 1 bit shorter than counter_WIDTH. Hence the error.
BinaryCount(counter_WIDTH-1) = 1 bit
BinaryCount(counter_WIDTH-2 downto 0) xor BinaryCount(counter_WIDTH-1 downto 1) = counter_WIDTH-2 bits
hence length of output = (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-06-2015 13:08 :: TrickyDicky :: Replies: 6 :: Views: 745
Will there is be power and area difference for an 6 bit upcounter and 6 bit updown counter?
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-30-2015 13:51 :: tv123 :: Replies: 4 :: Views: 563
For a near constant frequency I would recommend a ring
with large per-stage non-junction, non-MOS capacitors
(as these will vary with temp and voltage as well) and a
current starved inverter (i.e. current controlled). Then
your transition is all about I=CdV/dt and I, C are fixed
(to the quality of your current reference).
Now if you had a low-TCR
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-14-2015 02:59 :: dick_freebird :: Replies: 8 :: Views: 1143
Disclaimer: this is schoolwork, so I'm not sure if it's in the right segment.
I need to write a frequency counter for a PIC16F870 microcontroller that can read frequencies from 0 to 255hz (8 bit, at least they had some mercy there...). This is for a school project where we have to build a capacitive pick-up and then output the RPM of a DC motor
Microcontrollers :: 04-03-2015 21:03 :: metiz :: Replies: 2 :: Views: 781
hello i am working on an900 code but i am not getting exact frequency from formula as mention in an900 app note
CALCULATING TIMER0 RELOAD VALUE
imer0 Reload Value = FFFFh ?
but i am getting 35hz even i am compute the equation for 50hz
thanks in advance
Microcontrollers :: 03-29-2015 08:49 :: abc_de :: Replies: 8 :: Views: 1761
What is the clock frequency which you have used in the project? One idea I can think of is,
If you have a 2 MHz clock ( 0.5 us period) you can write the code for a two-bit counter and generate the pulses accordingly. So you'll transmit when count==0 and receive otherwise.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-04-2015 08:47 :: harpv :: Replies: 2 :: Views: 860
For your 2nd question the output is always 8 bits(from one of the 2 counters). This means that the lower 8 bits of the 16 bit counter are not used.
For driving 8 bits of the output, you will need 8 2:1 muxes. Each mux will take one input from the 8 bit (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-22-2015 07:07 :: sharath666 :: Replies: 2 :: Views: 766
Step 1: Read the Fine Manual:
Step 2: Actually read it.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-19-2015 15:39 :: mrflibble :: Replies: 1 :: Views: 536
Microcontrollers :: 01-16-2015 07:34 :: ud23 :: Replies: 3 :: Views: 1940
I have generated netlist for a 16 bit counter using Encounter RTL the synthesis I set the clock as
define_clock -period 3500 -name clk and in the timing report generated a have a positive slack
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(clock clk) capture
ASIC Design Methodologies and Tools (Digital) :: 01-16-2015 05:20 :: JineshKB :: Replies: 1 :: Views: 597
Actually I want to count that how many times switch has pressed. For this I made **T0CK1** as input of switch and put TMR0 on external crystal but its not working as I thought it would be
Code I made with my little knowledge about timers
TRISAbits.RA4=1; // COnfigure RA4 as inp
Microcontrollers :: 12-13-2014 09:14 :: wasif_khan :: Replies: 3 :: Views: 1074
Hello, Ill try to answer a question as I seem to only leech off the boards :D so forgive me if this isn't that helpful.
I'm not that well versed in Verilog, I've mostly used VHDL but this might help you.
1) yes you are quite right you will need some denouncing for your switch these are common and you can find some code for it online.
2) have a po
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-03-2014 08:08 :: completelyuseless :: Replies: 9 :: Views: 5509
1. The original code doesn't work as a counter in real hardware.
2. A state-of the art synthesis tool recognizes that the counter'high is restricted to 12 by the code, thus the fifth FF will be discarded and replaced by a constant 0 bit. Only 4 Latches, respectively D-FFs if using the working code suggested by shaiko.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-22-2014 11:50 :: FvM :: Replies: 34 :: Views: 3124
Hi. I'm using Cadence Virtuoso with verilog ams. I pretend to build a counter with a 9 bit word.
How can I check the value of the counter?
ASIC Design Methodologies and Tools (Digital) :: 11-03-2014 20:26 :: dshoter13 :: Replies: 0 :: Views: 815
Look at this image, it suggests a external asynchronous 1imer clock period of 60nanosec, ~16MHz.
Use timer0 in conjunction with a timer0 interrupt clocked software counter to give a precise 1 second period for reading the Timer1 count.
Also use timer1 interrupt to clock a software counter, this will give a 24 bit value [ (...)
Microcontrollers :: 10-02-2014 17:46 :: esp1 :: Replies: 8 :: Views: 1579
8bit vs 16 bit counter.
An 8 bit counter counts 0...255 then overflows and restars with 0...
A 16 bit counter counst 0...65535 then overflows and restars with 0...
That's the difference.
What max counter frequency...
Tells you (...)
Microcontrollers :: 09-30-2014 18:36 :: KlausST :: Replies: 2 :: Views: 420
This will end up being slower than the internal PWM hardware.
Have you tried to see what F you need and what pre-scaler changes can be made to default counter clock?
For standard Arduinos the system clock is 16MHz so that the timers are clocking at 250kHz by default. Phase correct 8-bit PWM mode takes 510 clocks to cycle and fast 8-bit (...)
Microcontrollers :: 09-04-2014 16:29 :: SunnySkyguy :: Replies: 2 :: Views: 683
if you don't use interrupt , you can count number of elementary MCU Cycles.
1 cycle duration= 4/ (Fosc in MHz) in ?sec
// if Fosc=16MHz
MOVLW 210 ;
MOVWF _N1; // 8 bit counter
nop ; //1
Microcontrollers :: 08-22-2014 10:51 :: paulfjujo :: Replies: 2 :: Views: 605
I'm beginner on VHDL and playing with VGA,
I want to flip green to red with one statement of VHDL, is that possible ?
I tried with combining :
red <= '1' when vert_scan > 10 and vert_scan < 515 and horz_scan >= 100 and horz_scan < 350 else '0';
grn <= '1' when vert_scan > 20 and vert_scan < 525 and horz_scan >= 200 and horz_s
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-03-2014 05:29 :: bianchi77 :: Replies: 9 :: Views: 760