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4 bit full adder in verilog
i need to make a 4 bit full adder using verilog can anybody please help me?...
PLD, SPLD, GAL, CPLD, FPGA Design :: 15 Nov 2009 19:13 :: icaniwill :: Replies: 4 :: Views: 3849
nanosim -- hspice netlist and verilog netlist simulation
also call some digital blocks.and those digital blocks were define in another verilog netlist.how should i run my simulation? i keep getting the error below. i dont know how to solve.error:nanosim:0x30204......
Analog IC Design & Layout :: 11 Nov 2009 9:38 :: nima1357 :: Replies: 3 :: Views: 123
full adder .. please help with checking the program
i have just learned to write on vhdl and i have completed my first full adder code using components for the xor, and, or gates but im not sure if its right, could someone please tell me if this is right? i do not have vhdl ive written this on notepad...
ASIC Design Methodologies & Tools (Digital) :: 08 Nov 2009 5:57 :: OKcomputer6 :: Replies: 0 :: Views: 114
power dissipation in spartan 3e using ise 10.1 [plz help]
i am beginner of the fpga design. i am facing problem in estimating dynamic power dissipation using ise10.1(xpower analyzer) tool. i wanted to estimate dynamic power dissipation of 1bit full subtractor (combinational circuit) using ise 10.1. how do i...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Oct 2009 8:47 :: Ashwini12 :: Replies: 1 :: Views: 99
problem with simulation in modelsim se plus 5.7e
# vsim adder.vhdl# loading c:/modeltech_5.7e/win32/../win32aloem/convert_hex2ver.dll# ** error: (vsim-3193) load of c:/modeltech_5.7e/win32/../win32aloem/convert_hex2ver.dll failed: file not found.# ** error: (vsim-pli-3002) failed to load pli object...
PLD, SPLD, GAL, CPLD, FPGA Design :: 18 Aug 2009 13:49 :: yasser_shoukry :: Replies: 5 :: Views: 2123
help with measure statements for calculating prop. delays
hi, sorry, if this is the wrong place to ask, pls redirect me to the right place. i am very much new to this forum. the problem is that, i am simulating a simple full adder in hspice for 1000 random inputs, and want to measure the propagation d...
Analog IC Design & Layout :: 09 Aug 2009 13:57 :: erikl :: Replies: 5 :: Views: 381
verilog examples....
can anybody plz help me with a sample hdl code that you have done for your project or something...i havent seen a verilog code completely...tats y..im familiar with stuffs lk full adder n ol..but want to write something big..so any examples???...
PLD, SPLD, GAL, CPLD, FPGA Design :: 15 Jul 2009 20:53 :: thiagu_comp :: Replies: 6 :: Views: 683
how to p&r a design using custom cells in cadence encout
hi folks, instead of using standard cells, i want some custom cells to be used in placement and routing of a design. is there any tutorial or way to do that.also if i want certain specific standard cells to be used, how can i do that in c...
ASIC Design Methodologies & Tools (Digital) :: 13 Jul 2009 9:27 :: kadhan :: Replies: 7 :: Views: 429
geeks! can you please help!
have made the code and it is compiling well but when i try to simulate, i get dozens of errors. i will greatly appreciate if someone can guide me with this coz i need to transfer the code on spartan-3 fpga very soon. here is the complete code i have...
PLD, SPLD, GAL, CPLD, FPGA Design :: 03 Jul 2009 19:48 :: shelby :: Replies: 1 :: Views: 229
could you help me about this vhdl error
i take this error after simulating this code: cant find a pinstub/port in the symbol, function prototype, or other construct test that represents a design file that corresponds to pin xa2 in the file.this is a 16 bit csa simulatorthank you for helpmi...
PLD, SPLD, GAL, CPLD, FPGA Design :: 07 Jun 2009 10:51 :: minemercan :: Replies: 0 :: Views: 180
how to design a digital adder??
valuation and i was given a guide for preparation. one of the problems is the following:design an adder in module based on the following truth table:x y s0 0 00 1 10 2 2 0 3 31 0 11 1 21 2 31 3 0...
Electronic Elementary Questions :: 22 May 2009 11:34 :: halls :: Replies: 6 :: Views: 501
to make a 4x4 multiplier
how can i make a 4x4 multiplier using only half adder,full adder,8 bit shift register?...
ASIC Design Methodologies & Tools (Digital) :: 28 Apr 2009 7:57 :: ray123 :: Replies: 2 :: Views: 804
problem with verilog testbench
hi.i write a code for full adder simulation in verilog.i write a code for test it(testbench).bbut when i run the code the following error appears.(i am working with maxplusii)can you solve it?module fa (x,y,sum,carry);input x;input y;output sum;outpu...
PLD, SPLD, GAL, CPLD, FPGA Design :: 31 Mar 2009 13:47 :: pentium_m :: Replies: 7 :: Views: 1425
need full verilog code for 16-bit adder with carry save
please send me full verilog code for 16-bit adder with carry save.please send it as fast as you can.i need it very urgently....
Electronic Elementary Questions :: 25 Mar 2009 13:28 :: rsharitwal :: Replies: 2 :: Views: 372
a lot interview questions with resposes
hi all,here is a nice collection of interview questions with reponses:cmos interview questions.1/ what is latch up?latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or scr) is in...
EDA Jobs, Promotions, Advertising :: 21 Jan 2009 9:03 :: sridhar540 :: Replies: 15 :: Views: 8813
sigma-delta modulator in fractional-n frequency synthesizer
its known that a spur free fractional-n frequency synthesizer is mostly realized with a sigma-delta modulator and a multi-module divider. the control bits of the multi-module divider is dithered by the sigma-delta modulator (sdm). but the output of t...
Analog IC Design & Layout :: 17 Dec 2008 14:08 :: Leo_fish :: Replies: 7 :: Views: 768
simulink mash1-1-1 help
dear alli am a green hand in simulink. i want to set up a sigma delta modulator in simulinki planed to make it in a digital way, that is to say, i will need a multi-bit full adder , a multi-bit register and a single bit register.i searched the tool b...
Analog IC Design & Layout :: 09 Dec 2008 2:47 :: Leo_fish :: Replies: 0 :: Views: 186
can anyone help me to calculate the pseudo nmos logic effect
as in the picture, its a full adder using the pseudo nmos.the size of the mos is in the picture,and how we can get the logic effect of cin,the power up logic effect,and the power down logic effect ,and the intrinsic of power up and power down.as a ne...
ASIC Design Methodologies & Tools (Digital) :: 17 Nov 2008 9:40 :: purian :: Replies: 0 :: Views: 90
need a rail to rail opamp design
hi,i need a low power rail to rail opamp with max 200 mhz bw.i work in 0.35um and simulate with hspice 49 level cmos.let design it.thanks....
Analog IC Design & Layout :: 31 Oct 2008 15:44 :: meysam_abbasinia :: Replies: 4 :: Views: 324
test bench for a full adder problem.....
hii i am having a problem with a test bench in vhdlthe following is my code for a full adder::library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity adderwa isgeneric (n:positive:=4);port(a,b:in std_logic_vector(n-1 downto 0); cin...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05 Oct 2008 0:27 :: prashant_sharma :: Replies: 1 :: Views: 861
plz help me out..
plz can u show me the design of 3-bit multiplier (unsigned) in circuit maker???...
Electronic Elementary Questions :: 21 Sep 2008 11:59 :: SWINI :: Replies: 2 :: Views: 135
a question about delay difference
a,b,c is 8bit integer，z=a*b，z=a*b+c，pls compare the delay difference between two designs，in unit of gateʌ88;e.g.A306;the difference is 4 full adder + 1 muxsʌ89;pls explain the result in detail :)thank you!...
ASIC Design Methodologies & Tools (Digital) :: 19 Sep 2008 5:54 :: yx.yang :: Replies: 4 :: Views: 180
full custom design of datapath for use in cpu
is there any material about full custom design of datapath, such as adder, multiplier, not cell based?thanks in advance, guys...
ASIC Design Methodologies & Tools (Digital) :: 04 Aug 2008 5:11 :: ljxpjpjljx :: Replies: 3 :: Views: 159
from vhdl/verilog to layout
hi everyone,i am wondering if it is possible to write a vhdl/verilog code and uses it to generate the schematic and layout so that i can combine it with my own full custom design?for instance, say i am working on a adder. in order to test the adder, ...
ASIC Design Methodologies & Tools (Digital) :: 25 Jul 2008 17:06 :: pichuang :: Replies: 6 :: Views: 423
verilog - generate multiple interconnected modules
hi everybody!i have the following code that works as a shift register :module sreg (c, si, so);input c,si;output so;reg tmp;always @(posedge c)begintmp = tmp << 1;tmpand i want to create multiple instances of the sreg module which are intercon...
ASIC Design Methodologies & Tools (Digital) :: 05 Jun 2008 15:00 :: korgull :: Replies: 13 :: Views: 6315
two"s complement
hi... can anyone tell me how to compute the twos complement of n bit number using minimum harware... i.e using minimum number of logic circuits... is it possible to do this without using a n bit adder......
ASIC Design Methodologies & Tools (Digital) :: 13 May 2008 16:54 :: SWINI :: Replies: 5 :: Views: 159
implementing full adder using cpl
hi,i need circuit diagram for full adder using cpl......anyone can help??...
ASIC Design Methodologies & Tools (Digital) :: 13 May 2008 14:30 :: basha_vlsi :: Replies: 1 :: Views: 123
digital questions....can anyone solve these?
from y or y from x, depending on the value of a .if a=1, the output should be x-y, and if a=0, the output should be y-x.use a 4 bit substractor and two 4bit 2to 1 mux?2) realize a full adder using a 3 to 8 line decoder and a)two or gates b)two norga...
ASIC Design Methodologies & Tools (Digital) :: 26 Apr 2008 22:10 :: Alkakkali :: Replies: 4 :: Views: 309
urgent help needed !!
adder cell layout. i drawed its layout in magic but when i try to simulate it using hspice and awanwaves im getting spikes which i circled in red in this link:http8;//img166.imageshack.us/img166/8391/spikeeh3.jpghow can i fix it?thanks added afte...
Analog IC Design & Layout :: 16 Apr 2008 5:01 :: santhosh.mandugula :: Replies: 3 :: Views: 123
urgent help needed about layout!!
adder cell layout. i drawed its layout in magic but when i try to simulate it using hspice and awanwaves im getting spikes which i circled in red in this link:http8;//img166.imageshack.us/img166/8391/spikeeh3.jpghow can i fix it?thanks...
ASIC Design Methodologies & Tools (Digital) :: 16 Apr 2008 2:22 :: Rob B :: Replies: 3 :: Views: 120
multiple threshold mos
hican any one clarify my doubts.....1) is it possible to use different threshold voltage mos transistors in one design,i mean for example consider a cmos full adder can i use pmos transistors with different vthp i.e, vthp1=-0.65v,vthp2=-0.5v nmos tra...
ASIC Design Methodologies & Tools (Digital) :: 31 Mar 2008 12:49 :: balan :: Replies: 3 :: Views: 171
threshold voltage variation
hi can any one clarify my doubts.....1) is it possible to use different threshold voltage mos transistors in one design,i mean for example consider a cmos full adder can i use pmos transistors with different vthp i.e, vthp1=-0.65v,vthp2=-0.5v nmos t...
ASIC Design Methodologies & Tools (Digital) :: 30 Mar 2008 11:31 :: madhavisai :: Replies: 2 :: Views: 195
ADS
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inout port+testbench problem, verilog
i wrote a testbench for my i2c code but it doesnt seem to work.in the module sda is an inout port.in the testbench:...wire sda;reg sda_reg;oe = 1;...assign sda = (oe == 1) ? sda_reg : 1bz;...i always write sda_reg. the problem is that sda always stay...
PLD, SPLD, GAL, CPLD, FPGA Design :: 26 Mar 2008 23:47 :: echo47 :: Replies: 12 :: Views: 2424
transmission gate
any one please give me circuit digram of 8:1 mux using transmission gates...
Electronic Elementary Questions :: 15 Mar 2008 12:50 :: sandeep_sggs :: Replies: 4 :: Views: 198
vhdl code for adder
i need adder vhdl code...
PLD, SPLD, GAL, CPLD, FPGA Design :: 07 Mar 2008 15:39 :: eng_aq :: Replies: 7 :: Views: 6672
interview questions
i,if inverted output of d flip-flop is connected to its input how the flip-flop behaves?design a circuit to divide input frequency by 2?design a divide by two counter using d-latch.design a divide-by-3 sequential circuit with 50% duty cycle.what are ...
ASIC Design Methodologies & Tools (Digital) :: 28 Feb 2008 13:08 :: sizzlers :: Replies: 4 :: Views: 5819
cordic
hi guys ..anyone has any information on how to make the cordic algorithm calculate say the phase of a certain input vector in one clock cycle ? .. in other words, the current algorithm that i have do implement the calculation process in pipeline stag...
ASIC Design Methodologies & Tools (Digital) :: 23 Feb 2008 21:16 :: rubnawaz :: Replies: 23 :: Views: 1248
help for implementing parallel adder
hai friends,i am new to this fpga design and all.i am doing an adder now which isx = z + a1 + a2 + a3 + a4;it is taking a more delay,i thought of implementing a tree type adder, which is like a12 = a1 + a2; a34 = a3 + a4;x = z+a12 + a34; will this w...
PLD, SPLD, GAL, CPLD, FPGA Design :: 18 Feb 2008 13:59 :: platopathrose :: Replies: 3 :: Views: 180
full adder implementation for pipelined adc
can anyone please give materials regarding the full adder implementation for pipelined adc design the spec of the adc is 10 bit 100 ms/s...thanks in advance .......
Analog IC Design & Layout :: 10 Jan 2008 9:11 :: barath_87 :: Replies: 0 :: Views: 120
what type of adder you suggest ?
i am trying to implement/ the pipeline and parallel in vhdl for the given filefor that i am choose the a ckt which is shown in file (without pipeline& parallel )after complete analysis of this ckt i will go for pipeline & parallel .i would like to ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 17 Dec 2007 11:26 :: manish12 :: Replies: 1 :: Views: 225
test bench
can anyone help me out for writing test bench for full adder and 4:1 mux...
ASIC Design Methodologies & Tools (Digital) :: 21 Nov 2007 11:24 :: barkha :: Replies: 7 :: Views: 279
absolute value or magnitude
hello all, newbie to these boards. i have a question regarding absolute value in terms of binary. for instance (a and b are 4 bits long):|a - b| + 1 my thoughts are do it like:- for b, negate all the bits- pass the negated b into a full adder with ...
ASIC Design Methodologies & Tools (Digital) :: 25 Oct 2007 6:15 :: wsobhan :: Replies: 0 :: Views: 54
subtract 3
please tell me how to subtract a binary a by 3 (a-3) in the best way ( except the way that using a subtract block from fa to have the result)thanks a lot !!!...
PLD, SPLD, GAL, CPLD, FPGA Design :: 16 Oct 2007 4:22 :: bigrice911 :: Replies: 8 :: Views: 210
verification enviroment
dear all what is verification enviroment?is it tool dependent or is a concept?if it is a concept how should one generate it,or what are methodologies for that?if there is any goo book or link on this matter plz post it.thanks to all ....
ASIC Design Methodologies & Tools (Digital) :: 26 Sep 2007 14:10 :: kinjal_book :: Replies: 10 :: Views: 696
problem with post synthesis simulation
i am generating post p&r vhdl file from leonardo. while compiling it in modelsim error is coming like no default binding for ibuf and obuf.if i generate same file from the xilinx then it includes simprim and unisim file. but file generated from leona...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Sep 2007 4:32 :: gck :: Replies: 0 :: Views: 78
hey guys one interview question! beat the hell out of me!!
hey guys!..i got this question in an online interview..may be i might be dumb enough not to figure it out.. but ive been thinking since 48 hours, but still i am not able to figure out!..qs: design a digital circuit (only basic logic gates and, or, xo...
ASIC Design Methodologies & Tools (Digital) :: 18 Sep 2007 12:39 :: nand_gates :: Replies: 17 :: Views: 1422
standard cell library design
hii want to develop a standard cell libraryfor .13u/.09u technology.can anyone guide me on this .1) what tools are required; i have tools for schematic drawing, spice simulation, layout drawing, drc/lvs, netlist extraction; all from silvacos iccad...
ASIC Design Methodologies & Tools (Digital) :: 22 Jul 2007 0:33 :: mm6349 :: Replies: 17 :: Views: 1920
interview question
hi,i am having a interview ..i want digital design inteview question ...can any buddy help me . regardskapil...
ASIC Design Methodologies & Tools (Digital) :: 06 Jun 2007 18:32 :: the_vamsi :: Replies: 9 :: Views: 2379
floating point adder/subtracter
hello my friendsi want to design a floating-point adder/subtracter circuit:i know the algorithm (e.g: computer architecture,m.mano,3rd ed,pritice-hall page:359) but i have problem with the hardware implementation of the algorithm :cry: :which ic :?: ...
Embedded Systems and Real-Time OS :: 22 May 2007 19:43 :: sadid :: Replies: 5 :: Views: 621
what is the boolean equation of 2bit full adder???
input a0 a1 b0 b1 cin output sum0 sum1 cout....thx a lot...
Analog IC Design & Layout :: 07 May 2007 14:13 :: cyw1984 :: Replies: 4 :: Views: 201
synthesis pragmas
hi all,can any body tell me what are synthesis pragmas.and how they effect.regards kunal mishra...
ASIC Design Methodologies & Tools (Digital) :: 25 Apr 2007 16:06 :: boardlanguage :: Replies: 4 :: Views: 432
interview question
how many min. no. of mos transistors are required to implement full adder???...
ASIC Design Methodologies & Tools (Digital) :: 09 Apr 2007 7:55 :: sumit_techkgp :: Replies: 12 :: Views: 678
how to design amultiplier& divider logic circuit
hi expertsi wanna desing a circuit which supposed to multiply 4bits no using the full adder ic and the clock and counter there is no problem about the multiplying circuit .. but how can i use the same circuit of multiplying to perform the division...
Electronic Elementary Questions :: 19 Mar 2007 19:09 :: nanoYasser :: Replies: 0 :: Views: 132
please help me solving this problem.
how can i make excess-3 to bcd decoder by using 4 bit parallel adders?...
Electronic Elementary Questions :: 19 Mar 2007 18:39 :: nanoYasser :: Replies: 1 :: Views: 171
using electronic workbench
i need halp.4-bit full adder which can add two (4 bit) binary numbers and produces a(4-bit) binary sum plus carry out. i want to use switches for inputs and decodes (7 - segment display) for output. the carry should be shown by an led....
Hobby Circuits and Small Projects Problems :: 03 Jan 2007 16:03 :: Shani :: Replies: 2 :: Views: 390
16-bit bdc adder
any code available ?? on vhdland also tutorialpoints will be given.......ty in advance...
PLD, SPLD, GAL, CPLD, FPGA Design :: 20 Dec 2006 12:27 :: nand_gates :: Replies: 6 :: Views: 306
help with interview question #1
hi, members,ive some interview questions about digital circuit, vhdl and asic/fpga. i think its a good opportunity for us to discuss these questions. maybe its very helpful when we want to seek for jobs in the near future. the following is the first ...
ASIC Design Methodologies & Tools (Digital) :: 20 Dec 2006 11:45 :: rakesh1234 :: Replies: 11 :: Views: 540
how can i create a user-defined package?
im trying to run a package id created using quartus tools but when i run the compilation, an error with the following appear in the message box. the following is the package header of simple full adder (fulladd_package.vhd): library ieee ;use ieee.st...
PLD, SPLD, GAL, CPLD, FPGA Design :: 18 Dec 2006 13:03 :: hairo :: Replies: 1 :: Views: 153
binary to floating point conversion
hi all...,pls let me know any core for converting binary to floating point. the floating point should be in ieee 754 format... thanks in advancebyeee...
PLD, SPLD, GAL, CPLD, FPGA Design :: 17 Dec 2006 16:51 :: sixdegrees :: Replies: 4 :: Views: 426
how can i create a user-defined package?
im trying to run a package id created using quartus tools but when i run the compilation, an error with the following appear in the message box. the following is the package header of simple full adder (fulladd_package.vhd): library ieee ;use ieee.st...
PLD, SPLD, GAL, CPLD, FPGA Design :: 14 Dec 2006 22:05 :: salma ali bakr :: Replies: 3 :: Views: 180
16-bit carry-select full adder
could you give some details about this adder because we need it for vhdl design....thnx.......
Microcontrollers :: 13 Dec 2006 6:36 :: zhaorah :: Replies: 0 :: Views: 144
difference of process between fpga design and asic design
hi, members,what are the differences of process between fpga design and asic design? i know the design process for fpga, is it helpful for the design process for asic design?...
ASIC Design Methodologies & Tools (Digital) :: 06 Nov 2006 15:57 :: richardyue :: Replies: 7 :: Views: 390
vhdl program for a 4 bit full-adder
dear,i need a help in writing a vhdl cobe for a 4bit full-adderregards...
PLD, SPLD, GAL, CPLD, FPGA Design :: 10 Oct 2006 22:26 :: wvengineer :: Replies: 1 :: Views: 1857
8-bit adder using 1-bit adder in systemc
hi,can any1 send me the code for 8-bit adder using eight 1-bit adder in systemc.i have attached the 1-bit full adder code in systemc. mail me the code at rahul.malik@amd.com.thanks...
Embedded Systems and Real-Time OS :: 02 Oct 2006 17:55 :: malirah :: Replies: 0 :: Views: 363
a problem about transistor simulation using nanosim .
hello ,all i met with a problem when i try to do transistor level simulation using nanosim ,it puzzled me for several days . i hope someone may help me out . i write a very simple 4-bit full adder in verilog , and i synthesis with synopsys dc adn...
Digital Signal Processing :: 04 Sep 2006 12:34 :: wildwood :: Replies: 0 :: Views: 126
a problem about transistor simulation using nanosim .
hello ,all i met with a problem when i try to do transistor level simulation using nanosim ,it puzzled me for several days . i hope someone may help me out . i write a very simple 4-bit full adder in verilog , and i synthesis with synopsys dc adn...
Analog Circuit Design :: 04 Sep 2006 11:40 :: wildwood :: Replies: 0 :: Views: 366
implementation of algorithm in hardware.
i am just curious how to implement algorithm into hardware. let say, i have written a convolutional in c++ language for simulation purpose. then, what should i do to implement in hardware?is it using fpga or vhdl?any good informations about it? thank...
Digital communication :: 05 Aug 2006 11:51 :: cmos babe :: Replies: 7 :: Views: 516
critical path minimisation
in case of combo-full adder (3 fa are connected in serially, each having 10ns delay) the result should be updated in every 10ns. how can i minimise the critical path here ???...
ASIC Design Methodologies & Tools (Digital) :: 19 Jul 2006 14:37 :: neo_chip :: Replies: 3 :: Views: 231
full costume design for 32-bit adder
hi, all i want full costume design for adder circuit if anyone can contribute ur moat welcome..thanks.....
Analog IC Design & Layout :: 24 Jun 2006 5:30 :: abionnnn :: Replies: 1 :: Views: 159
dc , help instantiating asics librarys full adder
i am using design compiler, width tsmc 0.13 asic library.the tsmc library provides full adder cell but design compiler is not using it.i instantiated a full adder using the component instantiation as descripted in designware user guide.library ieee, ...
ASIC Design Methodologies & Tools (Digital) :: 13 Jun 2006 16:00 :: nkef :: Replies: 3 :: Views: 228
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