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73 Threads found on 6 Layer Stack Up
Hello, all the overlaps on tStop layer are marked up and listed when I'm doing the DRC, which is quite annoying and inconvenient. How can I stop eagle from listing them as errors? This is what it looks
There are many GND Vias between RF traces, but In the middle of the GND plane, some vias each have a black square(copper removed) next to it. 135956 What's the reason behind this design? We are considering follow the EVB's design in our project. Any help will be greatly appreciated!
i don't how to matching 100 ohm and 50 ohm impedance in 2 layer pcb , i need trace width and spacing pls any one can help me..
Hello. I have a more or less complete design for a lab supply which I have been trying to implement on a 4-layer PCB, even if changes may occur this thread wont loose any value for my progress since they will if any minor. Here is a muck-up of the design to be the subject here: 116719 This is my first such a comple
HI all, I'm designing a multilayer PCB (12 layer ) and I decided to use layer 5 and 6 for power distribution. So the question is can I put one voltage(eg. 1V) on one plane(eg. L5) and then a second voltage(eg. 3.3V) on other plane(eg. L6) on top of it? OR i have to have GND plane In-between? layer L4 and L7 are GND (...)
I am beginner in the Altium, and need guidance on how to proceed with the schematic and pcb layout mainly. The board will keep all the components welded on one side only. The other side will need to be free to be engaged in an LCD. I have many doubts, did just a basic course to know and use the basic tools available in Altium. It will be very diff
Hi, I am new to rf design. I'm trying to design a 4 layer PCB. the stack-up looks like this: 1.GND 2.Power 3.signal 4.GND the data rate in layer 3 (signal layer) is about 16 GHz. What do I have to consider? I mean, what is the best method (draw finite GNDs? vias between layer 1 and 4?) in ADS (...)
I am printing a 2-page fabrication drawing: Page one is the board/drill guide, and page two is just the fab notes and stack-up. The board outline is printed on both pages , even though my "board outline" mechanical layer isn't one of the layers selected to print for page 2. Is there a way to turn that off for? Thanks!
Hello, I wanted to place a stackup legend on my design files. It puts a nice bracket, it names the layers aaand.. that's about it. Details are filled in in the layer manager (obviously) and I enabled all options when I 'tabbed' after placing first corner. Seems I did just about everything as mentioned in (...)
I'm looking for stack up recommendations (keeping in mind readily available materials) for a 6 layer board I'm working on. Design requirements dictate the following: - maximum 6 layers - lots of high speed traces DDR3, SERDES, Gbit ETH, USB2.0 etc - high speed signals due to BGA need to be 4mils wide So for 50/100Ohm with 4mil (...)
Hi Folks, I'm using Orcad Layout (v9) to route my PCB (2 layers , top and bottom only). I need to achieve the following requirement, On Top layer i have to manually route important traces. Auto Route rest of the traces on the bottom layer. (No more traces on top) How to achieve this ? I route manually important tr
I need +Power, -Power, 2 routing layers, and a ground plane. However, I don't know how to choose my stack-up? If someone could explain all the different possibilities along with the trade-offs I'd really appreciate it. I'm concerned with things such as cost and routing difficulty and EMI and all that good stuff. ALSO: what are the disadvantage
Hi Cadstar have really nice layer stack editor but i still not find a way to put that info into the gerber or documetation drawing ? still have solution to make it by hand and put it on templace but i sure zuken not put lot of tome for make great layer stack up editor and forgot way to put it on output file (...)
Can any body help me How to decide layer stack up in Multi layer designing?
Hi everyone, in my design has BGA(256pins),DC-DC converter,opto isolator,schmitt trigger,connector is avaiable and power and ground are 1.5V(1.5A),3.3V(2A),5V(1A),+15V_FTR,+15V_DC,5VDC,+ 5V_FTR,+24V_ISO,ISO_GND,GND,AGND,minimum pitch details for package tssop package-0.65mm,soic-1.27mm,BGA Pitch-1mm i am planning to design in 6 layer ,Here
Hi , I am designing 24 layer card with 1GHz having 12 BGAs , Is there any guideline for layer stack up for BGA Thanks Ashwin
hi robis, top layer and bottom layer is signal layer if want to design 2 layer top and bottom is enough no need to assign extra layer like ground or power (planes). usually layer are assign in multiplication of 2 like 2 layer,4 layer, 6 (...)
I went through the Si self teach guide, over a period of time, started at page one and did everything in the guide in order, that is the best way, its quite a steep learning curve, but can be donein a couple of weeks. I cant think of any easier way, to use the software properly requires the proper training, there is no simplistic path to getting r
Hi all, Engineers who are familiar with HyperLynx please help solve stackup problem in HyperLynx. I'm getting stackup problems message when trying to simulate a one single net in my PCB. My PCB board has 2 physically layer only. But when trying to simulate a got warning message "The stackup has error". And when I opened (...)
Hi everyone, I was wondering which tool is best for model PCB stack up and able to do simulation on the model. We are talking about multiple layer. I would like to be able to change the dielectric constant and dissipate factor for core a on each layer. An example of layout is: Plane Gnd Core Signal Cu pre-preg plane Gnd I (...)
hi, go to drafting -->2D line and then draw line like that in drill drawing layer
Hello all, I am designing a two-layer PCB in Allegro PCB Designer. (My school has a T-Tech machine that this job will be sent to.) I would like to route signals on the top and leave the bottom as a ground plane with a few short routes on the bottom. I have both layers in the stack-up set up as positive artwork signal (...)
Hi! Structure of my PCB stack up: L1--^---^--- SIG L2----------- GND L3--^---^--- SIG/PWR L4--^---^--- SIG/PWR L5----------- GND L6--^---^--- SIG on L1/L6 assembled BGA (DDR2,FPGA) with pitch 0.8mm, so i need route aproximately 0.1/0.1 (line/clr.) and VIA about 06/03 or 05/02 L1/L3/L4/L6 single - 50ohm, diff - 100ohm
Hello ppl, I have a 4 layer PCB stack up and the corresponding .dxf file imported in ADS. My doubt is that I know that layer 1 which is signal trace 1 corresponds to the .dxf layer Trace_01 and same is the case with signal trace 2 i.e Trace_04. Now between these two layers I have ground and Power supply (...)
Hi! here is my sample. Via 0.5/0.2 minimal line width/clearance 0.1/0.1 71344 L1 ? Signal L2 ? GND L3 ? Signal/Power L4 ? Signal/Power L5 ? GND L6 ? Signal
As Fvm as stated there is no easy answer, there is a lot to learn. Just to add some points.. 1. Impedance control requirement 2. Routability- approximately a 12 X 12 array of BGA can be routed in a 6 layer card (a thumb rule) 3. Number of power rails 4. Performance specs of the PCB- EMC in specific 5. Allowed
Both quoted stackups are rather special ones and hardly suitable for your design purposes, I presume. 4 layer is almost mandatory for complex designs with high density packages and a larger amount of signals. You still would want to avoid packages like BGA for fully connected FPGAs, they rather demand for 6 layers. A continuous GND plane (...)
How is layer stackup calculation done?
Hello I would want to have your opinion about the design of my board. My design is a analog amp for a sensor which use a 300kHz bandwidth and two voices. I have to use a FR4 4 layers PCB. I have the TOp for routing signal, the inner1 for the GND (which is a plane), the inner2 for the VCC/VEE supply rails (planes too), and the bottom layer (plane o
hello all. we need 4 layer fr4 pcb board. but with non standarts stack up. top layer - 35 um copper prepreg - 0.8 mm mid layer1 - 35 um copper core - 0.5 or 0.6 mm mid layer 2 - 35 um copper prepreg - 0.8 mm bottom layer - 35 um copper so total thickness it about 2.2 mm. most (...)
Go to the layers Editor (Options -> layers). There you can add/delete/rename any layers as you want. (Note that you can also map any layers other than cond and cond2 as metal) JB Thanks! Just to make sure that Momentum will NOT calculate the maxwell equations according to the name of the layout layers, (...)
What r considarations ? what r prequesties for routing multilayer board . After Routing the multilayer board what r documentios to be submitted ?
hi prastesh, thanks for your reply. but i think your are not understand my ?? please see that file, in this board is 6 layer board file,when i click this layer stack up it is shows as class:maufacturer sub class :layer stack up how it is come ??
iam going to use allegro16.2
Hi all In my schematic the following VCC is using 9v, 5V , 3.3V 2.5V, 1.8 V. but i could not identify how to design it .i though is it possible to design in four layer?? (till now i am design the board in 2 layer ). whether layer stack up increases depends on VCC or no of nets?? Note: how to identify the (...)
Hi Everyone, I am facing a problem in ORCAD 9.10.I am designing a 4-layer board and using top-->gnd-->pwr-->bot as my stack up.But ORCAD has given me this stack up top-->bot-->pwr-->gnd which is the default.I am not able to change the layers in ORCAD.I am attaching a snapshot of layers
Hi all, Can anybody pls tell, What is the effect of Unbalanced layer stack up ? or sometimes it is required to unbalance the Core or prepage thickness for some Desing requirements? And what is the difference if We use Core in center or we use Prepage in center .because somedody told me that we shuld use like Top layer CORE (...)
i designed in such a way that all signal layers are guarded by power supply or gnd planes.... example: 1)TOPlayer 2)GND 3)signal1 4)power1 5)signal2 6)power2 7)signal3 8)bottom layer
Hi all, i need help with stack up 8 layer board with controlled impedance 50 ohm (+-10%) on all layers for 0.125mm tracks. Can you help me please ? board thickness 1.6mm. The stack up is : ------signal ------GND ------signal ------VCC ------GND (signal) ------ signal ------VCC ------signal Thank you in advanced !
i am new to multilayer routing (4 layers) plz send the basic settings of the layer.i already worked in 2layer ie top & bottom only.
I am wondering who have done HDI Design using Altium Designer (AD). If done, please let me know how to do the HDI layer stack up (with stacked or staggered microvias) in AD. Thanks in advance.
Attached here is the chip that I'm designing right now and I need some suggestion for layer stack up that I can use for this chip & blind & buried via layer combinations. Thank you.
Is it possible to create the stacked microvias in layers 1-2 and 2-3, when the layer stack up is foil-prepreg-core-prepreg-core-prepreg-foil? Thanks in advance.
I sent my previous queries regarding the PCB layer stack up and thickness of core and prepreg. I got a common reply - the PCB Manufacturer will prepare the same. How can the PCB Manufacturer prepare the PCB layer stack up and determine the value of thickness of core and prepreg? Is the forum for the PCB Manufacturer (...)
The layer stack up (4 layers) is as below TOP layer CORE GND PLANE PREPREG POWER PLANE CORE BOTTOM layer. The other layer stack up (4 layers) is as below TOP layer PREPREG GND PLANE CORE POWER PLANE PREPREG BOTTOM (...)
Hi, I am designing a 4 layer pcb which involves a ARM 7 controller and 2 SDRAMs. stack-up is; Top layer : Routing layer 2 : VCC layer 3 : GND layer 4 : Routing Routing parameters are 8/8 mil. The set-up and hold timings given in the datasheet are as below; (...)
So I'm trying to route an RF device, but do the complexity of the device, I can't route the RF on a single layer. I know routing RF on separate layers will loose a little bit of performance, but at this point it's my only option. Will the following stack up minimize the lost? RF SIGNAL GND SIG1 SIG2 GND RF SIGNAL Would it be (...)
Hi.. In layer stack up the power and signal layer as well as ground and signal layers are spaced closly about 5 mils or 8 mils.But the PWR and Ground planes in stack up are spaced around 30mils or 40 mils.what is the reason for having this kind of stackup? Regards Rajan. >K
the stack up as 4 layer (S,Gnd,Vcc,S) (Select the Vcc and Gnd as planes) 2.Hide the power and gnd nets. 3.Fanout(take connection from pin and select end via) all the Power and Gnd Pins of all Smd the routing as 2 layer 5.If different voltages select the vcc layer and split the plane. 6.Generate gerber like 2 (...)
Hi everybody, This is my first question in this forum. I need to take signal @ 4GHz from Top layer of the PCB to the bottom layer stack up has both RO4350B and FR4 dielectric.The overall thickness is 1.5mm stack up: RF RO4350B GND FR4 SIG FR4 SIG FR4 SIG FR4 GND Can anyone suggest a solution???Can I (...)