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			<div id="results_count">70 Threads found on edaboard.com: <strong>6 Layer Stack Up</strong></div>
		
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			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread336260.html" rel="nofollow">Mixed circuit PCB stack-up, and circuit orientation.</a></h2></div>
			</div>
			<div class="content_text">Hello.

I have a more or less complete design for a lab supply which I have been trying to implement on a 4-<strong>layer</strong> PCB, even if changes may occur this thread wont loose any value for my progress since they will if any minor.

Here is a muck-up of the design to be the subject here:
116719

This is my first such a comple</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 04-22-2015 05:03 :: David_ :: Replies: <strong>0</strong> :: Views: <strong>312</strong>
			</div>
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								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread335728.html" rel="nofollow">Power planes in Multilayer PCB</a></h2></div>
			</div>
			<div class="content_text">HI all,

I'm designing a multi<strong>layer</strong> PCB (12 <strong>layer</strong> ) and I decided to use <strong>layer</strong> 5 and 6 for power distribution.

So the question is can I put one voltage(eg. 1V) on one plane(eg. L5) and then a second voltage(eg. 3.3V) on other plane(eg. L6) on top of it? OR i have to have GND plane In-between?

<strong>layer</strong> L4 and L7 are GND (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 04-13-2015 07:30 :: www111 :: Replies: <strong>4</strong> :: Views: <strong>438</strong>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread328697.html" rel="nofollow">Building a board 4 layers in Altium Designer</a></h2></div>
			</div>
			<div class="content_text">I am beginner in the Altium, and need guidance on how to proceed with the schematic and pcb layout mainly. The board will keep all the components welded on one side only. The other side will need to be free to be engaged in an LCD. I have many doubts, did just a basic course to know and use the basic tools available in Altium.
It will be very diff</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 12-17-2014 11:14 :: TiagoRibeiro :: Replies: <strong>4</strong> :: Views: <strong>796</strong>
			</div>
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								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread313885.html" rel="nofollow">4 Layer PCB Design in Momentum ADS2013 - Best Way!!</a></h2></div>
			</div>
			<div class="content_text">Hi,
I am new to rf design. I'm trying to design a 4 <strong>layer</strong> PCB.
the <strong>stack</strong>-up looks like this:
1.GND
2.Power
3.signal
4.GND

the data rate in <strong>layer</strong> 3 (signal <strong>layer</strong>) is about 16 GHz.
What do I have to consider?
I mean, what is the best method (draw finite GNDs? vias between <strong>layer</strong> 1 and 4?)  in ADS (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 04-15-2014 09:44 :: ala_einstein82 :: Replies: <strong>0</strong> :: Views: <strong>743</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread308974.html" rel="nofollow">Altium: I don't want to print PCB border/outline</a></h2></div>
			</div>
			<div class="content_text">I am printing a 2-page fabrication drawing: Page one is the board/drill guide, and page two is just the fab notes and <strong>stack</strong>-up. The board outline is printed on both pages , even though my "board outline" mechanical <strong>layer</strong> isn't one of the <strong>layer</strong>s selected to print for page 2. Is there a way to turn that off for? Thanks!</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 02-04-2014 14:38 :: colklink :: Replies: <strong>1</strong> :: Views: <strong>809</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread309130.html" rel="nofollow">Altium - Layer stack up detail empty</a></h2></div>
			</div>
			<div class="content_text">Hello,

I wanted to place a <strong>stack</strong>up legend on my design files. It puts a nice bracket, it names the <strong>layer</strong>s aaand.. that's about it. Details are filled in in the <strong>layer</strong> manager (obviously) and I enabled all options when I 'tabbed' after placing first corner. Seems I did just about everything as mentioned in (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 02-06-2014 08:35 :: Ice-Tea :: Replies: <strong>1</strong> :: Views: <strong>1179</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread306889.html" rel="nofollow">6 layer stack-up recommendations</a></h2></div>
			</div>
			<div class="content_text">I'm looking for <strong>stack</strong> up recommendations (keeping in mind readily available materials) for a 6 <strong>layer</strong> board I'm working on.

Design requirements dictate the following:

 - maximum 6 <strong>layer</strong>s
 - lots of high speed traces DDR3, SERDES, Gbit ETH, USB2.0 etc
 - high speed signals due to BGA need to be 4mils wide

So for 50/100Ohm with 4mil (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 01-06-2014 12:10 :: Jester :: Replies: <strong>8</strong> :: Views: <strong>995</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread278985.html" rel="nofollow">Help required in routing : Orcad layout plus</a></h2></div>
			</div>
			<div class="content_text">Hi Folks,

I'm using Orcad Layout (v9) to route my PCB (2 <strong>layer</strong>s , top and bottom only). I need to achieve the following requirement,

On Top <strong>layer</strong> i have to manually route important traces.
Auto Route rest of the traces on the bottom <strong>layer</strong>. (No more traces on top)



How to achieve this ? I route manually important tr</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 02-01-2013 07:14 :: boiler95 :: Replies: <strong>3</strong> :: Views: <strong>889</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread278445.html" rel="nofollow">PCB Stackup/Ground Planes/Tradeoffs</a></h2></div>
			</div>
			<div class="content_text">I need +Power, -Power, 2 routing <strong>layer</strong>s, and a ground plane.  However, I don't know how to choose my <strong>stack</strong>-up? If someone could explain all the different possibilities along with the trade-offs I'd really appreciate it.  I'm concerned with things such as cost and routing difficulty and EMI and all that good stuff.

ALSO: what are the disadvantage</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 01-28-2013 03:06 :: mspagon :: Replies: <strong>1</strong> :: Views: <strong>791</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread278183.html" rel="nofollow">Cadstar  How put layer Stack-up on Gerber ?</a></h2></div>
			</div>
			<div class="content_text">Hi 

Cadstar have really nice <strong>layer</strong> <strong>stack</strong> editor 
but i still not find a way to put that info into the gerber or documetation drawing ?

still have solution to make it by hand and put it on templace
but i sure zuken not put lot of tome for make great <strong>layer</strong> <strong>stack</strong> up editor 
and forgot way to put it on output file (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 01-24-2013 15:23 :: T5400 :: Replies: <strong>5</strong> :: Views: <strong>814</strong>
			</div>
		</div>
								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread278127.html" rel="nofollow">[MOVED] How to decide layer stack up in PCB</a></h2></div>
			</div>
			<div class="content_text">Can any body help me How to decide <strong>layer</strong> <strong>stack</strong> up in Multi <strong>layer</strong> designing?</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 01-24-2013 06:06 :: honey 77 :: Replies: <strong>2</strong> :: Views: <strong>635</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread273648.html" rel="nofollow">where will core and prepreg use ?</a></h2></div>
			</div>
			<div class="content_text">Hi everyone,

in my design has BGA(256pins),DC-DC converter,opto isolator,schmitt trigger,connector is avaiable and power and ground are
1.5V(1.5A),3.3V(2A),5V(1A),+15V_FTR,+15V_DC,5VDC,+ 5V_FTR,+24V_ISO,ISO_GND,GND,AGND,minimum pitch details for package
tssop package-0.65mm,soic-1.27mm,BGA Pitch-1mm

i am planning to design in 6 <strong>layer</strong> ,Here </div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 12-05-2012 00:33 :: kabaleevisu :: Replies: <strong>4</strong> :: Views: <strong>1413</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread273793.html" rel="nofollow">Layer stack consideratin in BGA PCBs</a></h2></div>
			</div>
			<div class="content_text">Hi ,
I am designing 24 <strong>layer</strong> card with 1GHz having 12 BGAs ,
Is there any guideline for <strong>layer</strong> <strong>stack</strong> up for BGA
Thanks 
Ashwin</div> 
			<div class="content_info">
				&nbsp;&nbsp; Show your DIY :: 12-06-2012 04:54 :: ashwinbhole :: Replies: <strong>0</strong> :: Views: <strong>674</strong>
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		</div>
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			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread267846.html" rel="nofollow">4 layer board vs. 2 layer board layer stack up</a></h2></div>
			</div>
			<div class="content_text">hi robis,

top <strong>layer</strong> and bottom <strong>layer</strong> is signal <strong>layer</strong> if want to design 2 <strong>layer</strong> top and bottom is enough no need to assign extra <strong>layer</strong> like ground or power (planes). usually <strong>layer</strong> are assign 
in multiplication of 2 like 2 <strong>layer</strong>,4 <strong>layer</strong>, 6 (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 10-07-2012 03:09 :: kabaleevisu :: Replies: <strong>3</strong> :: Views: <strong>1767</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread266609.html" rel="nofollow">Cadstar si and emc analysis</a></h2></div>
			</div>
			<div class="content_text">I went through the Si self teach guide, over a period of time, started at page one and did everything in the guide in order, that is the best way, its quite a steep learning curve, but can be donein a couple of weeks.
I cant think of any easier way, to use the software properly requires the proper training, there is no simplistic path to getting r</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 09-26-2012 06:17 :: marce :: Replies: <strong>13</strong> :: Views: <strong>732</strong>
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			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread264579.html" rel="nofollow">Need stackup editing help in HyperLynx</a></h2></div>
			</div>
			<div class="content_text">Hi all,
Engineers who are familiar with HyperLynx please help solve <strong>stack</strong>up problem in HyperLynx. I'm getting <strong>stack</strong>up problems message when trying to simulate a one single net in my PCB. My PCB board has 2 physically <strong>layer</strong> only. But when trying to simulate a got warning message "The <strong>stack</strong>up has error". And when I opened (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 09-03-2012 03:37 :: mkrtich.nazaryan :: Replies: <strong>2</strong> :: Views: <strong>712</strong>
			</div>
		</div>
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			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread258535.html" rel="nofollow">Model PCB stackup layout question</a></h2></div>
			</div>
			<div class="content_text">Hi everyone,

I was wondering which tool is best for model PCB <strong>stack</strong> up and able to do simulation on the model. We are talking about multiple <strong>layer</strong>. I would like to be able to change the dielectric constant and dissipate factor for core a on each <strong>layer</strong>. 

An example of layout is:

Plane Gnd
Core
Signal Cu
pre-preg
plane Gnd

I (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 07-06-2012 13:21 :: 1a2s3d4f :: Replies: <strong>1</strong> :: Views: <strong>780</strong>
			</div>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread257182.html" rel="nofollow">Stack-up detail on Drill Drawing Layer</a></h2></div>
			</div>
			<div class="content_text">hi,

go to drafting -->2D line and then draw line like that in drill drawing <strong>layer</strong> </div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 06-26-2012 07:20 :: kabaleevisu :: Replies: <strong>5</strong> :: Views: <strong>1378</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread251695.html" rel="nofollow">Allegro autorouting over dynamic shape</a></h2></div>
			</div>
			<div class="content_text">Hello all,

I am designing a two-<strong>layer</strong> PCB in Allegro PCB Designer. (My school has a T-Tech machine that this job will be sent to.) I would like to route signals on the top and leave the bottom as a ground plane with a few short routes on the bottom. I have both <strong>layer</strong>s in the <strong>stack</strong>-up set up as positive artwork signal (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 05-10-2012 09:43 :: parasonic :: Replies: <strong>1</strong> :: Views: <strong>881</strong>
			</div>
		</div>
								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread244763.html" rel="nofollow">[MOVED] 6 layer stack up, 50ohm - single, 100 ohm diff, low cost prototype suggestions</a></h2></div>
			</div>
			<div class="content_text">Hi!
Structure of my PCB <strong>stack</strong> up:
L1--^---^--- SIG 
L2----------- GND 
L3--^---^--- SIG/PWR
L4--^---^--- SIG/PWR
L5----------- GND 
L6--^---^--- SIG

on L1/L6 assembled BGA (DDR2,FPGA) with pitch 0.8mm, so i need route aproximately 0.1/0.1 (line/clr.) and VIA about 06/03 or 05/02 
L1/L3/L4/L6 single - 50ohm, diff - 100ohm
</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 03-16-2012 01:15 :: fpga-developer :: Replies: <strong>3</strong> :: Views: <strong>1502</strong>
			</div>
		</div>
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			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread246040.html" rel="nofollow">ADS .dxf file import: specific layer</a></h2></div>
			</div>
			<div class="content_text">Hello ppl,

I have a 4 <strong>layer</strong> PCB <strong>stack</strong> up and the corresponding .dxf file imported in ADS. My doubt is that I know that <strong>layer</strong> 1 which is signal trace 1 corresponds to the .dxf <strong>layer</strong> Trace_01 and same is the case with signal trace 2 i.e Trace_04. Now between these two <strong>layer</strong>s I have ground and Power supply (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Electromagnetic Design and Simulation :: 03-26-2012 08:24 :: Samkeet :: Replies: <strong>1</strong> :: Views: <strong>766</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread245633.html" rel="nofollow">Stack-up of a six-layer help</a></h2></div>
			</div>
			<div class="content_text">Hi,

I have to design a 6 <strong>layer</strong> board with Altium Designer software.

Well, in this board I have :

-Power: 1.2V , 1.8V and 3.3 V
-GND
-Digital signals.

This board is based on a DSP with the maximum frequency of 600 MHz.


Can any one help me how to make the <strong>stack</strong>-up of my six-<strong>layer</strong>s.

Well I read bofore that I'm able to use (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 03-23-2012 06:18 :: hot_snow :: Replies: <strong>5</strong> :: Views: <strong>870</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread236563.html" rel="nofollow">Layer stack up in PCB..</a></h2></div>
			</div>
			<div class="content_text">As Fvm as stated there is no easy answer, there is a lot to learn.

Just to add some points..

1. Impedance control requirement
2. Routability- approximately a 12 X 12 array of BGA can be routed in a 6 <strong>layer</strong> card (a thumb rule)
3. Number of power rails
4. Performance specs of the PCB- EMC in specific
5. Allowed </div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 01-09-2012 04:01 :: cks3976 :: Replies: <strong>12</strong> :: Views: <strong>1695</strong>
			</div>
		</div>
								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread223562.html" rel="nofollow">Help on PCB stack up for FPGA with uC design</a></h2></div>
			</div>
			<div class="content_text">Both quoted <strong>stack</strong>ups are rather special ones and hardly suitable for your design purposes, I presume. 4 <strong>layer</strong> is almost mandatory for complex designs with high density packages and a larger amount of signals. You still would want to avoid packages like BGA for fully connected FPGAs, they rather demand for 6 <strong>layer</strong>s.

A continuous GND plane (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 09-04-2011 12:48 :: FvM :: Replies: <strong>21</strong> :: Views: <strong>3086</strong>
			</div>
		</div>
								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread210989.html" rel="nofollow">Layer stackup calculation for multilayers</a></h2></div>
			</div>
			<div class="content_text">How is <strong>layer</strong> <strong>stack</strong>up calculation done?</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 04-30-2011 01:25 :: PCB design :: Replies: <strong>3</strong> :: Views: <strong>1875</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread211092.html" rel="nofollow">Need help to design a PCB board</a></h2></div>
			</div>
			<div class="content_text">Hello
I would want to have your opinion about the design of my board. My design is a analog amp for a sensor which use a 300kHz bandwidth and two voices. I have to use a FR4 4 <strong>layer</strong>s PCB. I have the TOp for routing signal, the inner1 for the GND (which is a plane), the inner2 for the VCC/VEE supply rails (planes too), and the bottom <strong>layer</strong> (plane o</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 05-01-2011 05:05 :: pcbboard :: Replies: <strong>2</strong> :: Views: <strong>869</strong>
			</div>
		</div>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread210406.html" rel="nofollow">non standart 2.2mm 4 layer pcb manufacturer need in china.</a></h2></div>
			</div>
			<div class="content_text">hello all.

we need 4 <strong>layer</strong> fr4 pcb board. but with non standarts <strong>stack</strong> up.

top <strong>layer</strong> - 35 um copper
prepreg - 0.8 mm
mid <strong>layer</strong>1 - 35 um copper
core - 0.5 or 0.6 mm
mid <strong>layer</strong> 2 - 35 um copper
prepreg - 0.8 mm
bottom <strong>layer</strong> - 35 um copper

so total thickness it about 2.2 mm. most (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 04-25-2011 05:16 :: orpheus :: Replies: <strong>1</strong> :: Views: <strong>1200</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread209880.html" rel="nofollow">needs more metal layer in ADS Momentum</a></h2></div>
			</div>
			<div class="content_text">Go to the <strong>layer</strong>s Editor (Options -> <strong>layer</strong>s). There you can add/delete/rename any <strong>layer</strong>s as you want.
(Note that you can also map any <strong>layer</strong>s other than cond and cond2 as metal)

JB
 
Thanks! 

Just to make sure that Momentum will NOT calculate the maxwell equations according to the name of the layout <strong>layer</strong>s, (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Electromagnetic Design and Simulation :: 04-20-2011 02:29 :: grit_fire :: Replies: <strong>5</strong> :: Views: <strong>1351</strong>
			</div>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread206584.html" rel="nofollow">PCB multilayer Routing</a></h2></div>
			</div>
			<div class="content_text">What r considarations ? what r prequesties for routing multi<strong>layer</strong> board . After Routing the multi<strong>layer</strong> board what r documentios to be submitted ?</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 03-21-2011 10:42 :: scriptx007 :: Replies: <strong>1</strong> :: Views: <strong>1119</strong>
			</div>
		</div>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread200811.html" rel="nofollow">how to create layer stackup like this ???</a></h2></div>
			</div>
			<div class="content_text">hi prastesh,
thanks for your reply. but i think your are not understand my ?? please see that file, in this board is 6 <strong>layer</strong> board file,when i click this <strong>layer</strong> <strong>stack</strong> up it is shows as 
class:maufacturer
sub class :<strong>layer</strong> <strong>stack</strong> up 
how it is come ??</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 02-01-2011 04:05 :: kabaleevisu :: Replies: <strong>5</strong> :: Views: <strong>1316</strong>
			</div>
		</div>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread200613.html" rel="nofollow">layout cross section for 4layer</a></h2></div>
			</div>
			<div class="content_text">iam going to use allegro16.2</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 01-29-2011 06:34 :: selvakumar.m :: Replies: <strong>5</strong> :: Views: <strong>1099</strong>
			</div>
		</div>
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			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread194903.html" rel="nofollow">VCC depends on layer stackup??</a></h2></div>
			</div>
			<div class="content_text">Hi all 

In my schematic the following  VCC is using  9v, 5V , 3.3V  2.5V, 1.8 V. but i could not identify  how to design it .i though is it possible to design in four <strong>layer</strong>??  (till now i am design the board   in 2 <strong>layer</strong> ). whether  <strong>layer</strong> <strong>stack</strong> up  increases depends on  VCC or no of nets??

Note: how to identify the (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 12-01-2010 06:33 :: kabaleevisu :: Replies: <strong>9</strong> :: Views: <strong>1188</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread193959.html" rel="nofollow">Changing Layer stack up and assigning mirror layer</a></h2></div>
			</div>
			<div class="content_text">Hi Everyone,

I am facing a problem in ORCAD 9.10.I am designing a 4-<strong>layer</strong> board and using top-->gnd-->pwr-->bot as my <strong>stack</strong> up.But ORCAD has given me this <strong>stack</strong> up top-->bot-->pwr-->gnd which is the default.I am not able to change the <strong>layer</strong>s in ORCAD.I am attaching a snapshot of <strong>layer</strong>s</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 11-21-2010 03:53 :: deba_fire :: Replies: <strong>0</strong> :: Views: <strong>1343</strong>
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			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread193012.html" rel="nofollow">Need Help For  PCB Layer Stack Up '''</a></h2></div>
			</div>
			<div class="content_text">Hi all,
 Can anybody pls tell,  What is the effect of Unbalanced <strong>layer</strong> <strong>stack</strong> up ? or sometimes it is required to  unbalance the Core or prepage thickness for some Desing requirements?
And what is the difference if We use Core in center  or we use Prepage in center .because somedody told me that we shuld use like 

 Top <strong>layer</strong> 
  CORE (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 11-11-2010 01:48 :: jack_pcb :: Replies: <strong>3</strong> :: Views: <strong>1732</strong>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread188565.html" rel="nofollow">PCB layer stack-up considerations</a></h2></div>
			</div>
			<div class="content_text">i designed in such a way that all signal <strong>layer</strong>s are guarded by power supply or gnd planes....

example:

1)TOP<strong>layer</strong>
2)GND
3)signal1
4)power1
5)signal2
6)power2
7)signal3
8)bottom <strong>layer</strong></div> 
			<div class="content_info">
				&nbsp;&nbsp; ASIC Design Methodologies and Tools (Digital) :: 09-24-2010 07:54 :: vinodkumar :: Replies: <strong>4</strong> :: Views: <strong>1698</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread187242.html" rel="nofollow">Help me with 8 layer stack up with controlled impedance of 50 ohm on all layers</a></h2></div>
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			<div class="content_text">Hi all, i need help with <strong>stack</strong> up 8 <strong>layer</strong> board with controlled impedance 50 ohm (+-10%) on all <strong>layer</strong>s for 0.125mm tracks. Can you help me please ?
board thickness 1.6mm.
The <strong>stack</strong> up is :

------signal
------GND
------signal
------VCC
------GND (signal)
------ signal
------VCC
------signal

Thank you in advanced !</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 09-08-2010 10:36 :: haimanov :: Replies: <strong>3</strong> :: Views: <strong>2643</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread185894.html" rel="nofollow">routing multilayer board</a></h2></div>
			</div>
			<div class="content_text">i am new to multi<strong>layer</strong> routing (4 <strong>layer</strong>s) plz send the basic settings of the <strong>layer</strong>.i already worked in 2<strong>layer</strong> ie top & bottom only.</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 08-21-2010 00:18 :: m_kavith :: Replies: <strong>3</strong> :: Views: <strong>1184</strong>
			</div>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread185718.html" rel="nofollow">HDI Design using Altium Designer</a></h2></div>
			</div>
			<div class="content_text">I am wondering who have done HDI Design using Altium Designer (AD). If done, please let me know how to do the HDI <strong>layer</strong> <strong>stack</strong> up (with <strong>stack</strong>ed or staggered microvias) in AD.

Thanks in advance.</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 08-19-2010 01:37 :: tennythomas :: Replies: <strong>0</strong> :: Views: <strong>1703</strong>
			</div>
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								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread185278.html" rel="nofollow">Stack Up &amp; Via Combinations</a></h2></div>
			</div>
			<div class="content_text">Attached here is the chip that I'm designing right now and I need some suggestion for <strong>layer</strong> <strong>stack</strong> up that I can use for this chip & blind & buried via <strong>layer</strong> combinations. Thank you.</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 08-13-2010 04:50 :: bert_kak :: Replies: <strong>1</strong> :: Views: <strong>1487</strong>
			</div>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread185462.html" rel="nofollow">Is it possible to create the stacked microvias in layers 1-2 and 2-3 ?</a></h2></div>
			</div>
			<div class="content_text">Is it possible to create the <strong>stack</strong>ed microvias in <strong>layer</strong>s 1-2 and 2-3, when the <strong>layer</strong> <strong>stack</strong> up is foil-prepreg-core-prepreg-core-prepreg-foil?

Thanks in advance.</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 08-16-2010 03:01 :: tennythomas :: Replies: <strong>0</strong> :: Views: <strong>1042</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread184263.html" rel="nofollow">How PCB Manufacturer prepares the PCB layer stack up and determines the values?</a></h2></div>
			</div>
			<div class="content_text">I sent my previous queries regarding the PCB <strong>layer</strong> <strong>stack</strong> up and  thickness of core and prepreg. I got a common reply - the PCB Manufacturer will prepare the same.

How can the PCB Manufacturer prepare the PCB <strong>layer</strong> <strong>stack</strong> up and determine the value of thickness of core and prepreg? 

Is the forum for the PCB Manufacturer (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 07-30-2010 23:35 :: tennythomas :: Replies: <strong>9</strong> :: Views: <strong>2639</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread184108.html" rel="nofollow">Help me choose a PCB Layer stack up</a></h2></div>
			</div>
			<div class="content_text">The <strong>layer</strong> <strong>stack</strong> up (4 <strong>layer</strong>s) is as below
TOP <strong>layer</strong>
CORE
GND PLANE
PREPREG
POWER PLANE
CORE 
BOTTOM <strong>layer</strong>.

The other <strong>layer</strong> <strong>stack</strong> up (4 <strong>layer</strong>s) is as below

TOP <strong>layer</strong>
PREPREG
GND PLANE 
CORE
POWER PLANE
PREPREG
BOTTOM (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 07-29-2010 03:27 :: tennythomas :: Replies: <strong>4</strong> :: Views: <strong>2608</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread166178.html" rel="nofollow">Need help in timing budget calculation.</a></h2></div>
			</div>
			<div class="content_text">Hi,

I am designing a 4 <strong>layer</strong> pcb which involves a ARM 7 controller and 2 SDRAMs. <strong>stack</strong>-up is;

Top <strong>layer</strong> : Routing
<strong>layer</strong> 2    : VCC
<strong>layer</strong> 3    : GND
<strong>layer</strong> 4    : Routing

Routing parameters are 8/8 mil.

The set-up and hold timings given in the datasheet are as below; (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 01-01-2010 02:13 :: AK2009 :: Replies: <strong>1</strong> :: Views: <strong>1243</strong>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread162053.html" rel="nofollow">How to minimize loses through multilayer RF Stack up</a></h2></div>
			</div>
			<div class="content_text">So I'm trying to route an RF device, but do the complexity of the device, I can't route the RF on a single <strong>layer</strong>. I know routing RF on separate <strong>layer</strong>s will loose a little bit of performance, but at this point it's my only option.  Will the following <strong>stack</strong> up minimize the lost?

RF SIGNAL
GND
SIG1
SIG2
GND
RF SIGNAL

Would it be (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 11-04-2009 10:44 :: berms03 :: Replies: <strong>1</strong> :: Views: <strong>1238</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread158602.html" rel="nofollow">Ground and Power Plane Dielectric thickness</a></h2></div>
			</div>
			<div class="content_text">Hi..
       In <strong>layer</strong> <strong>stack</strong> up the power and signal <strong>layer</strong> as well as ground and signal <strong>layer</strong>s are spaced closly about 5 mils or 8 mils.But the PWR and Ground planes in <strong>stack</strong> up are spaced around 30mils or 40 mils.what is the reason for having this kind of <strong>stack</strong>up?

Regards
Rajan.
>K</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 09-15-2009 05:54 :: dmd4raj :: Replies: <strong>3</strong> :: Views: <strong>2080</strong>
			</div>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread158076.html" rel="nofollow">Guide for design 4 layer pcb in  PADS2005</a></h2></div>
			</div>
			<div class="content_text">the <strong>stack</strong> up as 4 <strong>layer</strong> (S,Gnd,Vcc,S)
 (Select the Vcc and Gnd as planes)
2.Hide  the power and gnd nets.
3.Fanout(take connection from pin and select end via) all the Power and Gnd Pins of all Smd the routing as 2 <strong>layer</strong>
5.If different voltages select the vcc <strong>layer</strong> and split the plane.
6.Generate gerber like 2 (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 09-09-2009 06:55 :: chakravarthy80pcb :: Replies: <strong>1</strong> :: Views: <strong>1606</strong>
			</div>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread156284.html" rel="nofollow">Signal in PCB - RF VIA or Coaxial cable ?</a></h2></div>
			</div>
			<div class="content_text">Hi everybody,

This is my first question in this forum.

I need to take signal @ 4GHz from Top <strong>layer</strong> of the PCB to the bottom <strong>layer</strong> <strong>stack</strong> up has both RO4350B and FR4 dielectric.The overall thickness is 1.5mm

<strong>stack</strong> up:

RF
RO4350B
GND
FR4
SIG
FR4
SIG
FR4
SIG
FR4
GND

Can anyone suggest a solution???Can I (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 08-14-2009 07:03 :: ganesh.moorthy :: Replies: <strong>0</strong> :: Views: <strong>924</strong>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread154600.html" rel="nofollow">Layer Stack up for 14  &amp; 12 layers  in 1.6mm thickness</a></h2></div>
			</div>
			<div class="content_text">2 outer <strong>layer</strong>s plus 6 inner signal <strong>layer</strong>s. Others are all ground and power <strong>layer</strong>s.</div> 
			<div class="content_info">
				&nbsp;&nbsp; PCB Routing Schematic Layout software and Simulation :: 07-21-2009 15:41 :: alex_epds :: Replies: <strong>3</strong> :: Views: <strong>4064</strong>
			</div>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread150961.html" rel="nofollow">How can I make extraction data from AWR ?</a></h2></div>
			</div>
			<div class="content_text">I work on The EM Simulator
and I need Urgent help,
Thanks alot</div> 
			<div class="content_info">
				&nbsp;&nbsp; Electromagnetic Design and Simulation :: 06-10-2009 08:37 :: dragonhamada :: Replies: <strong>5</strong> :: Views: <strong>1324</strong>
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								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread149177.html" rel="nofollow">Prototype PCB fabrication</a></h2></div>
			</div>
			<div class="content_text">I want to get some prototype PCB's fabricated. I need the following capabilities.

->Volume: Prototype - 3pcs
->Board Size: 15"x12"
->6 to 8 <strong>layer</strong> FR4 <strong>stack</strong>-up
->Impedance Controlled
->5mil/5mil and lower
->Vias: Through/Burried/Blind/Micro - Filled and plated via's with high planarity
->Electrical test
->Lead time: 2-4 weeks

Kin</div> 
			<div class="content_info">
				&nbsp;&nbsp; Printed Circuit Boards (PCB) and assembly :: 05-15-2009 13:13 :: kishore2k4 :: Replies: <strong>15</strong> :: Views: <strong>5592</strong>
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