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14 Threads found on 74ls74
Unsuitable input waveform might be a problem, however near to maximum frequency, a FF will work with sine input voltage of sufficient magnitude. But did you review frequency limits in 74xx datasheets? Maximum clock frequency of 7474, 74HC74 and 74ls74 is about 25 MHz. Only 74S74 reaches typically 110 MHz, 74AHC74 even more (but still not 200 MHz
Hello, Circuit as shown in pictures: 130803 Design concept: U0 (not shown) is the output of the door before. After delay 0.5 seconds of NE555, the 3 feet of 74ls74 form rising edge and the 5 feet (U1) output high level, through triode connecting relay (not show
Sorry for such a late reply. I was stuck up with a different project. I have setup the entire circuit on a vero/strip board. My new circuit is attached. Now I have a relay at the output of the D flip flop. I also have a small delay circuit in between the relay and the D-FF output. It is just a requirement of my application. At the output of the r
Why 74LS173? If you don't need gated D-inputs and gated outputs then you can use any D-register IC with (only) D-registers, eg. 74ls74
hai friends, i need to get a pulse detection circuit using 4013 d-flipflop ic or can u suggest 15 v input equivalent of 74ls74 . rakesh
In this case you need to use a Common Anode 7 segment LEDs display. Seven Segment Display Common anode to be connected to the Vcc pin. Look here for an example how to connect the 74ls74 with the 7 segment LED display.
Hello, Is there any 74ls74 quad or octal flip flop equivalent? In need Q as well as Qbar outputs.
Hello All!!! I have some digital inputs working 0V (for 0) to +12V (for 1). 1. I understand that I can't use TTL gates/flip-flops. What's the remplacement in CMOS? I use the following TTL's: 74LS32 (or another multiple input OR gate), 74ls74 (flip-flop) 2. I need to use 1-0 clock for flip-flops, I only know the standard 555 1-0 clock. What
hi i am using 74ls74 for motor driver but its not working i am not geting change in output according change in input i am giving 1 s clk pulse and change in d is 1sec also can any one help me
Hi, You can check the function of those pins in 74ls74 datasheet. 74ls74 Datasheet pdf - Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs - Fairchild Semiconductor As a suggestions, since you have to use 2 those ICs to divide frequency
hi, we are trying to do a project and we have to use a d-flip fliop in schematic editor. what is the most basic part to use? thanks It depends upon which logic family you want to use, ie. TTL or CMOS In the TTL family, there is the 7474, 74ls74, etc. In the 4000 series CMOS there is 4013, 40174, 40175 In the 74H
If the output should be 1 an undefined amount of time, not just a constant period, before reset, you need a latch or bistable. Use 74ls74, or 4013, connecting the D and CLK inputs to ground. Use S to set and R to reset. You can build the same circuit with 2 transistors and some resistors.
Hello All, I am new to this forum as well as Orcad. I having some problems simulating a Flip-Flop ( 74ls74 from the psice lib) When running the simulation I can see the alternating digital output from dstm into the clk of the flip-flop but when monitoring the D Q and QBar of the flip-flop all I see is three red flat lines ie no digital out
Hi, I just start to learn HDL and choose to study verilog. I try to write D-FF (74ls74), but it shows some errors. I've seen some D-FF example but those did not include preset and clear. What wrong with my program? Please help me. Thanks alot. Following is my program by using Xilinx module dffpc(d, q, preset, clear, clk);