13 Threads found on edaboard.com: 74ls74
Circuit as shown in pictures:
Design concept: U0 (not shown) is the output of the door before. After delay 0.5 seconds of NE555, the 3 feet of 74ls74 form rising edge and the 5 feet (U1) output high level, through triode connecting relay (not show
Analog Circuit Design :: 07-18-2016 02:02 :: Kimmy10 :: Replies: 1 :: Views: 167
Sorry for such a late reply. I was stuck up with a different project.
I have setup the entire circuit on a vero/strip board. My new circuit is attached.
Now I have a relay at the output of the D flip flop. I also have a small delay circuit in between the relay and the D-FF output. It is just a requirement of my application. At the output of the r
Microcontrollers :: 06-14-2014 09:07 :: RohanDey :: Replies: 23 :: Views: 2095
If you don't need gated D-inputs and gated outputs then you can use any D-register IC with (only) D-registers, eg. 74ls74
Elementary Electronic Questions :: 06-09-2013 00:03 :: DrWhoF :: Replies: 4 :: Views: 1019
i need to get a pulse detection circuit using 4013 d-flipflop ic or can u suggest 15 v input equivalent of 74ls74 .
Analog Circuit Design :: 11-02-2012 06:06 :: rakesh1987 :: Replies: 2 :: Views: 742
In this case you need to use a Common Anode 7 segment LEDs display.
Seven Segment Display
Common anode to be connected to the Vcc pin.
Look here for an example how to connect the 74ls74 with the 7 segment LED display.
Elementary Electronic Questions :: 01-10-2012 08:47 :: mister_rf :: Replies: 5 :: Views: 636
Is there any 74ls74 quad or octal flip flop equivalent? In need Q as well as Qbar outputs.
Elementary Electronic Questions :: 10-01-2011 09:44 :: neazoi :: Replies: 1 :: Views: 1633
1. I understand that I can't use TTL gates/flip-flops. What's the remplacement in CMOS? I use the following TTL's: 74LS32 (or another multiple input OR gate), 74ls74 (flip-flop)
The ooold metallic-gate CMOS series 4000 and 4500 allow that logic levels (from 0-5 V to 0-15 V).
2. I need t
Elementary Electronic Questions :: 05-25-2011 21:01 :: zorro :: Replies: 1 :: Views: 485
hi i am using 74ls74 for motor driver but its not working i am not geting change in output according change in input i am giving 1 s clk pulse and change in d is 1sec also can any one help me
Microcontrollers :: 05-16-2011 01:31 :: ud23 :: Replies: 2 :: Views: 619
i will be using adc0809 analog-to-digital converter. it needs an external clock and i saw this pic from crankshaft:
the microcontroller's oscillator can provide the adc clock but it needs to be divided by four 74ls74. i was just confused with the connection because the ic have a lot of pins:
Microcontrollers :: 01-20-2011 01:39 :: crankler :: Replies: 6 :: Views: 2120
we are trying to do a project and we have to use a d-flip fliop in schematic editor. what is the most basic part to use?
It depends upon which logic family you want to use, ie. TTL or CMOS
In the TTL family, there is the 7474, 74ls74, etc.
In the 4000 series CMOS there is 4013, 40174, 40175
In the 74H
Elementary Electronic Questions :: 12-13-2010 21:17 :: ljcox :: Replies: 1 :: Views: 1849
If the output should be 1 an undefined amount of time, not just a constant period, before reset, you need a latch or bistable.
Use 74ls74, or 4013, connecting the D and CLK inputs to ground. Use S to set and R to reset.
You can build the same circuit with 2 transistors and some resistors.
Hobby Circuits and Small Projects Problems :: 07-12-2007 08:38 :: Eugen_E :: Replies: 3 :: Views: 2537
I am new to this forum as well as Orcad.
I having some problems simulating a Flip-Flop ( 74ls74 from the psice lib)
When running the simulation I can see the alternating digital output from dstm into the clk of the flip-flop but when monitoring the D Q and QBar of the flip-flop all I see is three red flat lines ie no digital out
PCB Routing Schematic Layout software and Simulation :: 02-08-2007 09:57 :: paragon :: Replies: 5 :: Views: 26464
I just start to learn HDL and choose to study verilog. I try to write D-FF (74ls74), but it shows some errors. I've seen some D-FF example but those did not include preset and clear.
What wrong with my program? Please help me. Thanks alot.
Following is my program by using Xilinx
module dffpc(d, q, preset, clear, clk);
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-02-2005 05:00 :: MRFGUY :: Replies: 1 :: Views: 2809