43 Threads found on edaboard.com: Abstol
They are solution constraints on the simulator and will
have default variable values set, but you should be
able to bump them around as any other variable (in
a SPICE) or at least via some option menu (like
Spectre). What particular simulator?
There are more than RELTOL and abstol, I have
also seen CHGTOL (good for circuits that -need- to
Analog Circuit Design :: 09-23-2009 15:38 :: dick_freebird :: Replies: 8 :: Views: 5642
This is the result of convergence problems. You should look at the documentation for the program to find the .options statements to use to tighten up the tolerance at each calculated point. reltol and abstol are some of these. Tighten them up by 10x and then 100x if necessary to get the waveform you expect.
Software Problems, Hints and Reviews :: 09-24-2003 19:18 :: flatulent :: Replies: 4 :: Views: 3261
.options abstol= absvdc=
to increase accuracy
Analog IC Design and Layout :: 11-22-2004 02:45 :: xuel :: Replies: 3 :: Views: 1613
You can try to increase the value of abstol.
Software Problems, Hints and Reviews :: 12-23-2004 21:46 :: yeechyan :: Replies: 1 :: Views: 1391
PSS simulation is very tricky way to predict oscillation frequency. Transient is better with higher accuracy levels ( increase abstol,iabsoltol,vabstol in simulation option ).
But PSS will also converged if you take care some critic nodes such as floating nodes, short circuited components etc. PSS doesn't like unusual circuit topologies and to avo
Analog IC Design and Layout :: 07-23-2005 20:22 :: BigBoss :: Replies: 4 :: Views: 1353
Use this veriloga file, just connect your clock to this clock
// VerilogA for bmslib, Sig2FreqJitter, veriloga
// last revised: 7/21/03 (ronv)
// Measures the frequency and Jitter of the input signal by detecting
// the times at which the last two zero crossings occured. This method
// will only work accurately on si
Analog Circuit Design :: 12-06-2005 04:07 :: flushrat :: Replies: 1 :: Views: 1435
Heres a simple one.
The circuit has been tweaked a little in order to make the lamp ligthing quite smooth.
First I've increased "Frame per second" to 50 as this helps to make less flickering the lamp, though it requires more CPU resources.
Then I changed some spice parameters to make simulation less accurate but faster; abstol=1e-08 and
Software Problems, Hints and Reviews :: 06-09-2006 04:10 :: Iain :: Replies: 1 :: Views: 1740
most probablt PWL signal will spve ur prob. othrwise try to play with abstol reltol values
Analog Circuit Design :: 08-03-2006 07:08 :: engrvip :: Replies: 5 :: Views: 761
Circular Integrator Operator
Use the circular integrator operator to convert an expression argument into its indefinitely integrated form.
idtmod(expr [ , ic [ , modulus [, offset )
expr is the dynamic integrand or expression
Analog Circuit Design :: 08-10-2006 23:08 :: Teddy :: Replies: 4 :: Views: 4924
I use a very old version of orcad that uses ascii text input and so use the .options command.
If you use a newer version look in the help menu for words like reltol and abstol. These are relative tolerance and absolute tolerance.
PCB Routing Schematic Layout software and Simulation :: 08-18-2006 23:19 :: flatulent :: Replies: 4 :: Views: 2241
simpliest answer is - let say you run transient sim. Then you can choose between conservative, moderate and one more which I forget how they name it.
So if you choose between them and then in analog options look at reltol abstol how it is changed and from there you will see how to change those if you want to increase/decrease accuracy.
Analog IC Design and Layout :: 08-23-2006 01:26 :: Teddy :: Replies: 8 :: Views: 1960
To get accurate results you will have to select reltol and abstol values several orders of magnitude smaller than the default values. Then do the transient analysis for an exactly integer number of input sine wave cycles. Then do the FFT option.
(This is what is done in PSpice, and HSpice may be very similar.)
Analog Circuit Design :: 10-12-2006 22:43 :: flatulent :: Replies: 3 :: Views: 1276
Can anyone tell me the exact meaning of this error and warning which was generated by the TANNER tool/TSPICE . I was executing a circuit for output , when i got this error . I need the meaning of this error and method/procedure to rectify the problem.
Any help would be appreciated !
The errors generated are :
Fatal DC OPPT :
Analog Circuit Design :: 02-26-2007 05:23 :: blowfish :: Replies: 4 :: Views: 1570
It looks like u need to relax ur convergence criteria, as the simulator couldn't find a solution within the specified criteria even when using the minimum allowed time step.
An easy solution is to use Moderate or Liberal setting when choosing the transient analysis, a better solution is to change the reltol,abstol and relref settings in order to
Analog Circuit Design :: 06-10-2007 08:24 :: MSSN :: Replies: 2 :: Views: 1512
I will try to explain better:
From the plot you are showing us, it is clear that you are using Spectre RF, PSS and Pac. My opinion is that the strange result you are getting is due to inaccuracy of simulation settings.
First issue to check are the analog accuracy settings, such as reltol, abstol and so on. To proper simulate IP3 you should decrea
RF, Microwave, Antennas and Optics :: 07-02-2007 23:34 :: Mazz :: Replies: 10 :: Views: 899
I am using spectre RF transient and PSS for VCO simulation.
Initially, i had connected the VCO directly to an output buffer (a differential amp). The output DC voltage of VCO is used to bias the buffer transistors. I also use an initial condition to start-up the oscillation. This setup works fine for me.
However, i want to isolate the VCO fr
RF, Microwave, Antennas and Optics :: 07-04-2007 08:07 :: haadi20 :: Replies: 6 :: Views: 1418
the schematic and simulated waveforms are in the attachment
the problem is there is something wrong with my simulated wvaeform, the ideal output should be start at 0.75V, why, help?
the circuit's netlist is:
vphi1 phi1 0 pulse (0 1.5v 0 200p 200p 4n 10n)
vphi2 phi2 0 pulse (0 1.5v 5n 200p 200p 4n 10n)
Analog Circuit Design :: 07-26-2007 09:01 :: prcken :: Replies: 1 :: Views: 2147
Increase the accuracy of the simulator: reltol, abstol, etc
Analog IC Design and Layout :: 08-20-2007 09:00 :: Humungus :: Replies: 5 :: Views: 1058
i programmed a model in matlab which requires solving differential equations numerically. i used the commands
options = odeset('abstol',1e-20,'RelTol',1e-4);
= ode15s(@odes, , icval1, options);
and wrote the eqns. I have attached the results where i expect a difference. In the image 1.jpg, there are 2 graphs. However, if
Mathematics and Physics :: 12-14-2007 08:06 :: cedance :: Replies: 0 :: Views: 678
Thanks for the information.
I think the newer hspice is getting faster speed by adding in an option to adjust the accuracy. that runlvl is a parameter which can scale all the other tolerence parameters at the same time, e.g abstol, vntol, reltol, etc.
it is not getting real faster, just more features.
Software Problems, Hints and Reviews :: 03-31-2008 01:00 :: Hughes :: Replies: 6 :: Views: 2071
Maybe simulation settings like reltol, abstol ,etc
Analog Circuit Design :: 04-02-2008 04:53 :: safwatonline :: Replies: 6 :: Views: 3276
I am designing a rather high resolution (>15bit) delta sigma ADC. I have a design that's working in MATLAB and I am trying to build the same thing in cadence using Verilog A modeling. Every component I have now is ideal and in verilog A code, so that means no transistors, no resistors and no capacitors. I am using the function laplace_nd to model m
Analog Circuit Design :: 08-21-2008 21:25 :: jowong1 :: Replies: 4 :: Views: 1447
i would suggest to try .option runlvl=6
this is best accuracy mode, and for adc accuracy is important.
other options like reltol,abstol,delmax were creating a lot of problem in term of ease of use so this new .option runlvl automatically sets everything.you can comment other settings.
tstep in .tran does not play any role in simulati
Analog Circuit Design :: 11-26-2009 22:14 :: ankitgarg0312 :: Replies: 3 :: Views: 1562
I am afraid things like SMPS simulations will be slow. You could try the following .options - check with your simulator software for exact function & syntax:
Make sure you haven't set the minimum time step too small in your .TRAN statement
My simulator will also do a fast but lower accuracy simulation for a defined a
Analog Circuit Design :: 02-18-2010 10:19 :: keith1200rs :: Replies: 2 :: Views: 999
See below example of simple verilog-a module,
which shall be instantiated in circuit with frequency
that you would like to measure
module freq_hdl(FO, IN);
electrical FO, IN;
parameter real VDD = 1.8;
parameter real scale = 1.0;
Analog IC Design and Layout :: 04-29-2010 05:15 :: mikersia :: Replies: 5 :: Views: 1591
I've fixed the issue which was causing my simulation to crash.
I changed the abstol VOLTOL and Gmin values to 2 magnitudes less and I got a successful simulation which was approximately what I was expecting. I suspect that my circuit was on the limit of complexity for finding a solution, as making small changes could make the simulation fail aga
PCB Routing Schematic Layout software and Simulation :: 10-26-2010 10:24 :: droseman :: Replies: 2 :: Views: 5711
I have a problem with my spice codes. When I add the precharge circuit, the error appears.
I have this problem only with finfet model. With other types, it works.
.option accurate=1 method=gear delmax=30p
.OPTIONS abstol=1p VNTOL=1u
Analog IC Design and Layout :: 12-04-2010 07:19 :: rosaeidi :: Replies: 6 :: Views: 1671
I have posted the link because they contain the only way I know that can solve problems but you have already done that.
Increase Iteration limit (ITL)
and decrease the accuracy
abstol is the absolute current tolerance (default value is 1pA)
VNTOL is the absolute voltage tolerance (default value is 1uV)
RELTOL is the relative tolerance (default
Power Electronics :: 07-04-2011 12:34 :: alexan_e :: Replies: 14 :: Views: 1942
Try changing following parameter
ITL4: Increase this to 40 from 10
abstol make this to 1n instead of 1p
If this still not resolved, Try using ─UTOCONVERGANCE"
Analog Circuit Design :: 07-20-2011 11:17 :: atripathi :: Replies: 7 :: Views: 2801
In order to solve the convergence problem in my simulation, I wish to set some simulation parameters in Cadence ADE as what I did in Hspice. The parameters that I wish to modify is as follows:
abstol = 1n
CHGTOL = 1p
GMIN = 1n
ITL1 = 5000
ITL2 = 5000
ITL4 = 5000
ITL5 = 0
RELTOL = 0.01
However, I can not find
Analog Circuit Design :: 07-29-2011 06:02 :: yujun61hugh :: Replies: 1 :: Views: 499
Altering the Opamp node as suggested by LvW should resolve the convergence issue, just in case if this still persist, try "AutoConvergance" or increase the ITL4=40 and abstol=1n under Simulation Setting Options.
Hope this helps.
Analog Circuit Design :: 08-11-2011 08:28 :: atripathi :: Replies: 4 :: Views: 933
Try relaxing following simulator parameters
ITL4=50, abstol=1n, VNTOL=100u
Analog Circuit Design :: 11-03-2011 09:53 :: atripathi :: Replies: 2 :: Views: 829
I an new here and this is my first post. I am a newbie to ASIC and as part of my semester project I am implementing a 3TDRAM. I am using 0.13um technology and Cadence Hspice and Spectre tools. I am running into some simulator issues.
1. I initially started in hspice but realised I had to do monte Carlo so i switched to Spectre. But w
ASIC Design Methodologies and Tools (Digital) :: 03-24-2012 18:10 :: nincredible :: Replies: 0 :: Views: 282
It is difficult to know what to suggest because I think the problem is with Altium. I just ran your netlist through my simulator and it is fine.
Look through your documentation at the .OPTIONS. Look for ITL4 and increase it from the default (10 in my simulator). Also PIVREL=0.999 may help. Look at VNTOL, RELTOL and abstol although I rarely fin
Analog Circuit Design :: 03-29-2012 07:44 :: keith1200rs :: Replies: 18 :: Views: 1880
I've been working on a power device macromodel based on abm, but I got stuck in convergence issues (transient analysis) when Vdd goes over 100V
I changed RELTOL, abstol, VNTOL, etc., but I wasn't yet able to have it working with higher voltages.
The model is in the attached pdf. I am using PSPICE from Cadence SPB v16.3
Power Electronics :: 06-13-2012 13:35 :: Regnum :: Replies: 1 :: Views: 302
Did you already try different .IC values, e.g. .IC v(a1)=1 ?
Or reduce the default abstol value:
Analog Circuit Design :: 10-20-2012 07:54 :: erikl :: Replies: 6 :: Views: 1533
I doubt gate resistors will help your convergence problems.
Capacitors can give problems if they have no series resistance and are in parallel with voltage sources (so can create infinite current) but a more likely cause is the IR2110 model. Have you followed the instructions in the IR2110.TXT file with the model, in particular:
PCB Routing Schematic Layout software and Simulation :: 12-14-2012 04:31 :: keith1200rs :: Replies: 7 :: Views: 487
In my transient analysis am getting this error.
my input pulse is like PULSE (0 0.9 0 5N 5N 150N 300N)
.tran 10N 500N UIC
**error** internal timestep too small in transient analysis
time = 0.80000E-11; delta = 0.37253E-22; numnit = 32168
1****** HSPICE -- C-2009.03-SP1 3
ASIC Design Methodologies and Tools (Digital) :: 09-24-2013 00:25 :: srini.pes :: Replies: 0 :: Views: 465
Greetings. I wish to ask for method to create butterfly curve. It's V(q) vs V(qb). When I use DC analysis, I can sweep voltage q and observe voltage at qb, but the voltage q will be a linear increase straight line. If I were to observe the transition of q and qb, i will have to use transient analysis. How do I create a v(q) vs v(qb) butterfly curve
ASIC Design Methodologies and Tools (Digital) :: 11-30-2013 09:22 :: warlocklw :: Replies: 3 :: Views: 657
I would like to measure the power consumption of a circuit, such as an inverter.
The version of Hspice I used is 2012.06-SP2 64-BIT.
The version of BSIM-CMG I used is BSIMCMG106.0.0.
The Hspice file is as follows :
*Sample netlist for BSIM-CMG
.option abstol=1e-6 reltol=1e-6
Analog Circuit Design :: 12-02-2013 23:35 :: devang259 :: Replies: 3 :: Views: 566
Can you share the circuits (as suggested by Mvaseem) or complete circuit (where two of these modules are connected)? This would enable people to have a closure look.
Meanwhile - try following setting and see if this helps
- ITL4= 40
- RELTOL= 0.005
MAX TIME STEP = 50n --- If this works, in next run try increasing this to higher valu
Analog Circuit Design :: 03-01-2014 03:46 :: atripathi :: Replies: 6 :: Views: 486
First, I apologize if I post that thread in the wrong section of the forum, but my question is 2/3 analog 1/3 digital.
I'm making a simple simulation in (H)SPICE of a 1 bit full adder. I'm a bit curious about the current drawn from the supply of my full adder: the current drawn when my input rises and my input gets down has a totally
Electronic Elementary Questions :: 06-25-2014 02:08 :: dnanar :: Replies: 1 :: Views: 268
The Timestep error is not a software bug but it is a common occurrence in Spice simulator simulations when it has a problem converging to a solution in the calculations, often occurring when there is an abrupt change in the simulation voltages, such as the SCR turning on.
A couple things to try:
1. Change the program Integration Method from Tra
Analog Circuit Design :: 08-30-2014 20:25 :: crutschow :: Replies: 3 :: Views: 220