1000 Threads found on edaboard.com: Accumulator Vhdl
I found from Altera's website the following multiplier-accumulator. I doubt it will work because the delta propagation. In the code:
pdt_reg <= a_reg*b_reg;
adder_out <=adder_out +pdt_reg;
will the updated pdt_reg be added to adder_out withou the effect of delta delay? How to handle this?
ASIC Design Methodologies and Tools (Digital) :: 05-04-2006 21:07 :: vistapoint :: Replies: 0 :: Views: 813
i have written the code beneath in vhdl for a mupltiply accumulator and
while it is coming in FPGA port, the led don't provide with the correct
result. is there anyone who knows what the problem is?
Microcontrollers :: 12-14-2006 09:02 :: Tom2 :: Replies: 1 :: Views: 725
I need to make a multiply accumulator in vhdl and i dont have any idea..
As I understand you have 2 inputs and want to MAC
you should implemennt this simple algorithm:
out_next = in1 * in2 + out;
The following simple module can do that:
module mac (in1, in2, out, clk, init);
input clk, init;
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-27-2009 16:47 :: Syswip :: Replies: 2 :: Views: 1097
Im in greate need of a clock divider to be impemented into an FPGA.
Im involved in a project where I need to divide
a clock so I can use it for an UART.
I need detailed and working examples in vhdl so it can be
implemented into an FPGA.
I need to use eg 4MHZ input clock and divide this into
460 800 (= 16* 28 800 baud) with as small e
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-20-2011 03:10 :: nicklas_a74 :: Replies: 8 :: Views: 1449
please can any one give me the vhdl codes for the phase accumulator and the LUT(look up table) required in a numerically controlled oscillator.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-09-2008 15:51 :: anand37 :: Replies: 28 :: Views: 18320
The internal memory blocks of FPGA are generally capable of dual port operation, also with Xilinx Spartan, as far as I know. That means you have one sine ROM, e. g. for one quadrant and can access it at two ports, using different addresses and getting different data output for I and Q. You can use a single phase accumulator that is decoded twice t
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-23-2008 06:16 :: FvM :: Replies: 9 :: Views: 3408
search this forum for phase accumulator program, you will enter your input clock,output clock, and the program will generate the vhdl file for you.
I tried it , and it works well
hope that helps
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-08-2009 14:08 :: medra :: Replies: 3 :: Views: 1184
I am working currently in a project( Virtex-4 FPGA) where i want to add
two signals of 42 bits each with a clock frequency of 200MHz.
So for this addition, I want use only dsp48 accumulator for the first operation.
How to write vhdl code for this, so that it will infer to DSP48 accumulator ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-13-2013 08:17 :: kannan2590 :: Replies: 0 :: Views: 269
Z is a signal.
input is input to the system
this code is placed inside a clocked process.
Your diagram is a simple accumulator.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-27-2013 06:42 :: TrickyDicky :: Replies: 23 :: Views: 785
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments....
For FPGA design, what I have used synthesis tools(only to synthesis vhdl code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar
It is only my personal opinion...
Professional Hardware and Electronics Design :: 07-13-2001 17:19 :: :: Replies: 7 :: Views: 3671
If you want an audio interactive tutor to learn Verilog or vhdl.. I did upload it for someone who did ask me... ES PERAN Verilog & vhdl.
If you are interested let me know
Professional Hardware and Electronics Design :: 08-06-2001 13:01 :: henrik2000 :: Replies: 5 :: Views: 10012
I am a student from Harbin China. Now I am building a behavioral model of a Direct Sequence Spread Spectrum Communication system using vhdl-AMS. So i want to know where can I find some example similar to that or something that may give help to me.
Can you give me some advices. Thank you!
[ This Message was edited by: flybear on
Professional Hardware and Electronics Design :: 10-29-2001 04:17 :: flybear :: Replies: 0 :: Views: 1539
PARWAN is a simple accumulator-based processor
1. vhdl code
(Synthesizable RTL description)
2. level description)
3. library used for fault simulation)
Microcontrollers :: 02-19-2002 05:19 :: jimjim2k :: Replies: 0 :: Views: 4067
vhdl QUICK Reference Guide
Ready for onboard prints
Uploaded file: vhdlref.pdf
Microcontrollers :: 02-21-2002 06:04 :: jimjim2k :: Replies: 2 :: Views: 3180
where to get test bench with vhdl for SDH chip?
Microcontrollers :: 02-22-2002 00:49 :: coolsniper :: Replies: 10 :: Views: 2342
The vhdl Golden Reference Guide
A 136 pps ebook.
Uploaded file: vhdl-golden-reference.pdf
Please don't reply unless you have useful information to add on this post. Thanks !
(No Me-too's, no Thanks-you's, etc ... use
Microcontrollers :: 02-24-2002 06:48 :: jimjim2k :: Replies: 3 :: Views: 7841
Here is the vhdl code for 8051 MC.
Uploaded file: 8051 in vhdl.zip
Microcontrollers :: 02-24-2002 06:59 :: jimjim2k :: Replies: 8 :: Views: 7880
LEON is a synthesisable vhdl model of a 32-bit SPARC* compatible processor, developed by the European Space Agency (ESA) for future space missions. To promote the SPARC architecture and enable development of system-on-a-chip (SOC) devices using SPARC cores, ESA is making the full source code freely available under the GNU LGPL license.
Microcontrollers :: 02-25-2002 09:00 :: jimjim2k :: Replies: 5 :: Views: 3653
vhdl Language reference manual. latest edition.
Please don't reply unless you have useful information to add on this post.
Any other replies are always welcome via PM.
[ This Message was edited by: KARLZ on
Microcontrollers :: 03-01-2002 15:09 :: KARLZ :: Replies: 3 :: Views: 2401
Online vhdl Testbench Generator
1. TestBench Tool
3. -> t
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-02-2002 08:40 :: jimjim2k :: Replies: 6 :: Views: 6709
These materials are made available for ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech.
This text focuses on presenting the basic features of the vhdl language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by fami
Microcontrollers :: 03-02-2002 09:09 :: jimjim2k :: Replies: 9 :: Views: 3347
Anyone interested in a single entity vhdl testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this.
Uploaded file: tb_gen.tcl
Microcontrollers :: 03-04-2002 20:12 :: mexico_mike :: Replies: 2 :: Views: 3801
Would you please upload IEEE Standards
for verilog and vhdl to this place.
1. If you have uploaded files in some other boards, please leave a URL pointer only.
2. Please rename the files before uploading by the a definitive words to distingush files from each other. It seems that the forum replaces every newer file with
Microcontrollers :: 03-05-2002 02:40 :: jimjim2k :: Replies: 0 :: Views: 1651
Which most prefer or popular? vhdl or Verilog?
ASIC Design Methodologies and Tools (Digital) :: 03-09-2002 12:13 :: cadb0y :: Replies: 113 :: Views: 15542
Anyone has a DSP core in vhdl or Verilog? Prefer TI but anyone will do.
Microcontrollers :: 03-14-2002 11:16 :: ASIC :: Replies: 14 :: Views: 5395
Would anyone share the RS232 vhdl code ?
If you have RS232 test program , please share.
Thanks a lot.
Other Design :: 03-30-2002 04:47 :: cssheu :: Replies: 11 :: Views: 13186
Please suggest good books in this thread for vhdl/Verilog ASIC design
ASIC Design Methodologies and Tools (Digital) :: 04-04-2002 05:12 :: antipattern :: Replies: 7 :: Views: 2001
Tutorials for vhdl and Verilog.
HDL Synthesis for FPGAs: Design Guide (PDF 2MB)
SystemC -- Technical Papers
Cypress: Programmable Logic: vhdl Page
Cypress: Design Resources : Technical Articles
Logic Synthesis with vhdl System Synthesis
vhdl SYNTHESIS TUTORIAL
vhdl Coding Style manual (...)
Microcontrollers :: 05-09-2002 06:32 :: jimjim2k :: Replies: 5 :: Views: 3367
signal rd,dr : std_logic;
ad_bus,ram_bus : inout;
process(rd) ---- right.
if (rd='0' and dr='1') then
process(rd) ---- error.
if (rd='0') then
if dr='1' then
ASIC Design Methodologies and Tools (Digital) :: 05-19-2002 10:17 :: 75 sinfocia :: Replies: 9 :: Views: 1195
This object of this course is to introduce the student to more of the vhdl modeling language than what has been covered in previous courses.
1. -> t
Microcontrollers :: 06-09-2002 08:29 :: jimjim2k :: Replies: 0 :: Views: 1466
1. -> t
Microcontrollers :: 07-11-2002 03:09 :: jimjim2k :: Replies: 0 :: Views: 1476
1. -> t
Microcontrollers :: 07-11-2002 04:11 :: jimjim2k :: Replies: 0 :: Views: 1432
is there any software which convert matlab code to vhdl?
how can i get it?
PC Programming and Interfacing :: 07-13-2002 04:04 :: baa110 :: Replies: 32 :: Views: 15241
I am seeking cache controller vhdl example,
I hope some good guy can give me hint or
tell me where I can find it.
It is better a standalone module, simple.
Microcontrollers :: 07-17-2002 14:24 :: john5888 :: Replies: 6 :: Views: 3826
here is a link to comp.lang.vhdl newsgroup about the
necessary of the sensitivity list. very interesting.
PC Programming and Interfacing :: 10-03-2002 09:38 :: kobik :: Replies: 0 :: Views: 1714
Can any body help me if you have vhdl code for BFSK or even clear flowchart
PC Programming and Interfacing :: 12-08-2002 03:06 :: Vonn :: Replies: 0 :: Views: 1536
Is it possible that Vera work with NC-verilog/vhdl ?
ASIC Design Methodologies and Tools (Digital) :: 12-12-2002 09:47 :: DeepIC :: Replies: 7 :: Views: 2675
I need tha vhdl of the PCI LogiCORE interface from Xilinx.. could you help me???
Tnx a lot
PC Programming and Interfacing :: 12-14-2002 09:55 :: Leron :: Replies: 2 :: Views: 1457
Check for updates and fine resources especially on: Microprocessors/MCUs
1. -> t
Microcontrollers :: 12-15-2002 04:25 :: jimjim2k :: Replies: 0 :: Views: 1309
1. -> t
Microcontrollers :: 12-15-2002 07:05 :: jimjim2k :: Replies: 0 :: Views: 1305
Here is the pdf explains the efficient coding style in the vrilog hdl
ASIC Design Methodologies and Tools (Digital) :: 12-18-2002 04:08 :: hynix :: Replies: 4 :: Views: 2699
I am a newbie when it comes to making a clone of an old 16 bit uP
in vhdl. I know there are a lot of gurus around here so here
is my question.
I am looking for a feedback or hindsight on what to expect
when undertaking such a project. Are there any good books written
which might help me in tackling this kind of problem?
I know that
Other Design :: 12-19-2002 06:02 :: LLCD :: Replies: 5 :: Views: 2364
I was thinking of designing a 32 bit alu with vhdl.. I have coded with functionalites add,sub,and,or,etc....(no multiplication and divsion)..
My doubt is i just wrote
when 001-> c<- a and b;
is it this much easy to design an alu.. or I am doing something wrong ..
also How would
ASIC Design Methodologies and Tools (Digital) :: 12-22-2002 07:09 :: eda_wiz :: Replies: 6 :: Views: 4597
Are there any such tools? Preferably for Windows9x or Linux.
PC Programming and Interfacing :: 12-26-2002 18:59 :: the_penetrator :: Replies: 1 :: Views: 2982
vhdl, FPGA, News, Xilinx, EDA, Spanish and English
Software Links :: 12-28-2002 07:23 :: gulson :: Replies: 0 :: Views: 1491
Look at the following URLs for some sort of vhdl resources.
1. -> t
Microcontrollers :: 12-31-2002 06:58 :: jimjim2k :: Replies: 0 :: Views: 1232
Please telll me where I can find some good books in .pdf , .doc about practical desin in vhdl.
Professional Hardware and Electronics Design :: 01-03-2003 19:36 :: Payti :: Replies: 32 :: Views: 4213
say I want to learn vhdl programming.
Where do a start? I'm a complete newbie on this subject.
Is there something like
"vhdl in 24 Hours?"
Professional Hardware and Electronics Design :: 01-06-2003 07:11 :: emdee :: Replies: 6 :: Views: 1260
vho to vhdl translator
Microcontrollers :: 01-06-2003 08:22 :: rohit_tech :: Replies: 0 :: Views: 1276
i would like to simulate my entire circuit containg 74 series ic and 2 fpga .
i would like to see the pspice simulation of the entire circuit alongwith the fpga code. i know it can be done in multisim and i have done it for small vhdl codes. it is no good for large program.
can it be done in orcad 9.2 or PSD 14.2?
what are the other tools which
PCB Routing Schematic Layout software and Simulation :: 01-07-2003 06:05 :: hock :: Replies: 1 :: Views: 2658