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Hello, I found from Altera's website the following multiplier-accumulator. I doubt it will work because the delta propagation. In the code: pdt_reg <= a_reg*b_reg; adder_out <=adder_out +pdt_reg; will the updated pdt_reg be added to adder_out withou the effect of delta delay? How to handle this? LIBRARY ieee; USE ieee.std_log
hello everyone, i have written the code beneath in vhdl for a mupltiply accumulator and while it is coming in FPGA port, the led don't provide with the correct result. is there anyone who knows what the problem is? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity olok
I need to make a multiply accumulator in vhdl and i dont have any idea.. As I understand you have 2 inputs and want to MAC you should implemennt this simple algorithm: out_next = in1 * in2 + out; The following simple module can do that: module mac (in1, in2, out, clk, init); input clk, init; input in
Hi Im in greate need of a clock divider to be impemented into an FPGA. Im involved in a project where I need to divide a clock so I can use it for an UART. I need detailed and working examples in vhdl so it can be implemented into an FPGA. I need to use eg 4MHZ input clock and divide this into 460 800 (= 16* 28 800 baud) with as small e
please can any one give me the vhdl codes for the phase accumulator and the LUT(look up table) required in a numerically controlled oscillator.
The internal memory blocks of FPGA are generally capable of dual port operation, also with Xilinx Spartan, as far as I know. That means you have one sine ROM, e. g. for one quadrant and can access it at two ports, using different addresses and getting different data output for I and Q. You can use a single phase accumulator that is decoded twice t
hi search this forum for phase accumulator program, you will enter your input clock,output clock, and the program will generate the vhdl file for you. I tried it , and it works well hope that helps
Hi all, I am working currently in a project( Virtex-4 FPGA) where i want to add two signals of 42 bits each with a clock frequency of 200MHz. So for this addition, I want use only dsp48 accumulator for the first operation. How to write vhdl code for this, so that it will infer to DSP48 accumulator ?
Z is a signal. input is input to the system this code is placed inside a clocked process. Your diagram is a simple accumulator.
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments.... For FPGA design, what I have used synthesis tools(only to synthesis vhdl code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar It is only my personal opinion...
If you want an audio interactive tutor to learn Verilog or vhdl.. I did upload it for someone who did ask me... ES PERAN Verilog & vhdl. If you are interested let me know Kind regards.
I am a student from Harbin China. Now I am building a behavioral model of a Direct Sequence Spread Spectrum Communication system using vhdl-AMS. So i want to know where can I find some example similar to that or something that may give help to me. Can you give me some advices. Thank you! [ This Message was edited by: flybear on
Hi PARWAN is a simple accumulator-based processor 1. vhdl code (Synthesizable RTL description) 2. level description) 3. library used for fault simulation) 4. h**p://aspire.
Hi vhdl QUICK Reference Guide Ready for onboard prints tnx Uploaded file: vhdlref.pdf
where to get test bench with vhdl for SDH chip?
Hi The vhdl Golden Reference Guide A 136 pps ebook. tnx Uploaded file: vhdl-golden-reference.pdf ************************************************************** Please don't reply unless you have useful information to add on this post. Thanks ! (No Me-too's, no Thanks-you's, etc ... use
Hi Here is the vhdl code for 8051 MC. tnx Uploaded file: 8051 in
Hi LEON is a synthesisable vhdl model of a 32-bit SPARC* compatible processor, developed by the European Space Agency (ESA) for future space missions. To promote the SPARC architecture and enable development of system-on-a-chip (SOC) devices using SPARC cores, ESA is making the full source code freely available under the GNU LGPL license. LEON
Hi vhdl Language reference manual. latest edition. regards _________________ ***************************************** Please don't reply unless you have useful information to add on this post. Any other replies are always welcome via PM. ***************************************** [ This Message was edited by: KARLZ on
Hi Online vhdl Testbench Generator 1. TestBench Tool 3. -> t tnx
Hi These materials are made available for ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech. This text focuses on presenting the basic features of the vhdl language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by fami
Anyone interested in a single entity vhdl testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this. Uploaded file: tb_gen.tcl
Hi Would you please upload IEEE Standards for verilog and vhdl to this place. NOTE!!!!: 1. If you have uploaded files in some other boards, please leave a URL pointer only. 2. Please rename the files before uploading by the a definitive words to distingush files from each other. It seems that the forum replaces every newer file with
Which most prefer or popular? vhdl or Verilog?
Anyone has a DSP core in vhdl or Verilog? Prefer TI but anyone will do. ASIC
Would anyone share the RS232 vhdl code ? If you have RS232 test program , please share. Thanks a lot.
Please suggest good books in this thread for vhdl/Verilog ASIC design Thanks,
Hi Tutorials for vhdl and Verilog. HDL Synthesis for FPGAs: Design Guide (PDF 2MB) SystemC -- Technical Papers Cypress: Programmable Logic: vhdl Page Cypress: Design Resources : Technical Articles Logic Synthesis with vhdl System Synthesis vhdl SYNTHESIS TUTORIAL vhdl Coding Style manual (...)
signal rd,dr : std_logic; ad_bus,ram_bus : inout; :cry: 1. process(rd) ---- right. begin if (rd='0' and dr='1') then ad_bus_out<=ram_bus; else ad_bus_out<="ZZZZZZZZ"; end if; ad_bus<=ad_bus_out; end process; 2. process(rd) ---- error. begin if (rd='0') then if dr='1' then
Hi This object of this course is to introduce the student to more of the vhdl modeling language than what has been covered in previous courses. 1. -> t tnx
Hi P1076.2 P1076.3 P1076.4 ieee_1164 mathpack synopsys 1. -> t tnx
Hi 1. -> t tnx
hi all is there any software which convert matlab code to vhdl? how can i get it? best regards baa110
Hi, everybody, I am seeking cache controller vhdl example, I hope some good guy can give me hint or tell me where I can find it. It is better a standalone module, simple. Thanks :P
here is a link to comp.lang.vhdl newsgroup about the necessary of the sensitivity list. very interesting. :arrow:
Can any body help me if you have vhdl code for BFSK or even clear flowchart Thanks
hi,all Is it possible that Vera work with NC-verilog/vhdl ?
Hi guys! I need tha vhdl of the PCI LogiCORE interface from Xilinx.. could you help me??? Tnx a lot LEron
Hi Check for updates and fine resources especially on: Microprocessors/MCUs 1. -> t tnx
Hi 1. -> t tnx
Hi Here is the pdf explains the efficient coding style in the vrilog hdl :P
all, I am a newbie when it comes to making a clone of an old 16 bit uP in vhdl. I know there are a lot of gurus around here so here is my question. I am looking for a feedback or hindsight on what to expect when undertaking such a project. Are there any good books written which might help me in tackling this kind of problem? I know that
hi all, I was thinking of designing a 32 bit alu with vhdl.. I have coded with functionalites add,sub,and,or,etc....(no multiplication and divsion).. My doubt is i just wrote case (selectinput) when 001-> c<- a and b; likewise.. is it this much easy to design an alu.. or I am doing something wrong .. pleas advise.. also How would
Are there any such tools? Preferably for Windows9x or Linux. the_penetrator?
vhdl, FPGA, News, Xilinx, EDA, Spanish and English
Hi Look at the following URLs for some sort of vhdl resources. 1. -> t tnx
Dears, Please telll me where I can find some good books in .pdf , .doc about practical desin in vhdl. Thanks! -=Payti=-
say I want to learn vhdl programming. Where do a start? I'm a complete newbie on this subject. Is there something like "vhdl in 24 Hours?" :sm16:
vho to vhdl translator
i would like to simulate my entire circuit containg 74 series ic and 2 fpga . i would like to see the pspice simulation of the entire circuit alongwith the fpga code. i know it can be done in multisim and i have done it for small vhdl codes. it is no good for large program. can it be done in orcad 9.2 or PSD 14.2? what are the other tools which