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19 Threads found on Accumulator Vhdl
180 degrees phase shift is just a sign change. For BPSK you don't need both sine waves at the same time, and then there is an even better solution, without a mux. You can do the phase shift by adding/subtracting to the phase accumulator or the address. 180 degrees is probably the simplest case, just invert one bit: address(2). You should not m
As a delayed comment on the post #13 testbench, besides possible problems in the corrected DUT code that hasn't been shown, the testbench misses to assert the reset signal. So unless the DUT uses an initializing statement, the accumulator register will be never reset. P.S.: is this correct in vhdl Clearly no. Please observe
Well the problem will be that i is never set, so because its an accumulator, it will always be uninitialised.
Hi all, I am working currently in a project( Virtex-4 FPGA) where i want to add two signals of 42 bits each with a clock frequency of 200MHz. So for this addition, I want use only dsp48 accumulator for the first operation. How to write vhdl code for this, so that it will infer to DSP48 accumulator ?
The easier way to do this is just calculate a running sum, no need for those intermediate values. Initialize your counter and your running sum, and then add your new value to your existing sum at each sample time (This is called an accumulator, by the way) When your counter reaches its terminal value, you've got your answer in the running sum.
if the adder has 3 ports (a,b, clock), can I just feed b back as input without a one-clock delay? An adder as such doesn't utilize a clock. If the "adder" has a clock input it's most likely an adder with in- or output register. Then the output can be of course feed back to the input, forming an accumulator respectively integrator.
It's basically synthesizable. The accumulator should be changed to simple add with overflow for correct operation. i <= i+ conv_integer(n); Usually a NCO would use a larger bit width for the accumulator and the frequency input and only use the uppermost bits as address to sine/cosine table. I assume, that the frequency input
Hi Im in greate need of a clock divider to be impemented into an FPGA. Im involved in a project where I need to divide a clock so I can use it for an UART. I need detailed and working examples in vhdl so it can be implemented into an FPGA. I need to use eg 4MHZ input clock and divide this into 460 800 (= 16* 28 800 baud) with as small e
I need to make a multiply accumulator in vhdl and i dont have any idea.. As I understand you have 2 inputs and want to MAC you should implemennt this simple algorithm: out_next = in1 * in2 + out; The following simple module can do that: module mac (in1, in2, out, clk, init); input clk, init; input in
hi search this forum for phase accumulator program, you will enter your input clock,output clock, and the program will generate the vhdl file for you. I tried it , and it works well hope that helps
4x4 multiplier can be implemented with a scaling accumulator multiplier which performs multiplication using an iterative shift-add operations. EDIT: check this pdf which contains 4x4 multiplier
Cause a working accumulator involves a clocked register, it must reside in a clocked sequential block. It's possibly a problem of a unsuitable overall design structure. Remember that HDL means hardware description language. It's different from sequential processing implemented with procedural programming languages. The adequate behavioura
please can any one give me the vhdl codes for the phase accumulator and the LUT(look up table) required in a numerically controlled oscillator.
A basic DDS consists of a clocked accumulator with a constant input (the desired frequency), and a ROM containing one sinewave cycle. Connect the most significant bits of the accumulator to the ROM address inputs. The ROM output is your sinewave. If you show us your code, maybe someone can help you debug it.
nco is in fact a accumulator and a lookup table you can realize a accumulator like this process(clk) begin if rising_edge(clk) then acc(23 downto 0) <= acc(23 downto 0) + input; end if; end process; then, you can address the lookup table like this process(clk) begin if rising_edge(clk) then nco_out(7 downto 0) <= rom(conv_
hello everyone, i have written the code beneath in vhdl for a mupltiply accumulator and while it is coming in FPGA port, the led don't provide with the correct result. is there anyone who knows what the problem is? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity olok
Hello, I found from Altera's website the following multiplier-accumulator. I doubt it will work because the delta propagation. In the code: pdt_reg <= a_reg*b_reg; adder_out <=adder_out +pdt_reg; will the updated pdt_reg be added to adder_out withou the effect of delta delay? How to handle this? LIBRARY ieee; USE ieee.std_log
hi i m doing project on pipelined multiplier accumulator... i m writing this code for simulation but there is some problem with wiat for statement Architecture behavioral of Entity mac is up to date. Compiling vhdl file in Library work. ERROR:HDLParsers:1015 - Line 37. Wait fo
Hi PARWAN is a simple accumulator-based processor 1. vhdl code (Synthesizable RTL description) 2. level description) 3. library used for fault simulation) 4. h**p://aspire.