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97 Threads found on edaboard.com: Active Port
First, you can not use any passive/active component in ADS Momentum EM simulations Second, what is your intention to use finite ground underneath of the structure ?? Will it be covered by any GND environment ?? ?? Why not infinite ground ?? Third, there are many "close-in" ports, have you ever select calibration mode well ?? If the thickness of t
yours cannot be solved by software reset. a logic connected to the o/p port pins of 8051 which gets enable signal after a time delay after power-on may be suitable . if you can recode on the software modules , see that the port ststus '0 ' is for active switching level.
There isn't second port.The VCO has two parts, active part and passive part.If you obtain sufficient negative resistance from active side, you design a resonator in according with this active portion the VCO starts to swing.. Your test setup is completely wrong, the transistors are not biased at all. Read (...)
CST has very well elaborated and active online help system if you use the legal software In case of HFSS it is not the case but still type the issue in Google and i am sure you will find lot of help material and examples. The best way is always to start with tutorial
please help me , i want to measure active S parameter of a 2 port MIMO antenna. i know the equation to calculate active s parameter "active SParameters is (S11*a1 + S12*a2)/a1 where a1 is the complex excitation in volts incident on port 1 and a2 is the complex excitation in volts incident on (...)
Different SPI modes involve different active clock edges: You need to review the datsheet of connected interface.
Vcontrol is active low so an unused port must have Vc=high. Thse use depletion mode so current conducts when Vgs=0
Hi All, I have create a little project for school controlled, this project already working and function if I setting for all port, but is something wrong if I use only per port. Well, the scenario I want to configuring : --> portA AN0-AN1-AN2-AN3-AN4 are an input /using button. --> portB, used for LCD, (...)
The brightest, most efficient LED is the best one to choose to operate at low current. The best output is active low on port is 0 an ESR of 0.45V/3.2mA = 140 Ω. Use the voltage drop from Vcc to 3V if it is a White LED and compute the current limiting R including the driver internal 140 Ω. The LED ESR is around 10~15Ω for a 10 mm.
for a two port device it is fairly common that both ports have a negative resistance. But theoretically that might mean it oscillates at two different frequencies, or maybe even starts up at h wrong frequency. So it is best if the load port of the active device is unconditionally stable, and the resonator (...)
Pi match attenuators at all ports would help especially in diode mixer case. active mixers generally don't need very good (and wideband) 50 ohms terminations at the ports. The most important port that requires good termination to get good mixer IMD, is the IF port.
hi, when i try to open or edit hdl files in modelsim 10 it automatically opens the aldec active hdl editor does anybody know how to stop this? thanks
I fear it's not so easy to derive a "typical" impedance characteristic of a grid connected power converter. I presume, you're referring to a grid connected inverter or a bidirectional converter with "active front end" (AFE), in other words a PWM bridge connected through an inductor or LC low-pass filter to the grid. Its impedance is determined by t
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity I2c_master is port( clk : in std_logic; --system clock reset_n : in std_logic; --active low reset SDA : inout std_logic; --data read from slave LED : out std_logic_vector
Hi guys! I just coded a 4 to 2 priority encoder and am getting the following errors: How do I fix these? Here is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity priorityencoder is port(en_l: in std_logic; --active low enable din: in std_logic_vector(3 downto 0); --active
The DSR line is fed to the PC serial port from the Data Set when it is Ready. This can be asserted either by the Modem being powered up or a null modem cable to another Terminal or PC which becomes the DTR signal at the other end. So DSR is detected by the PC which asserts DTR when the serial port is active.
What features are still available when the is in SIM900A sleep mode. I want to double check with someone who has used this feature. Datasheet already has some info. Can it send/receive SMS? (datasheet says yes) Is the serial port available/active? (datasheet says No) How do you wake up from sleep? (datasheet says - pull down DTR or on receiv
You should remember to turn off the other not active LED outputs, when you set a new state.
How is everything connected? What protocol are you using? What is your hardware? If you have the transmit port of both slaves connected to the same input, and they're both active, it's not going to work; you need to have some protocol for slaves to connect and disconnect from the bus.
RAM should be modeled in the following way. RAM modeled without clocks will mostly infer Latches. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity RAM is generic ( K: integer:=8; -- number of bits per word W: integer:=8); -- number of address bits port (WR: in std_logic; --active high write enable
Hi, The WatchDog can only be Enabled or Disabled at programming time by means of the Config Statements. When used with the Sleep instruction it only wakes the pic, it does not Reset it. You can then test any port etc and if not active put it back to sleep, all done in a couple of instructions so little power used. Using the prescaler - if
Doing as FvM says is perfectly good, I just want to add that I have a software, AnTune, that is designed to aid with exactly this kind of job. It is a software that connects with your VNA and live calculates a matching network. It have smoothing and averaging which can be needed if measuring an active transmitter. Semiautomatic port extension is a
change ur entity ; part at end of the entity entity top is port ( clk_in : in std_logic; reset : in std_logic; WEN : in std_logic; -- taken as active high REN : in std_logic; -- taken as active high WADDR : in std_logic_vector(11 downto 0); RADDR : in std_logic_vector(11 downto 0); ram_dout : out std_logic_vector(2 downto 0) ); (...)
By design of the circuit, the output impedance of common drain stage M1 loads the active inductor node, so it can hardly achieve high real impedance values.
Hello All, How to find the asynchronous reset is active high or active low in the design using Design Compiler? As Top level reset port is connected through inverter to some sequential logic and sometimes it is connected through non how to find this...specifically in DC. Thanks & Regards, Maulin Sheth
i have a problem with my coding to change state of leds in pic16f877a when push button is active...i want to change the led pattern in port b, and d when press the push button.. i have 3 condition for this system and of course it can't use 'if' and 'else' right??? anyone please help me???
A RP7150 active Differential Probe is mentioned in the DS4000 manual and seems to be the only active probe presently manufactured by Rigol. Although the interface looks similar to Agilent DSO, it uses 7 instead of 9 pins and is most likely not compatible. Other major manufactorers (Tektronix, LeCroy, Yokogawa) have each their private muti-pin probe
The LO level in a mixer depends by the type of the mixer. Single stage additive (passive or active), single balanced (passive or active), double balanced (passive or active), etc.
What is the S-Parameters for ? An active or Passive device ? One thing you can do is see which ports have the biggest values. Those would most likely be the gain ports or throughput terminals. If S34 has the biggest numbers then port4 is like an input and port3 is the output... i.e. If it is like a (...)
Diamond creates a template VHD file that you can use in your design. This file ends with _tmpl.vhd. It shouldn't be that difficult to implement. I strongly recommend to read the extended datasheet of the XP2. Some of the blocks use active low reset, but I'm not sure if this is the case for the DPRAM.
active s is the reflection coefficient of one port when another port is excited... for example, a 2 port system ,the total reflect wave at port 1 is S11*V1+S12*V2 the total reflection coefficient is total reflect wave at port 1 over total incident wave at port 1,then (...)
You can use SPDT, of course you know which port ia active. And you can use directional antenna, for each branch, you can combine a ref signal.
There is no reason why you should need external pull-ups if you have correctly configured port B's internal pull ups. I have done it like that. Do you have diodes on the output lines to the keypad? You should - to prevent pressing two keys simultaneously from allowing the active output from one line to be shorted into an inactive output (...)
Hello! My Circuit Consists of a PIC16F877A. Pins RB0, RB1, RB2, RB3, RB4 is configured as active high inputs. port D0 is configured as output and is connected to a led. port C (pins C0 to C6) is connected to lcd. I need mikroBasic or mikroC code which uses interrupts to handle the button clicks. The program should display some text (on lcd) (...)
SETUP THE MODULE AT+CMGF=1 ; sets text mode (0 sets Packet Data Mode) AT+CSCS="GSM" ; sets GSM-character text mode AT+CGATT? ; Must return "+CGATT:1" indicates DATA is active TCP GPRS CONNECTION AT+CIPSRIP=1 ; shows you the received information and IP address and port number of the sender. AT+CGDCONT=1,"IP","airtelgprs.com" ; Define PDP C
Dear pancho_hideboo, Thank you for the reply. I changed the PSIN to port, but still get the same error"at least one active port should be defined to run LSSP analysis". You should use analogLib which is supplied with GoldenGate package... Standard analogLib hasn't "ads" view, that's why the simulator doesn't r
Hi Demise, You are displaying the target floor in a seven segment display na... so maximum value will be 9 (0 to 9) so you can make an input port of size (10, like std_logic_vector(9 downto 0)) to act as a switch, for example so if you need to select the target floor as 6, then you need to press the 6th pin as active high,... Means there are 10 s
I want to check if an active one-port network is stable or not under the condition of terminating with a certain passive element at the port. Now, I can write the input impedance of this one-port network. So If I give such network a voltage excitation, I can calculate the response current flowing into the network. From (...)
If it is a normal, not too old type of VNA, without any strange bridges, is it no needed to terminate P2 during S11 measurement. At S11 mode are both RX and TX performed at P1 while P2 is inactive. To be safe, you can easily check if a termination affects measurement result. At S21 mode are both ports active. Normally is P1 TX and P2 is RX.
Hi, do you mean the crystal frequency?? if the crystal frequency is not there then also all port pins will be active high state at power on due to bootloader action. if the crystal oscillator frequency is there then you can see around 2.3V at the pins where crystal is connected.
Hi, I am doing a CMOS active filter circuit using Cadence Virtuoso with 50 Ohms ports at the input and output. After the simulation the results of the filter S21 is good and as expected (high gain, high Q), but the input return loss S11 shows a positive value. I was expecting a negative S11 value... does this has something to do with the simu
Your question isn't complete. We have to know: - is the input rdy synchrounous to clk? You forgot to add clk to the entity port, by the way. - how long rdy will be active? Longer than one clock cycle, possibly even shorter? A typical case would be rdy unrelated to clk and active at least one clk cycle. Then rdy must be syncronized to (...)
When You use pull up resistor with port assigned as input then logic state of the input pin is active high.
Although the PC/motherboard user manual should clarify the com port assignment, you can connect a loopback (or a known working rs232 device) to indentify an active port.
"Γin * Γs = 1" Where did you get that equation? And what do Γin and Γs mean, and why use the = sign? If you had said something like Γactive device * Γresonator >> 1, then it would make some sense. Also you have to realize that the equations of oscillation are different if you are using a one port or two (...)
Sounds like you are trying to make a 8051 output port source current to the opto coupler. As you can read from the data sheet, they aren't intended for this operation, they are just open drain outputs with a weak pull-up. The most simple method would be to operate the output active low rather than active high. If you ever studied 8051 (...)
I want to power my microcontroller board using a 7805 (which receives input power via a DC adapter) and a USB port. Assuming only one of these power sources is active at a time, can i just tie the output of the usb and the 7805 together without using a jumper to select the appropriate power? If I tie the outputs together and use the USB, the OUTPUT
Hello there, I have been designing a active van atta retroreflective antenna with wilkinson power splitter. I am using MESFET amplifier in wilkinson divider to achieve the gain on either side of the antenna(since my divider is two port). Before going to the above step, i have to match the amplifier to the frequency of 9.
If the micro supports analogue inputs then you can use a single pin and a resistor network to give different voltages for each key, not recommended though. Much better way is to have an active serial keypad. If you have 2 port pins you can really use any clock+data protocol. Probably I2C is a good option, then you could use something like a (...)
For this particular application I have a VCO which outputs Fo and Fo/2 and a I/Q demodulator which has an active x2 multiplier on the LO line. Normally, if I had the I/Q demod with no multiplier, I'd have the VCO output going through a coupler to the antenna and the coupled port I would amplify and input as the LO drive, so the downconverted IF