280 Threads found on edaboard.com: Adc And Noise
In addition, there are two flavor of delta sigma adc. Discrete time and continuous time.
Continuous time has inherent anti-aliasing.
Analog Circuit Design :: 01-05-2017 13:39 :: deba_fire :: Replies: 3 :: Views: 565
Without thinking too hard about this, I think you've got a problem. If you lower your gain and, consequently your noise, you're also lowering your resolution, so I don't think you've gained anything. In other words, if you cut your noise by a factor of 2, you're also cutting your resolution by 2.
If I'm reading correctly, if you have 2V (...)
Analog Circuit Design :: 12-08-2016 00:28 :: barry :: Replies: 9 :: Views: 756
Some hints on how to start:
- 0 ~ 30 mA with a resolution of 1?A implies a 15 bit converter. You can find many 16 bits.
- As for the circuit, you have to use an op amp and set its gain to fit the input range of
- In the case you have enough noise (usually it's not a problem), and if your signal is slow (...)
Microcontrollers :: 09-27-2016 09:12 :: doraemon :: Replies: 10 :: Views: 645
I am writing a C code using mikroc and PIC16F676. Here is the code,
#define Dl_Relay PORTC.B2
#define Relay_1 PORTC.B1
#define Relay_2 PORTC.B2
#define Relay_3 PORTC.B3
#define test PORTC.B1
unsigned int mains_val=0,a=0,b=0,k=0,d=0,Average=0;
Microcontrollers :: 08-13-2016 09:41 :: djc :: Replies: 9 :: Views: 908
What is the minimul level of a I/Q signal at the input of tha adc of a SDR that is required to demodulate the signal?
In the document "Software defined radio for the masses IV" is is stated:
"For a weak signal to be recovered,
the minimum analog gain must be great
enough so that the weakest signal to
be received, plus thermal and atmosphe
Digital Signal Processing :: 07-05-2016 07:48 :: yo8tot :: Replies: 6 :: Views: 644
your AD7655 power supply specification is 4.75V ... 5.25V
But USB power supply specification is 4.4V ... 5.25V (wikipedia)
(I thougt USB Spec tells 4.5V ... 5.5V, but I may be wrong)
My experience with USB supply is worse. Especially when drawing more than 100mA, use some longer cables and the use of passive HUBs.
Especially cheap USB cables
Analog Circuit Design :: 07-11-2016 10:05 :: KlausST :: Replies: 13 :: Views: 742
1.) An adc is known for its horrible NF, say 30dB.
A conventional receiver would add LNA & gain in order make the overall NF much lower (through Frii's), say 5 dB.
However, these gain stages add noise themselves.
So if I assume the maximum input swing of my adc is 2Vpp (13 dBm) and I can pick my input power level of the recei
RF, Microwave, Antennas and Optics :: 06-11-2016 13:16 :: pancho_hideboo :: Replies: 12 :: Views: 1089
Could you please tell me what's the relationship between OSR and ELD in continous-time sigma-delta
adc? and why lower OSR is more sensitive to ELD?
Thanks a lot!
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-05-2016 06:11 :: ken_cn :: Replies: 8 :: Views: 617
Hi, when we calculate the SNDR or ENOB in adc, we add all the noise together, i.e., quantization noise, kT/C noise, DNL noise, etc. Let's say DNL is +/- 0.5LSB and LSB=1mV, what's its equivalent noise in terms of mV? Thank you.
Analog Circuit Design :: 02-04-2016 17:33 :: newroad :: Replies: 0 :: Views: 376
How to interface sensor-preasure to 16f877a
we have-voltage and pressure from the sensor
wat to write the code by MPLAB X IDE from adc named- adchelp
Microcontrollers :: 10-24-2015 06:37 :: Amin Ahmed :: Replies: 1 :: Views: 467
hi my friends
i have problem with ground loop noise .what can i do?
this is my circuit:
A simple way to solve this problem, is STAR Topology : All of Ground Nodes connect together in one point only.
in Your Circuit i think the best po
Analog Circuit Design :: 09-19-2015 04:52 :: memarian :: Replies: 1 :: Views: 473
I have written Matlab script for BPSK modulation. The way my code works is as follow:
series of 0 and 1----> NRZ data (continuous rectangular pulses with amplitude -1 and 1)--->multiply by carrier----> add noise--> multiply by carrier---> integration--->detection---> Bit Error collection?
I would like to know can
Digital communication :: 07-10-2015 23:02 :: David83 :: Replies: 5 :: Views: 1218
Using a voltage divider to 50 Ohms and coax feed to Spectrum Analyzer on analog preamp out may help isolate noise by viewing spectral density. Examine noise above f/2 sampling rate also.
- - - Updated - - -
I recall designing something with 12 bit adc using Burr Brown Hybrid in 70's and had no difficulty gett
Elementary Electronic Questions :: 06-23-2015 15:35 :: SunnySkyguy :: Replies: 5 :: Views: 771
using VCC as reference....
Are you sure it is stable enough, free of noise, filtered?
It seems you built a motor control with PWM. Then there are high power pulses. I recommend to start conversion at a dedicated point of PWM. Then the values schould be stable and reliable.
Do you have a picture of your circuit / PCB layout. Especially powe
Microcontrollers :: 06-08-2015 08:25 :: KlausST :: Replies: 2 :: Views: 1082
I have just joined this forum looks like a great place.
I have just made this Volt ammeter with the 16F877A.
I am came across the post about adc Value Fluctuating in PIC Voltmeter and Ammeter LCD PIC16F877A which I have the same problem.
From what i have been reading it's been solved.
I'm just not to sure what "There was wiri
Microcontrollers :: 06-07-2015 21:27 :: musovern :: Replies: 1 :: Views: 776
it depends on your power supply filtering, but usually using a linear power supply is better and you can achieve better results. Normally in microcontrollers there is no internal ripple or switching noise rejection, (because it needs large capacitors or inductors (in Chip Scale)) , and usually they have an extra power pin for (...)
Microcontrollers :: 06-07-2015 10:25 :: memarian :: Replies: 8 :: Views: 818
I have a Kinetis MCU design that senses temperature from a PTD using the internal 16-bit adc. It also has a UART that I use as a console port for development. When the UART is plugged in (to a FTDI cable), the adc input is very stable with all samples within a 3 unit range. When I unplug the UART, the samples are much noisier with a range of about
Elementary Electronic Questions :: 05-14-2015 13:52 :: RogerFL :: Replies: 1 :: Views: 382
I have written a code for 8255 PPI but I am having three problems.
1. In the code comment out all code inside the while(1) loop and un-comment lcd_string(*msg); which is before while(1) loop and Compile and run.
LCD displays proper string if there is no character repeated i.e., string "EDABOARD" is printed as EDABOARD but (...)
Microcontrollers :: 04-11-2013 10:13 :: jayanth.devarayanadurga :: Replies: 3 :: Views: 1721
I would use a MCP9701 or MCP9701A from Microchip. They are inexpensive, cover the temperature range you want with sufficient accuracy and best of all, produce an analog output voltage which is already scaled to suit a standard adc. They can also drive large capacitances so you can easily filter out any noise picked up on (...)
Analog Circuit Design :: 12-30-2014 14:45 :: betwixt :: Replies: 8 :: Views: 992
In theory, a pH probe produces about 59 millivolts (mV) per pH unit, and at pH 7 (neutral pH) the probe produces 0 volts. A typical pH probe conducts 1~2nA thus represents an impedance ~ 600mV/1nA=600M approx.
Naturally a FET input Op Amp is needed such as a TL071 but the INA116 gives better CMRR for stray Efield noise.
You must choose a bette
Analog Circuit Design :: 08-29-2014 13:44 :: SunnySkyguy :: Replies: 3 :: Views: 820
Thanks for the reply.
I have attached a schematic of CS5467.
I am using with 12 bit resolution. The adc counts are not stable. Even I am not getting good stable 10 bit data. 103522103523
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-24-2014 06:05 :: ravi1488 :: Replies: 3 :: Views: 1036
First of all whats your application is it for load cell application. Both hardware and software holds the key in getting better results. post your code, schematic and adc result. Nau7802 is not that accurate compared to other adc, also noise from power supply affects the result.
Microcontrollers :: 07-23-2014 05:19 :: dhimullai :: Replies: 2 :: Views: 1732
Ok, probably not the answer you're looking for, but how about a noise source(diode) and an adc?
First you state that you want "maybe a bit more" than a single FF and gate, and then you talk about 8 LFSRs, which is way more than "a bit more".
There's a bunch of stuff on the net (where I'm sure you've (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-16-2014 16:31 :: barry :: Replies: 12 :: Views: 1055
I have VERY LIMITED experience in SAR adc design. Would you tell me how to tackle the noise and to estimate the resolution of the comparator? Thanks
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-11-2014 02:31 :: diodelite :: Replies: 0 :: Views: 478
The types of filters used to prevent aliasing in adc's in theory are called Nyquist filters, which define the stop bandwidth fSTOP must be <= 1/2 of the sampling rate.
The implementation however is a tradeoff between distortion from noise above fSTOP , group delay distortion in the passband, amplitude ripple in the (...)
Analog Circuit Design :: 06-16-2014 12:24 :: SunnySkyguy :: Replies: 12 :: Views: 2124
Fluctuations of a few LSB steps are normal operation with PIC built-in adc. You need to average multple samples to get reduce the noise. For the explanation of DC offset, we should look at the schematic.
Microcontrollers :: 06-12-2014 19:00 :: FvM :: Replies: 6 :: Views: 1378
I am studying adc now and understood 1LSB=FS/2^n.
I got confused when input becomes single-ended to differential input.
for example, input common mode voltage is 0.5V and reference voltage is 1V.
then maximum input range which is full scale range is 1V for single-ended.
but when fully differential input is applied, I think input (...)
Analog Circuit Design :: 06-08-2014 17:10 :: justinsong :: Replies: 3 :: Views: 763
. It depends on your sampling rate. adc is linear but your detector is not.
Do you want to only track changes in Vac over long term or short term interruptions or do statistics Avearage & deviations ?
quasi RMS with Peak, P-p or rectified average
I would use LPF noise filter and rectified average with another LPF.
200Hz LPF (...)
Elementary Electronic Questions :: 05-12-2014 03:37 :: SunnySkyguy :: Replies: 3 :: Views: 841
I have a 100kbps BPSK modulated signal at 1 Ghz.
Usually one downconverts (Oscillator+Mixer) the signal and recovers the Data and Clock using an adc and DSP.
Since we have a BPSK signal can't we just detect the phase changes and filter out the transmitted 100kbps signal? No (...)
Digital Signal Processing :: 04-18-2014 08:37 :: kurtulmehtap :: Replies: 2 :: Views: 844
sir i am doing 8 Bit folding 8 interpolating adc in cadence. plz tell me how to calculate INL,DNL factor using calculator option of cadence tool. is there any other way to calculate INL,DNL factor.
How to calculate noise margin and SFDR ?
Analog Circuit Design :: 03-14-2014 05:42 :: subhasmita2201 :: Replies: 0 :: Views: 998
Separate analog and digital grounds may be a solution in some cases.
The general problem with separate GND planes is where to connect them. You'll notice, that data sheets of mixed signal devices, e.g. adc, DAC, ?Ps with analog functions usually claim to get the separate GNDs connected directly at their respective pins. It's a clever suggestion
Analog Circuit Design :: 03-07-2014 18:34 :: FvM :: Replies: 17 :: Views: 1099
Because the circuit uses the 5V as the reference for the adc, it is sensitive to any noise on the 5v rail. Try connecting a 1000uF capacitor across the supply, does it improve it? I assume that you are using a ripple free well regulated 5V supply.
Microcontrollers :: 02-10-2014 02:31 :: pjmelect :: Replies: 6 :: Views: 1197
Attached is the output from a Lock-in amplifier simulation. I need to filter this out to DC for feeding it into a MAX1416 Sigma-Delta 16-bit adc.
What factors should I consider? I planned to design a Sallen-Key LPF with some gain using an online calculator. Do you think the signal is too small to be filtered and amplified with a single stage 2nd
Elementary Electronic Questions :: 02-01-2014 10:46 :: jonnybgood :: Replies: 1 :: Views: 469
I have a circuit that consists of an analog sensor, some signal conditioning, and an adc (ADuCM360). Everything is powered off the same supply. The adc supply can be anywhere between 1.8 and 3.6 V. From an adc noise performance standpoint, I'm trying to decide if there's any (...)
Analog Circuit Design :: 12-09-2013 14:48 :: tomk :: Replies: 2 :: Views: 418
Just wanted to share my project and solution for coping with the noise in OOK RF modules. Not sure if this was discussed before and certainly someone thought of this long before me
but I couldn't find much of information on-line, so it still might be useful to someone.
I had a project that needed an RF transmission (1000 bps) (...)
Microcontrollers :: 10-23-2013 05:14 :: trastikata :: Replies: 4 :: Views: 832
Changing gain will effect adc update rate?
No, PGA gain and update rate are indepent settings.
Both adc and PGA incorporate noise sources, by varying the update rate and gain, the output noise level will be changed. The relation between update rate and (...)
Analog Circuit Design :: 09-26-2013 06:30 :: FvM :: Replies: 2 :: Views: 625
I presume a low-pass would attenuate the IF frequency and thus the sampled signal.
VGA and adc bandwith is 10x more then my signal frequency.
What do you mean with signal frequency? IF? Baseband?
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-20-2013 15:38 :: FvM :: Replies: 4 :: Views: 640
In Continuous Time Delta Sigma adc, there are two options in Feedback DAC generally.
(1) Current DAC
(2) Voltage DAC or Resistive DAC
Regarding thermal and flicker noise, (2) have advantage.
Regarding calibration for multi level DAC, (1) have advantage.
Regarding speed, (1) have advantage.
(1) occupy large area than (2) (...)
Analog Circuit Design :: 09-02-2013 02:45 :: pancho_hideboo :: Replies: 0 :: Views: 673
I have the feeling that the amplifier is increasing the whole received signal Z(t) = S(t) + n(t) (S(t) - useful signal, n(t) - noise) and is not affecting the SNR.
Only in the world of ideal components. Amplifier noise adds to existing input noise, also adc quantization noise (...)
Elementary Electronic Questions :: 06-24-2013 17:52 :: FvM :: Replies: 4 :: Views: 842
I get digital data from the adc. the Sampling frequency of the adc is 600KHz. the Analog signal has the frequency 150KHz. Should i built a digital bandpass filter a after the adc to filter the noise (harmonics) and offset created by the adc. what are the critical (...)
Digital Signal Processing :: 06-22-2013 21:34 :: yasine79 :: Replies: 4 :: Views: 796
First, you need a comparator with a low-overdrive prop
delay of maybe 1nS - if you want to allocate 1nS to input
settling time including kickback noise, and 0.5nS to the
encode logic. If you want single cycle latency which is
the whole idea of a flash.
"Low overdrive" means VIN/2^(N+1) roughly - give it half
of the "bin" voltage for overdrive an
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-20-2013 17:27 :: dick_freebird :: Replies: 1 :: Views: 502
I have read that in adc it is desired to have a small input capacitance. Could anyone explain to me the reason?
Analog Circuit Design :: 04-10-2013 13:57 :: Osawa_Odessa :: Replies: 5 :: Views: 405
I am trying build 14 bit cyclic adc. To reduce noise floor by removing 1/f and offset, i am doing auto-zeroing.
In the figure auto-zeroing and gain setup is given.
even though i am doing auto zeroing the 1/f noise is not getting reduced in pssnoise analyis.
and one (...)
Analog Circuit Design :: 04-03-2013 09:16 :: shamala :: Replies: 0 :: Views: 527
Hi guys!I have designed a flip around SHA for a 10 bit 80 MHz pipelined adc, yet the fft analysis results are very bad, the peaks of the harmonics are very high and there's too much noise. I wonder if it's because I didn't use bootstrapped switches or it' the problem with my amp or anything else. I have attached some net lists (...)
Analog Circuit Design :: 03-22-2013 07:48 :: zoe88 :: Replies: 0 :: Views: 514
If you only need it for adc clock would be better to include a PLL to boost freq. Putting a single ended 500 MHz into a chip from outside will likely have jitter degradation. Also would have poor duty cycle predictability. Jitter performance for adc is usually strick and poor jitter means poor adc noise (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-20-2013 15:29 :: FvM :: Replies: 9 :: Views: 814
I have read that using averaging reduces the noise during adc reading. Using more number of samples for averaging further reduces the noise.
Can someone please let me know the mathematical relationship between RMS noise and no. of samples used for averaging for an adc?
I have a data (...)
Professional Hardware and Electronics Design :: 03-07-2013 09:31 :: knikhil271083 :: Replies: 1 :: Views: 639
I'm designing a oscillator for an ultra low power/voltage application, and I have some problems to define the maximum phase noise that is necessary to avoid the adc(sigma-delta) resolution degradation. The intention is to design a 16KHz oscillator, that will be used with a 14 bits adc, with 1KHz (...)
Analog Circuit Design :: 02-27-2013 18:28 :: jucampos :: Replies: 0 :: Views: 504
Before to treat fluctuation... check calculus..
For your calculus you are mixed int and floating point values ?
you better have to use long integer ...
What is your max voltage input ? 35V ?
so with a divider of 4.7K and 36K , you will get 35*4.7/36
4.04V on adc input for 35V DC
and for full scale of 5V , (...)
Microcontrollers :: 05-15-2014 16:43 :: paulfjujo :: Replies: 12 :: Views: 6791
I am trying to simulate an adc on verilog-A, using MOSFET models generated from TCAD tools.
In order to quantify adc performance in terms of SNR etc. I need to include noise in my simulations too.
Can someone help to identify where I can include noise sources in the simulation process and how (...)
Analog Circuit Design :: 02-02-2013 07:24 :: batmanbeginz :: Replies: 0 :: Views: 443
I have an adc board which I'm trying to improve by getting rid of some noise (although it does work fine now). The board from left right is basically an adc <-> buffer <-> microcontroller <-> FT232R. There are 0.01uF and 10uF caps at each of the chips. Power comes from a 7805 regulator. Using a scope I look
PCB Routing Schematic Layout software and Simulation :: 12-06-2012 01:17 :: myle00 :: Replies: 0 :: Views: 733