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6 Threads found on edaboard.com: Adc Clock Buffer
hi every one i am designing sar adc 26 Mhz and design input buffer as two stage ota with folded cascode as a core i wanna make my buffer switchable which work in the sampling phase and be off the rest of the clock to save power how can i make it ? can i switch on vdd i.e connect vdd in sampling and disconnect in the (...)
I need to design a reference buffer for a successive approximation adc. This adc uses a capacitive DAC array. What is the procedure to determine the reference buffer specifications such as gain , bandwidth, settling time etc. ?? Is there a document outlining this ??
I think you should connect LM35 directly to the adc or through unity gain buffer. In this case, the voltage fed to the adc doesnt reflect exact temperature shown by LM35.
Dear all , I am designing a pipelined SAR adc with having clock freq.>160MHz. i want to design an input driving circuit for this high speed adc. which is the most conveniet method to drive pipelined SAR adc having clock frequency >160MHz ? using OP AMP with RC circuit or transfor
My project need to supply a frequency-adjustable clock to a adc , and require the clock's jitter less than the same time , we need put a copy of the clock to a FPGA which receives datas from the adc. Now I know I can use VCO controlled by PLL to get low jitter clock , and I can use a (...)
i am trying to design a reference voltage buffer for switched -cap adc stage, which has a working clock up to 100~160Mhz. I need a wide-band opamp to get setting time shorter... but dont know where to begin with. any hint,spec,topology about wide-band opamp will be appreciated P.S.since the adc works at 160MHz, i (...)