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1000 Threads found on Adc Design Verilog
No It is not possible to 'design' an adc or dac using vhdl/verilog. However it is possible to 'model' an adc or dac using vhdl/verilog You dont HAVE to use ams if you dont want to. Simple adc and DAC can be modelled using simple vhdl/verilog hope it helps, Kr, Avi
adc is mostly implemented with analog circuit(r-2r adc,flash adc)... so not possible to write verilog code
HAI ALL, can someone tell me about the SAR adc design FLOW. I HAVE SEEN EXAMPLE of control logic unit in SAR in Tanner but the circuit is too complex to built using schematic(full custom). I cant find other ckt in ttech paper as people do not show the complete ckt . is it true if i assume that the logic unit was synthesize from FRONT end tool such
i'm going to design a multi-channel adc design ,which architecture should i choose? (SAR ,sigma-delta,pipeline)? The key parameter is 200MSBP and 8~9bit thanks
hi i presume that you already had course in analog ic design and cmos concepts. then, read the chapter on adcs in p.allen book. first understand the different architectures in adcs....know the diff blks in your concerned architecture and then study each blk in detail. For detail study books like CMOS A/D and D/A converters by Rudy van de (...)
Hi, I am curious how to determine loop-gain for 10bit adc design. Since static error is 1/To (To: DC loop gain), for 10bit adc, is error should be less than VFS/2^10 or 0.5*VFS/(2^10). I heard VFS/2^10 is being used for static error, but I think a half of VFS/2^10 makes more sense...
i m doing sigma delta adc design now. does anyone help me to find some article about MATLAB simulation please. Just search EDAboard, you'll find a lot of somthing that you care!!!
I start to do a low power/high performance pipelined adc design, and read some lectures and thesis, but I still puzzle some question: 1. there are many materials about delta-sigma adc modeling, but little about pipelined adc behavial modeling in simulink, how to start it? 2. what's the practical flow of (...)
can anyone tell me that , does adc design comes under mixed signal design or can we still call it as a pure analog design? And can we do all it's simulations in SPICE or do we need some othere tool for front end design???
SAR adcs with speeds of 50MSPS at 10bits have been acheieved. There is a paper in this years ISSCC from IMEC. This has the best figure of merit also.
i would like to know some reference regarding adc design steps for various kind of adc please send me link
I am designing a 6-bit adc for a linear input. The linear input for my adc is coming from a temperature sensor. The temperature sensor's output is 0.3 at -40°c and 0.7 at 125°c. I have attached the architecture of this design, I take it from a journal. The problem that I am facing right now is that the (...)
Which adc design is better for moderate speed and less chip area? as compair with flash adc.
Hi, We're working on a pipeline adc design and we need some help here. Our question is on the spec of the op. We're asked to get settling correct within 1/4 LSB when we input a sine wave of frequency Fs/2 of full-scale amplitude. 1) we did ask our professor what that means but we didn't really get it. so can anybody help us understand what th
Dear All : How do define the settling time in the sigma delta adc design . Thnaks
Hi, all I am very new for SAR adc design, I am going to design a 10MHz SAR adc, but I only need to work out the SAR logic part, the rest components I can use IC. 1. Any recommended IC for Voltage Comparator and DAC? 2. Is there any IC for CLOCK generation, if so, what?s the model? Many Thanks!
Can anyone give me some recommendation of good adc design books? Thanks a lot
Yes.. 70MS/s means the sample clock is running at 70MHz.. Also the input bandwidth of the adc means the maximum frequency of input which the adc can sample with accuracy less than 1/2 LSB. This bandwidth may or may not be equal to your 1/2*sampling rate... But this bandwidth should always be greater than half the adc sampling rate.
1\in pipeline adc design, we need to maesure SNR\THD\INL\DNL\SFDR,but what parameters in circuit are related to them separately?and if one of them or more don't meet the requirement,how to improve them(such as THD and SFDR)?and what method can be used?pls help me. 2\in sc-cmfb circuit,there are two cap C1 and C2(C1 connected Vo+\Vo- and C2 conne
Hi people...i am currently working on the design of high speed flash adc design.can anyone help me out what are the trade off's between different specification and comparator topology chosen????and what are the issues regarding flash adc design. ..thanks to everyone for reading this out...hoping ur (...)
Hi, I am trying to simulate a 10 bit 80Ms/s pipeline adc using verilog A models for switch and amplifier, but when i extract the output codes and plot fft i get only around 30 dB. The output codes are fine as i checked them using a ramp test and have no missing codes. I have tried this for different input frequencies and different sampling
hi there, Does anyone know why is dynamic comparator (rather than preamp+latch) frequently used in pipeline adc design? what is the advantage of it compared to other structures?
Hi, friends I have to look for a adc design, target 0.35um cmos process, 12-bit SAR adc with 1MS/s rate, +/- 1 LSB INL。if you can design this, or have something similar, or any helpful information, please let me know, thanks a lot! I only design digital logic before, although there is some (...)
I am doing adc design. In the layout design, the digital part is used standard cell and the analog part is draw by myself. But when i do the LVS check, it generated a error, "gnd! shots to gnd" (gnd! is the global ground for standard cell; gnd is the pin I created for analog part). Can any one help me to solve this problem?
Hello, i am working on SAR adc design in cadence schematic composer..i am getting proper ouput from shift register but after shift reg. to SAR register ,not getting proper output...can any one help me? for 5-bit DAC , shift register output is 10000 but therotically,we get out of 2.5v for vref=5v..but practically, i get 0.3125mv.. a
Hi What is the best know SA-adc design up to now?
I want to find DNL in flash adc design.I need to find my circuit is working properly or not? How the flash adc design track input sin signal wrt reference voltage
I have VERY LIMITED experience in SAR adc design. Would you tell me how to tackle the noise and to estimate the resolution of the comparator? Thanks
You can look for tutorials.. But why not do it yourself? Do you know any HDL? As far as I remember, this adc uses an SPI communication protocol and is quite easy to operate...
hi all i am asystem designer of a 9 bit pipelined adc , and i want some help in this work , and some books and data about that , thanks alot
Someone who can recommend some tutorials / manuals / ... regarding verilog design and synthesis? Thanks and best regards, S. 8)
I am designing a 8bit 100MHz Pipeline adc, and the result puzzled me. The structure is 1.5bit/stage *5 + 3bit/last stage. The result is that 1Lsb is always wrong. Can someone give some advise ? Or point some key notation? Additions: In this design, there are a S/H circuit, gain stage(include OTAs), dynamic Comparator, and bias circuit. (...)
i want to design 16 bit sigma delta adc.can i do it with switch cap sigma delta using "boser wooley" paper from JSSC paper. moreover what is the adv/disadv of using continuous time sigma deta over switch cap sigma delta.
Hi, The max offset a comparator can have depends on the resolution of the adc. If it is a 8bit adc, then the offset should be less than 1lsb at 8bit level. A good design will be offset <1/2 lsb. The settling time and slew rate of the comparator also depends on the conversion speed. hope this helps. Bakers book has some fundamentals (...)
hi,everybody! i want to learn design of sigma-delta adc, please introduce some book or paper to me. thanks a lot! good luck to you!
tsmc 0.35um Process ,, It is a little hard , We have implement 80M/12bit pipeline adc , We use 0.18um process , almost MOS we use .35um , but in the critical part we use 0.18um MOS , Like OTA . That OTA can get more high gain . high BW
If I want to design a 12bit, 65 or 80MHz pipeline adc, how can I get the various modules' parameters, such as the sample resolution, OTA gain, and so on, who can give me a advice or introduce some papers? For some reasons, I have to use hspice in windows to simulate my design and only have a TSMC .35 level49 model, is it enough to achieve my (...)
I have been looking for some ideal / behavioral model of a pipeline adc for a couple of weeks until i found your forum last week. I did find some interesting topics, someone also mentioned about a verilog-A model for the pipeline adc. But i couldnt find it in this website. perhaps someone can help me to find verilog-A (...)
have anyone have books about design adc or have schematic of adc 8 bits .
except for what sankudey said ,i think the experience is also very'd better find one that had design adc circuit and follow to him work for a wile. regards
Hello all! I design a 12 bit charge redistribution adc. I made an overview of many IEEE JSSC articles and books and stopped on Gilbert Promitzer IEEE article "12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation adc with 1 MS/s". But I have no some problems. Following the idea from this article I (...)
Hi All, I need to design a 4 bit Flash adc in 150nm technology. Can someone suggest me some basic books/docs/ieee papers/web links.. to first get a basic understanding of design. Thanks in advance , Regards, Abhi
I am beginning to design a sigma-deta adc,which book should i refer to?
The operation of the SAR-adc based on charge redistribution
use in this manner a resitor divider-unity gain Opamp -adc convertor.... now a days u get really good adc in market... 12,14-bit adc are reliable...
It is difficult to design so high speed 10bit adc in 0.18um process
Hello, what are the best references to understand pipeline adc's and design them circuit level. many thanks
Hello, what are the best references to understand pipeline adc's and design them circuit level. many thanks
Dear All, I would like to learn about adc's and specially pipelined adc's, so can anyone send me a good reference which I can use to start understanding the adcs theory and system design from scratch. Thanks, Best Regards,
Dear all, I need to simulate my design with another design which was done already in verilog. module in verilog will communicate with the design in VHDL. I did simulation of my design in VHDL using a test bench, but for practical reasons I need to used the other (...)