68 Threads found on edaboard.com: Adc Design Verilog
adc is mostly implemented with analog circuit(r-2r adc,flash adc)... so not possible to write verilog code
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.03.2006 05:47 :: eda_wiz :: Replies: 4 :: Views: 3681
HAI ALL, can someone tell me about the SAR adc design FLOW. I HAVE SEEN EXAMPLE of control logic unit in SAR in Tanner but the circuit is too complex to built using schematic(full custom). I cant find other ckt in ttech paper as people do not show the complete ckt . is it true if i assume that the logic unit was synthesize from FRONT end tool such
Analog IC Design and Layout :: 14.09.2006 05:35 :: KKramer2000 :: Replies: 5 :: Views: 2513
No It is not possible to 'design' an adc or dac using vhdl/verilog.
However it is possible to 'model' an adc or dac using vhdl/verilog
You dont HAVE to use ams if you dont want to. Simple adc and DAC can be modelled using simple vhdl/verilog
hope it helps,
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.09.2007 05:59 :: avimit :: Replies: 4 :: Views: 1500
i am asystem designer of a 9 bit pipelined adc , and i want some help in this work , and some books and data about that ,
Analog Circuit Design :: 15.03.2006 03:20 :: Mado_eng :: Replies: 3 :: Views: 651
I want to model a adc in verilog and use it in digital simulation. My purpose is to make this behavior the same interface as the true analog one and use it in a digital SOC environment. Write some testbench to test its connection.
My problem is how to model the analog input because it is one bit width signal, how do I model the different i
ASIC Design Methodologies and Tools (Digital) :: 15.10.2007 01:35 :: wy21century :: Replies: 2 :: Views: 1135
Hello . I have a bare 10bit pipeline adc design , and would like the create the top level interface . So to allow it to interface to mcu etc ? How do I do that , any example like in verilog for example ? Never didi it before as I more towards analog ?
Hope u guys can share example/knowledge ?
Thx in advance.
Analog IC Design and Layout :: 24.07.2008 23:49 :: wls :: Replies: 0 :: Views: 567
I am designing adc in verilog. The first block i need to design is a sampler. The specifications are as follows
Signal frequency : 1KHz
Sampling Frequency : 2Khz
over samppling : 10 % of sampling
So the new sampling frequency is 2.2 KHZ...
Can anyone give some idea how to implement. No code is (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.12.2008 23:55 :: deepu_s_s :: Replies: 0 :: Views: 473
Could you help me on the following questions:
1. Which information are included in the verilog model?
2. In which design flow we must use the verilog model?
3. How to deal with the analog signal in verilog model? Can anybody show me a example about adc or DAC model?
ASIC Design Methodologies and Tools (Digital) :: 30.05.2004 12:40 :: ajianer :: Replies: 1 :: Views: 974
I request any question about adc with FPGA or PLD.
How can I make adc with FPGA or PLD?
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.07.2004 02:40 :: picus :: Replies: 3 :: Views: 1879
I am designing a 16 bit sigma delta adc in cadence. I am not able to design a decimation filter in CMOS... can any one suggest me any circuit
Analog IC Design and Layout :: 04.09.2004 02:42 :: naomi :: Replies: 3 :: Views: 1776
I'm looking for a behavioral verilog or vhdl model of an adc? Type of adc does not matter. Anyone can help?
Analog Circuit Design :: 10.12.2004 23:18 :: rakko :: Replies: 178 :: Views: 55424
1. Read Books: Analog Integrated Circuits design by David & Martin.Get fundamental understanding of adc.
2. Select adc type, and find some papers on IEEE JSSC to try reference design.
System level simulation using Simulink or verilog-A is necessary.
Analog Circuit Design :: 11.12.2004 21:51 :: zmliu :: Replies: 12 :: Views: 1429
i agree...cadence should be sufficient.....for the adc which i designed i did use cadence... spectre simulation....and it was for 16-bit...
Analog Circuit Design :: 07.01.2005 21:30 :: chaitu2k :: Replies: 7 :: Views: 1235
I think case study is helpful , I once saw a case study provided by cadence named "Top Down Modeling and Test Bench Development Verification Case Study: Pipeline adc" ,it is quite good
Analog Circuit Design :: 25.01.2005 23:11 :: dayang :: Replies: 12 :: Views: 1406
is there a good simulation testbench for adc simulation available? thanks!
Analog IC Design and Layout :: 05.02.2005 01:39 :: crazyamd :: Replies: 3 :: Views: 983
i wrote FIR filter and adaptive filter code in verilog i wanna test this code using matlap 7. i read articles from mathworks web. they said we can interface simulink and modelsim. if any one has already experience in this area. pls help me. i wanna know my code is functional and logically correct.
is it possible i can put adc ->MODEL
Digital Signal Processing :: 08.02.2005 19:01 :: aravind :: Replies: 1 :: Views: 1905
Choose a FIR or IIR filter to design.
Choose a suitable sampling frequency.
Choose the number of taps and coeffcients to determine the frequency response of your digital filter.
Run simulation on Matlab-Simulink and make adjustment of your design.
Implement it either using DSP Processor, FPGA/CPLD or Custom IC.
If you want quic
Analog IC Design and Layout :: 11.09.2005 08:12 :: SkyHigh :: Replies: 3 :: Views: 2413
adc dac pll and son on
you can get many many example in this board
Analog Circuit Design :: 26.09.2005 22:25 :: sunking :: Replies: 11 :: Views: 1365
Can you tell us more about your adc and clock, and why you are having difficulty?
The common technique is to design one timing sequencer that controls both the FIR filter and the adc, so you have full control of everything.
Digital Signal Processing :: 01.01.2006 22:40 :: echo47 :: Replies: 7 :: Views: 2810
thank u tarkyss and aravind for your valuable answers,
i sorry that my question was a bit unclear.
the filter i want to implement is to be used in an integrated adc (fixed coefficients), so lets assume i want to implement a Decimation filter.....how do i go about implementing it in verilog?.....sounds easy to u, but not to me :D
so if some
ASIC Design Methodologies and Tools (Digital) :: 01.03.2006 03:30 :: nijMcnij :: Replies: 4 :: Views: 1151
either vhdl-ams or verilog-ams is a good choice.
search the ebook upload/download forum for a delta-sigma adc top-down design book.
Digital Signal Processing :: 01.03.2006 21:31 :: imon :: Replies: 1 :: Views: 759
i am about to start work on an charge redistribution SAR adc, however, i would like to do the so called system level simulations in Matlab/Simulink.
can someone please shed some light on this matter, maybe provide a reference also.
Analog Circuit Design :: 04.03.2006 15:28 :: nijMcnij :: Replies: 2 :: Views: 1072
You can find verilog models of op-amps. etc from the semiconductor manufacturer. Most will provide models on their web sites. You can also look at :
Which has some ideal models.
However, you are posting into a programmable logic forum. None of these analog solutions will ever be implemented
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.03.2006 21:32 :: banjo :: Replies: 5 :: Views: 6475
if the adc here is Anolog Digtial Converter, the first thing to design the interface is send a clock to adc.
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.04.2006 07:10 :: coolsniper :: Replies: 8 :: Views: 12325
Can anyone help me to find matlap model for pipe-lined adc?
I am just starting to study the pipelined adc's from scratch and need some guidance
Thanks in advance,
Analog Circuit Design :: 05.09.2007 14:10 :: mmohsen :: Replies: 19 :: Views: 13012
i have read the allen's book about the i want to design the circuit and simulation for it.but i donnt know how to start.the software i know is cadence and matlab.and i know use the verilog-a to design the DAC and the verilog to decimator and filter.But i am not sure.
Also,can anyone tell me the procedure in detail？
Analog Circuit Design :: 12.09.2007 03:57 :: Yanhui :: Replies: 18 :: Views: 2875
I'm undertaking a project involving Analog to Digital Converter (adc). From what i know, one way to implement this adc in verilog is by using a DAC and comparator. Basically this method is based on the Successive Approximation. The problem with this design is that it is slow as it requires many comparisons. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.11.2007 21:52 :: simonmada :: Replies: 2 :: Views: 583
So I am desingning a SA adc. The problem I am having is that how can I design the Successive Approximation Register (SAR). Do I design it using state diagrams?
If I use state diagrams (Moore State) to design it, then I will have to draw A LOT state diagrams for a SA adc that can convert 8 bits. State (...)
Analog Circuit Design :: 05.02.2008 20:43 :: firsttimedesigning :: Replies: 18 :: Views: 11172
I need to convert readings from sensor in analog voltage to binary fixed point Q2.13 format. (I hope this is the right place to ask...)
Is this something easy to do with discrete adc on stripboard? Any suggestions on components?
Hobby Circuits and Small Projects Problems :: 02.03.2008 22:59 :: hani nik :: Replies: 3 :: Views: 2017
Hello guys . Wanted to design serial 8/10 bit SAR adc ( something like AD7995 4-Channel, 10-Bit adc with I2C-Compatible ) . But I am more towards analog , know little about digital ? Anyone got example ( state-machine/verilog for the control etc ) to do something like AD7995 ? May be I will do it without channel ? Single (...)
Analog IC Design and Layout :: 22.04.2008 04:56 :: wls :: Replies: 5 :: Views: 805
I am designing a flash adc. As you know, it is composed of the array of comparators and the digital encoder. I have a question about the encoder.
The encoder is designed by using transistors in spectre or the netlist in verilog in practice.
Analog Circuit Design :: 30.05.2008 22:12 :: linrb :: Replies: 2 :: Views: 666
I am designing a rather high resolution (>15bit) delta sigma adc. I have a design that's working in MATLAB and I am trying to build the same thing in cadence using verilog A modeling. Every component I have now is ideal and in verilog A code, so that means no transistors, no resistors and no capacitors. I am (...)
Analog Circuit Design :: 21.08.2008 21:25 :: jowong1 :: Replies: 4 :: Views: 1392
I am looking for a synthesizer and a simulator for verilog with analog / verilog -AMS or something that would let me include analog parts in my design such as an op-amp / DAC / adc etc.
I searched google for such a tool for hours and did not find anything.
I would prefer a free tool... but tell me about it (...)
Software Requests :: 04.10.2008 10:57 :: Lord Loh. :: Replies: 2 :: Views: 338
I am using ic5141 and wrote a simple verilog-ams code for 1-bit DAC where input is digital signal and output is analog.After that i instantiated in schematic window for simulating it.
I reffered manuels to simulate this but i am not getting any proper idea for simulating mixed design.
For simulating any design, is it compulsory to (...)
Analog Circuit Design :: 25.12.2009 09:12 :: VINAY_RAO :: Replies: 0 :: Views: 651
Thats what I was expecting, glad you stated it explicitly!
Assuming you'll be targeting Xilinx devices.
It has what you call Delay Locked Loop(DLL), instead of PLL. To utilize DLL in your design you have to generate and instantiate HDL module in you design. Xilinx core generator will take parameter like multiplication/division factor to gene
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.02.2010 00:46 :: Jack// ani :: Replies: 5 :: Views: 782
hay every one, i am new to verilog, tried to make some small programs like clock etc. now i want to design an adc chip as one of my course projects. actually i want to design a chip that works as and adc if the mode pin is high and DAC if its low. plz gude me out, and suggest me that if its a nice project or (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.06.2010 15:23 :: princez :: Replies: 6 :: Views: 5464
how about adc/DAC design.
if u want a bit more complicated.. PLL.
ASIC Design Methodologies and Tools (Digital) :: 10.06.2010 08:55 :: somu.atluri :: Replies: 12 :: Views: 4844
I'm doing a graduation project about Delta-Sigma adc i started with the system level design using schreier tool and his book " Understanding Delta-Sigma Data converters" . I'm now determined with my OSR , Order , BW and DR . Now i'm asked to do a modelling for thoses parameters using verilog.A blocks in Cadence.
Analog Circuit Design :: 26.02.2011 10:38 :: egyeng1 :: Replies: 11 :: Views: 1105
SOC design is a term used for integration of smaller subsystems into a single system block on a single IC.
A microcontroller is a "system on chip". It integrates the CPU core and various peripherials (USB , SPI , I2C , adc etc...) on the same IC.
A SOC can be implemented on either FPGAs or ASICs (wich is termed VLSI).
ASIC Design Methodologies and Tools (Digital) :: 20.01.2012 10:55 :: shaiko :: Replies: 1 :: Views: 451
i design sar adc and there is a proplem in sar logic code
the command @(initial_step) saw the first command only (ex. see counter=0) and the other statement repeated in code and i want to make them initial only
this is the code
// verilogA for try, try, veriloga
Analog Circuit Design :: 07.02.2013 15:45 :: amr hema :: Replies: 0 :: Views: 399
There wont be any different in serial interface and parallel interface of adc.
If you developed for one channel it can be repeated for 16 channel. Upto my knowledge there wont be any difference for each channel.
If it is yes please share the data sheet.
Things has to taken care while design adc interface are sample rate and sampling (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.02.2013 06:10 :: sureshaa :: Replies: 3 :: Views: 851
I am designing a sigma delta adc using cadence (ic 4151),at 90nm technology.but i want to design it using ams verilog,so i want to know what are the library files that are required to carry out the designing procedure..The cadence licence which i am using doesnt contain the amsLib file ,so can i (...)
ASIC Design Methodologies and Tools (Digital) :: 14.03.2013 05:48 :: soumya guru :: Replies: 0 :: Views: 271
as I know , many analog design use C for delta_sigma modulator
and someone use matlab(simulink) design delta_sigma recently..
but it is idea case condition ..
and I know a tool called "smash " dolphin provide a mix mode simulation
maybe sometime we can use mix mode tool simulation whole chip
because deltaSigma AD need
1. frontend --> del
Professional Hardware and Electronics Design :: 18.06.2003 05:31 :: andy2000a :: Replies: 19 :: Views: 7963
It depends on the application. If you want to use it for adc the choice depends on the number of bit of resolution you need in the final ouput and you may ignore the LSBs.
Digital Signal Processing :: 24.12.2003 03:29 :: brmadhukar :: Replies: 2 :: Views: 3275
The easiest way to generate the code for your D/A simulation is to build an ideal adc with a sinewave input source. Then use its output to drive your DAC. HSPICE should have macro model capability to handle this.
Analog Circuit Design :: 07.04.2004 03:07 :: willyboy19 :: Replies: 4 :: Views: 2128
In your case I asume that the clock signal from Analog block is coming properly. But the moment it goes to digital domain you are seeing an unknown state for some time on the clock signal.
So you may have to check the adc(Analog to digital converter) models the tool is picking and placing on the clock signal. The threshold vol
ASIC Design Methodologies and Tools (Digital) :: 29.03.2005 05:44 :: akp494 :: Replies: 3 :: Views: 1369
There are some solutions.
1. Using matlab to generate the digital sine wave.
2. Using verilog-A to write a ideal adc, and then generate digital sine wave. In this case, you should use some simulator like spectre.
Analog Circuit Design :: 25.08.2005 12:28 :: nathanee :: Replies: 11 :: Views: 1907
I would try VHDL-AMS or verilog-AMS; they both have the big advantage when dealing with top-down design that you can start from a high-level behavioral description down to transistor level simulation in the same application (AdvanceMS from Mentor, Smash, SystemVision, Simplorer)...
You can even mix different levels of abstraction: e.g. your Opam
Analog Circuit Design :: 17.10.2005 03:27 :: shpongle :: Replies: 10 :: Views: 1394
im not quite sure abt all this testbed(cct) for testing pipeline adc performance such INL,DNL,SNDR & FFT using Cadence. Do anyone have some testbench cct for these performance metrics ? i knw it need to be done in transient.. but how about testbed signals ???
Analog Circuit Design :: 09.11.2005 07:58 :: pnanda65675 :: Replies: 5 :: Views: 2034
My background is analog. I need to estimate roughly the number of equivalent gates of a digital filter, a decimator for delta-sigma adc converter.
Is there a "best practice rule" to estimate this number based on the filter order, word length, ... ? Or do I have to design this filter, write some VHDL or verilog and run through a (...)
ASIC Design Methodologies and Tools (Digital) :: 01.06.2006 05:37 :: shpongle :: Replies: 3 :: Views: 797