1000 Threads found on edaboard.com: Adc Design Verilog
No It is not possible to 'design' an adc or dac using vhdl/verilog.
However it is possible to 'model' an adc or dac using vhdl/verilog
You dont HAVE to use ams if you dont want to. Simple adc and DAC can be modelled using simple vhdl/verilog
hope it helps,
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-04-2007 05:59 :: avimit :: Replies: 4 :: Views: 1559
adc is mostly implemented with analog circuit(r-2r adc,flash adc)... so not possible to write verilog code
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-14-2006 05:47 :: eda_wiz :: Replies: 4 :: Views: 3786
HAI ALL, can someone tell me about the SAR adc design FLOW. I HAVE SEEN EXAMPLE of control logic unit in SAR in Tanner but the circuit is too complex to built using schematic(full custom). I cant find other ckt in ttech paper as people do not show the complete ckt . is it true if i assume that the logic unit was synthesize from FRONT end tool such
Analog IC Design and Layout :: 09-14-2006 05:35 :: KKramer2000 :: Replies: 5 :: Views: 2586
i'm going to design a multi-channel adc design ,which architecture should i choose? (SAR ,sigma-delta,pipeline)?
The key parameter is 200MSBP and 8~9bit
Analog IC Design and Layout :: 12-12-2004 10:00 :: qslazio :: Replies: 13 :: Views: 2049
i presume that you already had course in analog ic design and cmos concepts. then, read the chapter on adcs in p.allen book. first understand the different architectures in adcs....know the diff blks in your concerned architecture and then study each blk in detail. For detail study books like CMOS A/D and D/A converters by Rudy van de (...)
Analog Circuit Design :: 03-17-2006 13:14 :: Karthikeya :: Replies: 6 :: Views: 1673
Hi, I am curious how to determine loop-gain for 10bit adc design.
Since static error is 1/To (To: DC loop gain), for 10bit adc, is error should be less than VFS/2^10 or 0.5*VFS/(2^10).
I heard VFS/2^10 is being used for static error, but I think a half of VFS/2^10 makes more sense...
Analog Circuit Design :: 04-24-2006 13:56 :: ee484 :: Replies: 0 :: Views: 440
i m doing sigma delta adc design now. does anyone help me to find some article about MATLAB simulation please.
Just search EDAboard, you'll find a lot of somthing that you care!!!
Analog Circuit Design :: 04-30-2006 04:10 :: shaq :: Replies: 2 :: Views: 767
I start to do a low power/high performance pipelined adc design, and read some lectures and thesis, but I still puzzle some question:
1. there are many materials about delta-sigma adc modeling, but little about pipelined adc behavial modeling in simulink, how to start it?
2. what's the practical flow of (...)
Analog Circuit Design :: 07-22-2006 23:47 :: ultra-neo :: Replies: 3 :: Views: 1239
can anyone tell me that , does adc design comes under mixed signal design or can we still call it as a pure analog design?
And can we do all it's simulations in SPICE or do we need some othere tool for front end design???
Analog Circuit Design :: 08-03-2006 06:46 :: engrvip :: Replies: 4 :: Views: 946
SAR adcs with speeds of 50MSPS at 10bits have been acheieved. There is a paper in this years ISSCC from IMEC. This has the best figure of merit also.
Analog Circuit Design :: 02-06-2008 11:14 :: fredflinstone :: Replies: 11 :: Views: 1758
i would like to know some reference regarding adc design steps
for various kind of adc
please send me link
Analog Circuit Design :: 08-27-2006 03:53 :: alpeshchokshi :: Replies: 5 :: Views: 808
I am designing a 6-bit adc for a linear input. The linear input for my adc is coming from a temperature sensor. The temperature sensor's output is 0.3 at -40°c and 0.7 at 125°c. I have attached the architecture of this design, I take it from a journal.
The problem that I am facing right now is that the (...)
Analog Circuit Design :: 09-07-2006 22:51 :: mcsquare :: Replies: 0 :: Views: 620
Which adc design is better for moderate speed and less chip area?
as compair with flash adc.
Analog Circuit Design :: 12-01-2006 22:14 :: manish12 :: Replies: 3 :: Views: 619
We're working on a pipeline adc design and we need some help here. Our question is on the spec of the op. We're asked to get settling correct within 1/4 LSB when we input a sine wave of frequency Fs/2 of full-scale amplitude.
1) we did ask our professor what that means but we didn't really get it. so can anybody help us understand what th
Analog Circuit Design :: 04-10-2007 11:20 :: airboss :: Replies: 2 :: Views: 723
Dear All :
How do define the settling time in the sigma delta adc design . Thnaks
Analog IC Design and Layout :: 01-03-2008 23:45 :: mitgrace :: Replies: 0 :: Views: 814
I am very new for SAR adc design, I am going to design a 10MHz SAR adc, but I only need to work out the SAR logic part, the rest components I can use IC.
1. Any recommended IC for Voltage Comparator and DAC?
2. Is there any IC for CLOCK generation, if so, what?s the model?
Analog Circuit Design :: 03-07-2008 21:46 :: s0g0 :: Replies: 1 :: Views: 971
Can anyone give me some recommendation of good adc design books?
Thanks a lot
Analog IC Design and Layout :: 05-14-2008 12:37 :: bageduke :: Replies: 0 :: Views: 522
Hi, I have some questions about adc design, please.
1. What does the parameter of Msample/s in adc or DAC design maen, please? For example, 70 Msample/s.
What determine this parameter? Is there any relation between it and the sample clock?
2. How to determine the bandwidth of the amp in the adc to fit the (...)
Analog Circuit Design :: 06-21-2008 01:51 :: gaom9 :: Replies: 4 :: Views: 548
1\in pipeline adc design, we need to maesure SNR\THD\INL\DNL\SFDR,but what parameters in circuit are related to them separately?and if one of them or more don't meet the requirement,how to improve them(such as THD and SFDR)?and what method can be used?pls help me.
2\in sc-cmfb circuit,there are two cap C1 and C2(C1 connected Vo+\Vo- and C2 conne
Analog Circuit Design :: 12-04-2008 08:55 :: lhlbluesky :: Replies: 1 :: Views: 977
Hi people...i am currently working on the design of high speed flash adc design.can anyone help me out what are the trade off's between different specification and comparator topology chosen????and what are the issues regarding flash adc design. ..thanks to everyone for reading this out...hoping ur (...)
Analog Circuit Design :: 01-30-2009 08:58 :: vaibhav_ns :: Replies: 1 :: Views: 1025
I am trying to simulate a 10 bit 80Ms/s pipeline adc using verilog A models for switch and amplifier, but when i extract the output codes and plot fft i get only around 30 dB. The output codes are fine as i checked them using a ramp test and have no missing codes.
I have tried this for different input frequencies and different sampling
Analog IC Design and Layout :: 05-01-2009 05:43 :: steadymind :: Replies: 3 :: Views: 3019
Does anyone know why is dynamic comparator (rather than preamp+latch) frequently used in pipeline adc design? what is the advantage of it compared to other structures?
Analog Circuit Design :: 09-21-2009 08:13 :: henrywent :: Replies: 0 :: Views: 1035
I have to look for a adc design, target 0.35um cmos process, 12-bit SAR adc with 1MS/s rate, +/- 1 LSB INL。if you can design this, or have something similar, or any helpful information, please let me know, thanks a lot!
I only design digital logic before, although there is some (...)
Analog IC Design and Layout :: 01-25-2010 19:46 :: catrat :: Replies: 1 :: Views: 1273
I am doing adc design. In the layout design, the digital part is used standard cell and the analog part is draw by myself. But when i do the LVS check, it generated a error, "gnd! shots to gnd" (gnd! is the global ground for standard cell; gnd is the pin I created for analog part). Can any one help me to solve this problem?
Analog Circuit Design :: 03-30-2010 09:15 :: liushaotao :: Replies: 1 :: Views: 690
i am working on SAR adc design in cadence schematic composer..i am getting proper ouput from shift register but after shift reg. to SAR register ,not getting proper output...can any one help me?
for 5-bit DAC , shift register output is 10000 but therotically,we get out of 2.5v for vref=5v..but practically, i get 0.3125mv.. a
Analog IC Design and Layout :: 08-18-2010 07:23 :: piyush.kanodiya :: Replies: 0 :: Views: 658
What is the best know SA-adc design up to now?
Analog IC Design and Layout :: 09-19-2010 07:19 :: jimjim2k :: Replies: 4 :: Views: 1510
I want to find DNL in flash adc design.I need to find my circuit is working properly or not? How the flash adc design track input sin signal wrt reference voltage
Analog IC Design and Layout :: 06-04-2014 06:28 :: abhilashkumar :: Replies: 0 :: Views: 246
I have VERY LIMITED experience in SAR adc design. Would you tell me how to tackle the noise and to estimate the resolution of the comparator? Thanks
Analog IC Design and Layout :: 07-10-2014 22:31 :: diodelite :: Replies: 0 :: Views: 149
Is there anyone familiar with the BASYS2 PmodAD1 (adc) using verilog???
Need a great tutorial about it.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-17-2014 11:54 :: blackmage :: Replies: 3 :: Views: 322
i am asystem designer of a 9 bit pipelined adc , and i want some help in this work , and some books and data about that ,
Analog Circuit Design :: 03-15-2006 03:20 :: Mado_eng :: Replies: 3 :: Views: 668
Someone who can recommend some tutorials / manuals / ... regarding verilog design and synthesis?
Thanks and best regards,
ASIC Design Methodologies and Tools (Digital) :: 01-05-2004 15:24 :: mlxsae :: Replies: 8 :: Views: 3497
I am designing a 8bit 100MHz Pipeline adc, and the result puzzled me.
The structure is 1.5bit/stage *5 + 3bit/last stage. The result is that 1Lsb is always wrong. Can someone give some advise ? Or point some key notation?
Additions: In this design, there are a S/H circuit, gain stage(include OTAs), dynamic Comparator, and bias circuit. (...)
Analog Circuit Design :: 06-24-2004 04:21 :: GaryHan :: Replies: 3 :: Views: 1204
i want to design 16 bit sigma delta adc.can i do it with switch cap sigma delta using "boser wooley" paper from JSSC paper.
moreover what is the adv/disadv of using continuous time sigma deta over switch cap sigma delta.
Analog Circuit Design :: 04-16-2005 01:03 :: avinash :: Replies: 6 :: Views: 1379
The max offset a comparator can have depends on the resolution of the adc. If it is a 8bit adc, then the offset should be less than 1lsb at 8bit level. A good design will be offset <1/2 lsb.
The settling time and slew rate of the comparator also depends on the conversion speed.
hope this helps.
Bakers book has some fundamentals (...)
Analog Circuit Design :: 09-09-2005 10:24 :: fredflinstone :: Replies: 4 :: Views: 1546
i want to learn design of sigma-delta adc, please introduce some book or paper to me.
thanks a lot!
good luck to you!
Analog Circuit Design :: 09-03-2005 04:34 :: ithink :: Replies: 1 :: Views: 577
tsmc 0.35um Process ,, It is a little hard ,
We have implement 80M/12bit pipeline adc ,
We use 0.18um process , almost MOS we use .35um , but in the critical part we use 0.18um MOS , Like OTA . That OTA can get more high gain . high BW
Analog IC Design and Layout :: 09-07-2005 02:17 :: mitgrace :: Replies: 4 :: Views: 975
If I want to design a 12bit, 65 or 80MHz pipeline adc, how can I get the various modules' parameters, such as the sample resolution, OTA gain, and so on, who can give me a advice or introduce some papers? For some reasons, I have to use hspice in windows to simulate my design and only have a TSMC .35 level49 model, is it enough to achieve my (...)
Analog Circuit Design :: 09-06-2005 10:25 :: carlyou :: Replies: 2 :: Views: 970
I have been looking for some ideal / behavioral model of a pipeline adc for a couple of weeks until i found your forum last week. I did find some interesting topics, someone also mentioned about a verilog-A model for the pipeline adc. But i couldnt find it in this website.
perhaps someone can help me to find verilog-A (...)
Analog IC Design and Layout :: 02-13-2006 10:27 :: jallix :: Replies: 0 :: Views: 1368
have anyone have books about design adc or have schematic of adc 8 bits .
Digital Signal Processing :: 02-25-2006 04:33 :: anhtuan :: Replies: 2 :: Views: 874
except for what sankudey said ,i think the experience is also very important.you'd better find one that had design adc circuit and follow to him work for a wile.
Analog Circuit Design :: 05-04-2006 21:10 :: tuza2000 :: Replies: 6 :: Views: 2058
I design a 12 bit charge redistribution adc. I made an overview of many IEEE JSSC articles and books and stopped on Gilbert Promitzer IEEE article "12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation adc with 1 MS/s".
But I have no some problems. Following the idea from this article I (...)
Analog IC Design and Layout :: 06-07-2006 04:05 :: vladimir1984 :: Replies: 10 :: Views: 2978
I need to design a 4 bit Flash adc in 150nm technology.
Can someone suggest me some basic books/docs/ieee papers/web links.. to first get a basic understanding of design.
Thanks in advance ,
Analog Circuit Design :: 06-16-2006 04:35 :: abhi_123 :: Replies: 1 :: Views: 688
I am beginning to design a sigma-deta adc,which book should i refer to?
Analog Circuit Design :: 07-16-2006 22:11 :: janet :: Replies: 0 :: Views: 494
The operation of the SAR-adc based on charge redistribution
Analog IC Design and Layout :: 09-12-2006 01:46 :: hspice2008 :: Replies: 3 :: Views: 1043
use in this manner
a resitor divider-unity gain Opamp -adc convertor....
now a days u get really good adc in market...
12,14-bit adc are reliable...
Analog Circuit Design :: 10-27-2006 13:06 :: tom_hanks :: Replies: 6 :: Views: 654
It is difficult to design so high speed 10bit adc in 0.18um process
Analog Circuit Design :: 11-17-2006 03:37 :: pfd001 :: Replies: 3 :: Views: 516
what are the best references to understand pipeline adc's and design them circuit level.
Analog IC Design and Layout :: 05-03-2007 00:52 :: nijMcnij :: Replies: 8 :: Views: 1406
what are the best references to understand pipeline adc's and design them circuit level.
Analog Circuit Design :: 05-03-2007 00:52 :: nijMcnij :: Replies: 7 :: Views: 1378
I would like to learn about adc's and specially pipelined adc's, so can anyone send me a good reference which I can use to start understanding the adcs theory and system design from scratch.
Analog Circuit Design :: 06-11-2007 01:29 :: mmohsen :: Replies: 1 :: Views: 987
I need to simulate my design with another design which was done already in verilog. module in verilog will communicate with the design in VHDL.
I did simulation of my design in VHDL using a test bench, but for practical reasons I need to used the other (...)
ASIC Design Methodologies and Tools (Digital) :: 07-12-2007 04:07 :: Mirzaaur :: Replies: 3 :: Views: 2231