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Adc Design Verilog

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22 Threads found on edaboard.com: Adc Design Verilog
Hi! I am a new user of ovm (I used to work with vhdl/verilog based verification methodology) I am trying to develop a verification environment for a design that communicates with an external adc( spi protocol: cs, sclk etc) I have some questions: As I need a model to emulate the behaviour of the adc, should I (...)
I am designing a sigma delta adc using cadence (ic 4151),at 90nm technology.but i want to design it using ams verilog,so i want to know what are the library files that are required to carry out the designing procedure..The cadence licence which i am using doesnt contain the amsLib file ,so can i (...)
i design sar adc and there is a proplem in sar logic code the command @(initial_step) saw the first command only (ex. see counter=0) and the other statement repeated in code and i want to make them initial only this is the code // verilogA for try, try, veriloga `include "constants.vams" `include (...)
hay every one, i am new to verilog, tried to make some small programs like clock etc. now i want to design an adc chip as one of my course projects. actually i want to design a chip that works as and adc if the mode pin is high and DAC if its low. plz gude me out, and suggest me that if its a nice project or (...)
how about adc/DAC design. if u want a bit more complicated.. PLL. Good luck.
hi,, I am using ic5141 and wrote a simple verilog-ams code for 1-bit DAC where input is digital signal and output is analog.After that i instantiated in schematic window for simulating it. I reffered manuels to simulate this but i am not getting any proper idea for simulating mixed design. For simulating any design, is it compulsory to (...)
Hi all, I am designing adc in verilog. The first block i need to design is a sampler. The specifications are as follows Signal frequency : 1KHz Sampling Frequency : 2Khz over samppling : 10 % of sampling So the new sampling frequency is 2.2 KHZ... Can anyone give some idea how to implement. No code is (...)
Hi... I am looking for a synthesizer and a simulator for verilog with analog / verilog -AMS or something that would let me include analog parts in my design such as an op-amp / DAC / adc etc. I searched google for such a tool for hours and did not find anything. I would prefer a free tool... but tell me about it (...)
I am designing a rather high resolution (>15bit) delta sigma adc. I have a design that's working in MATLAB and I am trying to build the same thing in cadence using verilog A modeling. Every component I have now is ideal and in verilog A code, so that means no transistors, no resistors and no capacitors. I am (...)
Hello . I have a bare 10bit pipeline adc design , and would like the create the top level interface . So to allow it to interface to mcu etc ? How do I do that , any example like in verilog for example ? Never didi it before as I more towards analog ? Hope u guys can share example/knowledge ? Thx in advance. Regards.
hi,everyone I am designing a flash adc. As you know, it is composed of the array of comparators and the digital encoder. I have a question about the encoder. The encoder is designed by using transistors in spectre or the netlist in verilog in practice.
Hello guys . Wanted to design serial 8/10 bit SAR adc ( something like AD7995 4-Channel, 10-Bit adc with I2C-Compatible ) . But I am more towards analog , know little about digital ? Anyone got example ( state-machine/verilog for the control etc ) to do something like AD7995 ? May be I will do it without channel ? Single (...)
i have read the allen's book about the i want to design the circuit and simulation for it.but i donnt know how to start.the software i know is cadence and matlab.and i know use the verilog-a to design the DAC and the verilog to decimator and filter.But i am not sure. Also,can anyone tell me the procedure in detail?
No It is not possible to 'design' an adc or dac using vhdl/verilog. However it is possible to 'model' an adc or dac using vhdl/verilog You dont HAVE to use ams if you dont want to. Simple adc and DAC can be modelled using simple vhdl/verilog hope it helps, Kr, Avi
I design a decimation filter(in verilog) for a 1-bit oversampled sigma-delta adc. But I don't have any idea to verify it. Could anyone give me a hand? Thanks a lot!
HAI ALL, can someone tell me about the SAR adc design FLOW. I HAVE SEEN EXAMPLE of control logic unit in SAR in Tanner but the circuit is too complex to built using schematic(full custom). I cant find other ckt in ttech paper as people do not show the complete ckt . is it true if i assume that the logic unit was synthesize from FRONT end tool such
either vhdl-ams or verilog-ams is a good choice. search the ebook upload/download forum for a delta-sigma adc top-down design book.
Can you tell us more about your adc and clock, and why you are having difficulty? The common technique is to design one timing sequencer that controls both the FIR filter and the adc, so you have full control of everything.
is there a good simulation testbench for adc simulation available? thanks!
i agree...cadence should be sufficient.....for the adc which i designed i did use cadence... spectre simulation....and it was for 16-bit...
I'm looking for a behavioral verilog or vhdl model of an adc? Type of adc does not matter. Anyone can help?
Hi people, I request any question about adc with FPGA or PLD. How can I make adc with FPGA or PLD? Thanks all.