14 Threads found on edaboard.com: Adc Fpga Verilog
Hello everyone, right now i have the adc module (12-bits) which i convert it to BCD and then ASCII number since hyperterminal understand ASCII code. For UART TX module, i use the one in and it works but hyperterminal output multiple times like this . I believe some cont
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-26-2015 09:56 :: darklumi92 :: Replies: 1 :: Views: 1086
MICROchip adc IC.
You really don't want a solution do you? Post specific part numbers and links to datasheet you non-specific monkey! That gets you solutions faster.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-11-2014 13:27 :: mrflibble :: Replies: 4 :: Views: 2375
Hello All !!!!!
I am trying to implement FIR filter on fpga. I am not able make out how to go about it. I have calculated the coefficients and written a verilog code.There is 12 bit adc which will provide the input. I am thinking of converting the 12 bit input into decimal, then apply the filter equation, then convert the answer into binary (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-19-2013 15:50 :: embeddedaebi :: Replies: 0 :: Views: 655
Hi, I'm newbie for fpga. Actually I'm doing a project where i need to do combustible gas detector. I'm using combustible gas sensor and send the output to adc 0804 which will be interface with altera cyclone ii board. I have no idea how to do the verilog code. Anyone can help me
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-12-2013 09:40 :: yuva89 :: Replies: 1 :: Views: 1270
There wont be any different in serial interface and parallel interface of adc.
If you developed for one channel it can be repeated for 16 channel. Upto my knowledge there wont be any difference for each channel.
If it is yes please share the data sheet.
Things has to taken care while design adc interface are sample rate and sampling frequency and
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-28-2013 11:10 :: sureshaa :: Replies: 3 :: Views: 2140
i am in need of simple adc code in vhdl with analog input at port grater the bit better it will be
can anybody help me ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-17-2011 11:53 :: cheetha :: Replies: 8 :: Views: 2954
You can you adc0808, however you have to divide 50Mhz clock down to something which 0808 can handle.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-22-2010 20:43 :: Jack// ani :: Replies: 4 :: Views: 2110
hi lads and happy holidays
I am trying to implement a routine, basic code on a fpga with verilog.
this will simply perform some calculations, adc/math operands etc to alter the supply voltage.
I am doing this to simply have control over the power usage of the fpga.
also I would like to have an additional bus for (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-27-2009 23:13 :: toffee_pie :: Replies: 0 :: Views: 812
I've been learning the basics (very basic) of DSP and I wanted to try to implement things in verilog. Histograms DAC->adc etc. How does one go about doing this on an fpga? I have the Spartan 3E starter kit. Not an fpga built specifically for DSP, but should be enough to get something going.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-08-2009 16:34 :: laserbeak43 :: Replies: 0 :: Views: 724
Hello . Any one can provide example using verilog to interface 10 bit SAR adc parallel out to cpld/fpga and out put i2c data ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-19-2009 10:42 :: wls :: Replies: 0 :: Views: 1019
A verilog code is required to run an DC motor. the motor speed should be varied using potentiometer. I have an 8 bit adc for potetiometer. Please send me a verilog code for the same which can be synthesize in fpga(Sptran-3)..........
I hopemany of you has already done. Suitable assumption can be made for (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-08-2008 18:24 :: kum123ar :: Replies: 1 :: Views: 2584
I don't know VHDL (and little verilog for that matter...) but...
You could copy the incoming 8 bits (for example) into an array of registers, using a counter to increment the array index each time a sample is written in.
This worked for my adc problem although the interface might differ:
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-22-2008 18:08 :: Rob B :: Replies: 7 :: Views: 966
Hello . Anyone have sample of 14 bit digital error correction for pipeline adc verilog sample ? Can please share / example ? How is it calibration is considered and when is it needed ? I am new to pipelined adc ?
Analog Circuit Design :: 11-13-2007 06:40 :: wls :: Replies: 1 :: Views: 905
I request any question about adc with fpga or PLD.
How can I make adc with fpga or PLD?
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-22-2004 06:40 :: picus :: Replies: 3 :: Views: 2330