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237 Threads found on Adc Fpga
i want interface spi and i2c adc's with fpga spartan 3e board with this i have attached data sheets of adc's115854115855
According to datasheet, 10 MHz input clock (resulting in 10 MHz sample rate) is the minimal operation frequency. 5 MHz isn't guaranteed to work. I don't know what's the purpose of cdce62005, but presumed it outputs a clean, continuous clock, it shouldn't hurt. All other points are referring to hardware and fpga design questions. Firstly t
Problem: I have data sampled in an adc at 337.5 MHz(actually it is sampled at 1335 MHz,but for sake of DDR3RAM i am slowing down the rate at which data comes out,using 1:2 demux provided within adc) which needs to be written to a DDR3 RAM via a Virtex 7 fpga.(I am using Xilinx Vivado Design Suite) My progress: To writ
Hello everyone, right now i have the adc module (12-bits) which i convert it to BCD and then ASCII number since hyperterminal understand ASCII code. For UART TX module, i use the one in and it works but hyperterminal output multiple times like this . I believe some cont
I decide to use 4 250MSps adc interleave to 1000MSps and connected to Spartan 3 fpga for processing, so I wonder can spartan 3 internal block can withstand this 1 G Hz frequency ?
I need schematic diagram for pcb design of adc/DAC interface using THS1030 and THS5651, for interfacing with my cyclone iii fpga starter kit.
Here is a manufacturer- and distributor-independent adc selection table, from which you can select an appropriate adc, considering your required parameters.
I used the clock divider to set the clock of the adc (according to dataheet 4.8kHz) 4.8 kHz is the maximum sampling rate, not the clock frequency. The adc clock frequency is generated by a crystal on the module. You'll generate a SPI interface timing according to the datasheet specification. Maximum SCLK frequency is 5 MHz, 1 or 2
I am trying to build a basic thermometer with LM35 sensor and adc0804. I am also using basys2 fpga. The problem is the LSB of adc keeps blinking and i can't get a consistent reading. I tied the input of adc to ground and still the lsb blinks. Is there any way to correct it? Or how can i write the vhdl code for (...)
We are using fpga development board to get data from adc and this board has USB 3.0 interface in device mode. We need to establish a USB 3.0 communication link with SSD(Solid state drive) which is also in device mode. We therefore need USB 3.0 host controller which stores data coming from fpga board to SSD. What is the best way to (...)
1) Convert your analog signal to digital 2) Perform the FFT. The real and imaginary parts come from the FFT, not from adcs! 3) The resolution of the adc has ABSOLUTELY NOTHING to do with the FFT size.
Hi, everyone, Please help me in selecting a suitable fpga board for designing controller for my '12V-48V Bidirectional DC-DC converter', which one I should prefer 'Spartan 6' or Spartan 3E, or something else for my converter control. My requirements are- 1. Inbuilt adc and DAC, 2. High Speed 3. Easy to operate,
Hello, I am currently using a FLASHY D adc card from KNJN. I need to test the card, and to make it work with an fpga. But there are some problems when I acquire the signal. The period of the input signal is not the same as the output one. I don't Know the input circuit of the adc but I suspect that it is one of these [URL="http:/
Hi All! A am a newbie in Simulink & Matlab programming, but I need to implement QAM64 modem in fpga. The task is - do digital mixind I&Q channels in transmitter for sending it to DAC, then separate its in receiver after adc. I found the HDL optimized model
No. fpgas only have discrete inputs (ie. each pin is '1' or '0') You will need an external adc to input values to the fpga.
The LM 35 has an analog output therefore - you cannot interface it directly with an fpga. You'll have to use an adc to convert the output of the LM35 to a digital signal. Does your fpga kit have an adc onboard ?
I think there are no limitations in modelling the adc behaviour in a digital simulator like Modelsim. You'll input an "analog" stimulus (a real signal) and perform the quantization in your adc model. Although it's not the primary application of a digital simulator, you can even model the behaviour of an external analog circuit by describing it i
First of all, you'll either need an fpga with a built-in Analog-to-Digital converter (like a Xilinx Kintex, for example), or you'll need an external device. Pressure and temperature and such are relatively slow signals, so you won't need a very fast adc for those, but voice will require a faster device. You don't say anything about resolution: 8
i need to take 24 bit data from ads1271 ic , it need some control signals through fpga, while i trying to generate sync signal it depends on dout of ic. the output of ic is 24 bit data through dout. when data availble in dout it is high, then sync low(after 1 clk period it will high) as early as dout return to low, from that on wards for ever
It sounds simple but as soon as I check for adc_busy signal the adc_busy signal stops coming at it doesn't, the adc response is not changed by the fpga reading the busy signal output. Rest assured that the problem is with your code, not the adc. New logic works fine with simulation.Any synt
You can save a lot of design work by using an fpga kit with a high-speed interface (like multi channel LVDS) suitable for adc connection and make a sutable adc front-end board if you don't want to refer to an existing plug-in board.
For high sampling rate in Gs/s of scope passing data to fpga ,interpolation will be used , for a 8 bit adc , multiple and sum in sinc interpolation will result in 16 bit data . 255 pixel of lcd is representing 8 bit data,but after interpolation 16 bit is comes out , how to put this 16 bit into 8 bit "heights" ?
Hi All, We have a QPSK modulated signal 700 Mhz IF, 80Mhz BW to demodulate.The bit rate is 100 Mbit, roll-off is 0.65. Now we have to select an RF-adc,fpga board to demodulate it. The RF part can be handled by an I&Q demodulator circuit. Our question is; what should be the minimum sampling rate of the adc's? What should be their (...)
Hi daer all; I have a question that for an 8-bit adc for low-speed industrial applications what is the accepted minimum ENOB for interested bandwidth? I designed and implemented my Sigma-delta adc on fpga; but the ENOB for lower frequencies (20hz) starts from 6.4 and for highest frequency in the bandwidth (8khz) is 4.9 are these values
MICROchip adc IC. You really don't want a solution do you? Post specific part numbers and links to datasheet you non-specific monkey! That gets you solutions faster.
Hello, I am using Virtex-4 RocketIO MGT with 12 RX channels. It works at 6.4 GS/s. I am using MatLab to see the output of these different channels. At present the channels sometimes get synchronized after several reset or re-programming fpga or several read from RS232 port. adc is the input. I have redesigned the GT11_INIT_RX 'fsm' generated
Hello. I'm a beginner in VHDL and want to interface adc(ADS7800) with fpga virtex-5 can anyone help me in this.? regards.
Hi, I need vhdl code for interfacing on board 8 bit (0808) adc-DAC to fpga SPARTAN 2 pl. help me
I'm having trouble understanding how the use of wideband DDC in a real-world system results in lower data transfer requirements compared to just transferring the bulk adc samples. There is a well known Internet-based shortwave receiver with this design: 16-bit adc, 77.76 MHz sample clock, 8 fpga DDCs with decimation of 8 and 3/4, each (...)
Hi All, In our design, we have an adc which gives out differential parallel outputs.The adc operates at 3.3V. The differential output is interfaced to fpga, which operates at 2.5V. Is it necessary that both transmitter and receiver should be at the same voltage levels? Thanks & Regards, Naveen
Hi, I'm a newbie in fpga's and vhdl, we are using spartan-6 lx150t development kit, this board consists of one max7500(temperature sensor) adc with two wire i2c protocol. please anyone guide me to implement i2c interface between spartan 6 and the adc. any tutorial or links will be helpful. Thanks
Hello All !!!!! I am trying to implement FIR filter on fpga. I am not able make out how to go about it. I have calculated the coefficients and written a verilog code.There is 12 bit adc which will provide the input. I am thinking of converting the 12 bit input into decimal, then apply the filter equation, then convert the answer into binary again
Hello all, I want to realize delta-sigma adc using fpga, where digital processing (the cic filter) is implemented in fpga and only R and C are the analog parts. LVDS is used as comparator. The block diagram is below. 96110 The problem is that the adc ouput is not what I expect. - when voltage of inputs are belo
hello, i need a vhdl code for fifo memory to store binary values from a high speed 8 bit resolution adc. can help me give the code and the ucf file for implementing it on spartan 6 sp605( fpga kit).?? thank you you can automatically generate it with xilinx core generator (coregen) you can find it under :
Look at Cypress semiconductors PSoC controllers. It has some useful features. You can configure any pin to any port or any function just like a fpga. example you can configure any pin to a analog pin, UART pin, I2C pin, USB, etc...., It has build in & configurable adc/DAC. You don't need external OPAMP because it has buid in digital gain controled
Hi, I am making use of the PMOD AD1 (AD7476-12bit) for my application. I have used a FSM to interface the PMOD to the fpga. From the timing diagram from the data sheets available, the adc's poweron is dependent on the nCS signal. And I have a doubt that what would happen to the data converted (SDATA), if the nCS pin is pulled up even before
Hi Experts, I am using Virtex 4 ML403 Evaluation Platform fpga kit, on this kit a product of TI is used for audio data converting named LM4550. This IC work on the AC 97 CODEC which take serial data as an input and output. This IC work on different 16 bit registers to route data either through the adc to DAC or connect input to the output. A
Dear all Hi; I've implemented sigma delta adc on cyclonII DE1 fpga. the analog input is digitized at the multi-bit output now I want to evaluate the output by measuring the Signal to Noise Ratio (SNR) and ENOB and power spectrum but I dont know how to do that in practice? using which software or which device? and how to get the diagrams for S
Hello to everyone, I am very new to the world of fpga boards, and digital data converters, and that I deal with signal processing hardware. I am going to work with a TR4 development board produced by Terasic, such a board is mounting a Stratix IV fpga which is meeting my performance requests. Now the point is that I would like to connect an A
how to interface ir sensor to fpga through adc?
Hi Could any one introduce an evaluation board containing spartan 3 fpga,2 analog to digital converter (minimum: 12 bit/4 Msps) and gigabit ethernet connection? I have already found some boards and kits in xilinx site which have some of these features but not all of them. If you know any similar products from other suppliers please tell me.
I want to interface ICL 7135 adc with nexys 2 kit provided by digilent. How to do that?? it contains PMOD connectors. i think that might be helpful, i just want to know, where to connect my adc.
I suggest you dont use a usb camera. a USB interface is very difficult to implement on an fpga. An analogue camera connected to an adc would be easiest.
Hi, I'm newbie for fpga. Actually I'm doing a project where i need to do combustible gas detector. I'm using combustible gas sensor and send the output to adc 0804 which will be interface with altera cyclone ii board. I have no idea how to do the verilog code. Anyone can help me
So I am trying to create an I2C controller with a Nexys2 fpga to interface with an adc (digilent AD7991) I am trying to get accelerometer data from. This is my first attempt at this and I want to fully understand what is happening step by step so I created a VHDL design that does just that: Library IEEE; USE IEEE.STD_LOGIC_1164.ALL;
There wont be any different in serial interface and parallel interface of adc. If you developed for one channel it can be repeated for 16 channel. Upto my knowledge there wont be any difference for each channel. If it is yes please share the data sheet. Things has to taken care while design adc interface are sample rate and sampling frequency and
Hi, I am doing a project where I need to give some freuquency values from a signal generator into an adc and the output from this adc, after being passed through window and FFT are being shown in a LCD display on a vertex 5 fpga board. The problem is the LCD I currently have can only support 4-bit mode but my output is 5-bit mode. I (...)
PCB design: Cadence Allegro 15.2 / 15.7 / 16.2 / 16.5 Schematic design: fpga, DSP, MCU, etc. adc / DAC high-speed interfaces Hardware design using Xilinx and Altera fpgas. e-mail:
Hi all I am having trouble with my design where I have adc input coming to fpga and then processing thing are done... Then output goes through PCIe to computer. I cannot know how can I simulate adc signals with the fpga... Moreover how can I do the in-system simulation for debugging. since I do not have JTAG (...)
1) just a fancy way of implying that you can put your uP, fpga, adc in one package and it's programmable. 2) It has a hard ARM core inside that can boot independently from the fpga fabric. 3) You could treat it as either an extremely expensive ARM processor or as a rather pricey generic fpga. The tool chain is the same for (...)