373 Threads found on edaboard.com: Adc Fpga
How are you processing the output of the adc? fpga/DSP.
It seems like you using some processor. You need not map the values. You may just use some logical operations to convvert it into 2s complement. Some of them are suggested in previous responses. Check what is the reference voltage to the adc. This will determine whether the (...)
Microcontrollers :: 15.12.2003 02:11 :: brmadhukar :: Replies: 12 :: Views: 6927
I have used adc and ALTERA fpga ( ACEX1K) on my board.. but while selecting, u have to take care of these things...
anyways... u can use boost up converter... ( 5V to 3.3V) many companies are providing this ICs...like TI, intersil... search there... dont use resistors... its not a good practice..... and before selecting converter IC.. check curr
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.09.2004 02:47 :: jay_ec_engg :: Replies: 4 :: Views: 694
Are schematics of these board available, particularly the Xilinx implementation?
What company makes the adcs and DACs for Xilinx?
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.09.2003 13:50 :: Jayson :: Replies: 8 :: Views: 1432
The one thing I'd like to see is how to go one step beyond the Matlab Simulink (Xilinx System Generator), add control for an adc and actually do the DSP in hardware. Does anyone even know how to do this?
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.09.2003 22:06 :: Jayson :: Replies: 9 :: Views: 1472
The need for an PLD (fpga or CPLD) depends on some parameters IMHO.
Speed, databus width, pre-processing need, etc.
There are also adcs with a serial output (mostly used in audio range).
If you have a high speed adc (>100MSPS) you will have a lot of problems getting the data from that adc to the ?P or ?C. DSP alikes have (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.02.2004 05:23 :: lucbra :: Replies: 2 :: Views: 823
Im also interested in building a DSO.
I've found this site that uses adc+fpga+PC
The general idea is clear and has some VHDL code.
Analog input is not completely posted.
There is also another post in this forum with more info.
Hope this help!
Hobby Circuits and Small Projects Problems :: 13.04.2004 09:08 :: martingn :: Replies: 6 :: Views: 1234
What is the resolution required of the adc (and the DAC) and the bandwidth? Would it be possible to change the colors, constrast, etc of the image and quickly dump it back?
Does anyone know methods (or reference designs) of doing the opposite, i.e. RGB to NTSC through an fpga.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.04.2004 23:09 :: Jayson :: Replies: 16 :: Views: 4503
The jitter is very serious problem in the flash adc. Once, when i tried to create a 40MHz clock using Acex fpga, the jitter caused a high noise in the adc.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.04.2004 09:11 :: yev15 :: Replies: 8 :: Views: 1225
Considering a 200msps, 8 bit adc, full swing input signal at Niquist rate, you will have an error of 0,0512 LSB/ps of reference clock jitter.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.06.2004 05:22 :: pisoiu :: Replies: 2 :: Views: 1011
I even find tek TDS220 use national adc chip!
Professional Hardware and Electronics Design :: 20.06.2004 12:22 :: alphi :: Replies: 5 :: Views: 1333
general fpga have not implement dac or adc,some special fpga integrate dac or adc unit,so it can use it.
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.06.2004 20:50 :: alphi :: Replies: 12 :: Views: 6072
I request any question about adc with fpga or PLD.
How can I make adc with fpga or PLD?
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.07.2004 02:40 :: picus :: Replies: 3 :: Views: 1814
Some questions about your design:
1- What is the fpga clock frequency?
2- Do you have DAC/adc ICs on board?
3- What kind of RF stuff you have on your board?
I think that if you are not able to figure out the board's problem with all the tools you listed above then you should have some very rough mistake in your layout (assuming there are no
PCB Routing Schematic Layout software and Simulation :: 28.07.2004 22:40 :: nandopg :: Replies: 1 :: Views: 1044
The adc card consists of three parts:1. the analog input which is used to condition the input signal; 2.the adc convertor chip or device which do the function of analog to digital convert;3.the digital output which usually includes the DSP function for
digital signal preprocess.
Electronic Elementary Questions :: 12.08.2004 12:18 :: dewdrop :: Replies: 4 :: Views: 1424
Evreryone have their own pros and cons...
for matehmatical operation appliation/ signal processing... u can choose DSP and for high freq operation obviously fpga is better... and one more advantage of fpga is its cheaper....and interfacing with adc , DAC is also easier
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.09.2004 00:07 :: jay_ec_engg :: Replies: 3 :: Views: 1343
Hi Vacuum, (hehe that's funny)
The Xilinx Virtex-4 and Virtex-5 can input 1 gigabit/sec per differential input, so you may be able to connect your adc directly to the fpga. Inside the fpga, you could split the data into several parallel paths, and process them at a comfortable clock rate.
Why would you want to use 64-bit math if your (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.06.2007 23:15 :: echo47 :: Replies: 13 :: Views: 1563
I am working on an fpga based DSO project. I would like some input on the fpga/adc clock. The project utilizes 2 adcs capable of up to 250MSPS (Maxim 1121s) and I plan on using a Xilinx Spartan fpga. For acquisition there needs to be several timebases. These include: 10Mhz, 25Mhz, 50Mhz, 100Mhz, 125Mhz, (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.11.2004 09:39 :: Fish4Fun :: Replies: 4 :: Views: 1955
I thought the stages in SDR were:
1.Convert RF to IF.
3.DDC (look at redriver), LPF
4. IQ demodulation using CORDIC or some sort of LUT.
you should look at gnuradio that would give a more detailed description.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.05.2005 16:38 :: eziggurat :: Replies: 11 :: Views: 1724
I want to search for some demodulatin algorithms for burst FSK.
I had built a FSK transmitter and two FSK receivers to do burst data communication between two computer via wireless channel. The data rate is 9600kbps/19200kbps. One receiver is analog demodulator and using philips SA605 fsk demodulation chip, the other using adc/fpga to
RF, Microwave, Antennas and Optics :: 08.04.2005 10:00 :: ddt694 :: Replies: 3 :: Views: 2230
Just need an adc. For an fpga-only (no external analog to digital converter), with minimal external component, see Xilinx app note XAPP155
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.05.2005 10:05 :: Big Boy :: Replies: 3 :: Views: 1658
You are asking too generic of a question - interfacing to all of those depends on the type of adc/DAC etc. that you are using. ie: is it parallel, SPI, I2C... they will have different methods of interfacign.
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.06.2005 11:35 :: jdhar :: Replies: 4 :: Views: 1216
Please, I need help.
I wanna to simulate system on chip on simulink.
I wanna to build circuit like fpga to store output bit from adc on it then make FFT for it. So, Can any one help me to do that in simulink?
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.08.2005 20:58 :: nedalqasem :: Replies: 1 :: Views: 836
fpga's have many resources inbuilt such as memories, multipliers, busses even microprocessor, so while going for an ASIC for the same design we need to consider the above and use an appropriate library which contains a few of the above features(multiliers, adc, DAC etc).
please do refer this, may get some extra feature ideas
ASIC Design Methodologies and Tools (Digital) :: 25.10.2005 08:41 :: eeeraghu :: Replies: 5 :: Views: 1172
Hi, this is my first time connecting an external component to the fpga. The adc's output can be 5 v .. I'm using digilent spartan 3 board, where Vcco is connected to 3.3 V .. should I interface the adc to it direcrly since the fpga has internal clamp diodes ? or is it better to use a tranciever?
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.11.2005 10:28 :: cmos babe :: Replies: 1 :: Views: 1310
Does there exists fpga that have adc integrated into the chip.
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.01.2006 05:17 :: doofus32 :: Replies: 1 :: Views: 1032
FastDAACS USB Controller for QuickEval-II Evaluation Kits
ADIsimadc? Virtual Evaluation Board
Digital Data Capture and Analysis for Hi
Digital Signal Processing :: 31.01.2006 08:13 :: elsalvador :: Replies: 0 :: Views: 821
I have an fpga and a adc which uses LVDS signals. Will it matter if I cross the pairs of LVDS signals from the fpga to the adc (i.e. p->n and n->p) so that it is easier to route.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.02.2006 10:37 :: wossy :: Replies: 1 :: Views: 699
Are you kidding ?
An adc in an all digital fpga ?
Never heard of such an odd idea.
If you want an adc you may pick one of the new Actel Fusion fpgas. They have several adcs on board.
P.s. adc is an Analog to Digital converter, and you can attach any commercially (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.03.2006 14:30 :: yego :: Replies: 3 :: Views: 1042
You should look at the Atmel 2GSPS adc. It uses DMUX chip to split the samples into 4x500MSPS and also provide a 250 MHz clock that can be fed to a fpga and split it down it further using DDR registers.
Digital Signal Processing :: 26.04.2006 11:17 :: eziggurat :: Replies: 5 :: Views: 1606
I want to design a fir bandpass filter.
its parameter: fc1=2MHz,fc2=3MHz, fs1=1.6MHz,fs2=3.4MHz. As=-45dB.delta=0.5;
I design a hardware system that has adc--fpga--DAC.
can anyone give me its code?
Digital Signal Processing :: 13.04.2006 20:40 :: Jackwang :: Replies: 0 :: Views: 859
if the adc here is Anolog Digtial Converter, the first thing to design the interface is send a clock to adc.
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.04.2006 07:10 :: coolsniper :: Replies: 8 :: Views: 12127
Hi,Can you help me for something?
I want to use the fpga interface for the dual-slope A/D converter using TC7109CPL
my analog input is Sine Wave signal so...
How is design vhdl code to read the amplitute of sine signal? can you suggest me?
thank you a lot!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.07.2006 16:36 :: nansity :: Replies: 1 :: Views: 770
fpga has more logic and ram memories.
cpld if faster, but adc is not that fast even if it is high speed.
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.07.2006 16:42 :: EDALIST :: Replies: 2 :: Views: 1331
Hi , I have a system with an adc that recieves an analog signal that may have values in the 0 - 5 V range. The signal must be filtered in the digital domain. My question is how should the 8 bit samples be converted to match the format of the filter coefficients?
Digital Signal Processing :: 16.10.2006 04:40 :: cmos babe :: Replies: 12 :: Views: 1340
i am trying to make a music processing unit (e.g. - a basic guitar processor) on an spartan 3 fpga kit...
my first issue is the interfaces between the guitar and the kit and then the kit and the amplifier... what would be the speed and the resolution of the adc and DAC chips that i should be looking for??
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.11.2006 03:03 :: wiztronix :: Replies: 5 :: Views: 1721
For my school project we are building a PC digital oscilloscope with a bandwidth of 10mhz and I need help with the design.
I want to sample a signal injected into a adc and store the value in RAM. The thing is I don't want to lose any samples and you can't read and write to Ram at the same time(I don't think). Ok, so there are t
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.11.2006 21:00 :: fresh_easy :: Replies: 9 :: Views: 1095
i want to sample signals from the electric guitar and make i talk to a digital fpga board... what adc type and resolution would be a good choice?? also what is the best way to interface it..? any help would be greatly appreciated...
Digital Signal Processing :: 02.02.2007 05:59 :: wiztronix :: Replies: 9 :: Views: 787
I am using a pipeline 14-bit fast adc chip. The INL noise affects its performance. Is there any way to improve the adc or reduce the INL noise? I read about adc calibration. How to implement it efficiently? Anyone has the experience? Thanks.
Digital Signal Processing :: 05.02.2007 18:01 :: fpmd :: Replies: 4 :: Views: 810
You can use audio adc like UDA1361 (there are many chips like this) this chip has IIS digital output interface. It's very simple interface to realize in fpga. Characteristics are normalize in working area therefore to calculate signal value will be not hard ( voice level / dB level ).
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.02.2007 05:45 :: compvision :: Replies: 1 :: Views: 598
the data will be parallel.... (from adc)... actually we have resource of actel family thats why im specific about actel... can u pls suggest the best out of actel which suites this appln..
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.03.2007 03:45 :: bharathi_dasan :: Replies: 2 :: Views: 592
Could anyone help me to find out how to connect an adc(AD9860) to fpga.
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.04.2007 23:43 :: Winno :: Replies: 3 :: Views: 1590
I'm trying to use adc on the spartan 3e now, but I have some problems I couldn't solve. If you find some documents and codes about this subject could you give me?
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.05.2010 14:27 :: ytmm :: Replies: 2 :: Views: 2357
i need code vhdl code or verilog code for adc ans DAC please help me ..
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.09.2007 01:26 :: rajakash :: Replies: 3 :: Views: 3092
Want to know about fpga and adc interfacing?
Is this interfacing differs with the fpga vendor or any standard interfacing is there???
Thanx in advance.:D
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.09.2007 03:04 :: vikrant.eda :: Replies: 6 :: Views: 2048
About to undergo a little project and i was wandering if anyone could provide a few answers to my questions please.
I am going to use an fpga to control an adc to convert an audio signal and store the data into memory. Then i am going to use the fpga to control a DAC to convert the data stored in memory and output to a speaker. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.10.2007 08:29 :: andrew257 :: Replies: 6 :: Views: 3450
Try offsetting your adc input to +1.65V (one half of 3.3V) by installing a simple resistor voltage divider and a DC blocking capacitor. That should make your adc input happy. Beware, that technique may couple noise from the 3.3V line into the adc input.
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.11.2007 23:32 :: echo47 :: Replies: 4 :: Views: 587
1. Altera/Xilinx/ Lattice, also you wiull need video buffer to store your frame(s) fpga does not have enough internal memory use SDRAM chiaper and less pins
using LVDS check Altera web site for app notes
depends on fpga can serial can be paralle configuration
Also you will need adc for converting your video to digital form
Professional Hardware and Electronics Design :: 13.12.2007 12:58 :: Iouri :: Replies: 2 :: Views: 1613
hi ,iam working on Rf design,iam using fpga in the design,my freq range is 1.5-20 GHz,the outputs iam getting from adc to the fpga after down conversion,iam getting the wrong results for the range 1.5 to 2 Ghz.i cannot tell what is the expected result.
but my question is i observed the outputs after adc they were correct (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.12.2007 22:13 :: vinodkumar :: Replies: 3 :: Views: 529
I'm studying the WaveVision4 System, of which the Evaluation Board is using adc08D1500. Is it connected to Data Capture Board through Future Bus Connector (J4)? How to download data from adc Evaluation Board to Data Capture Board (fpga)?
Electronic Elementary Questions :: 01.01.2008 22:51 :: sally wang :: Replies: 0 :: Views: 314
There is a version of VHDL called VHDL AMS. It can be used for mixed signal design. Therefore adc can easily modeled by using VHDL AMS.
Analog IC Design and Layout :: 17.05.2008 03:05 :: electronics_sky :: Replies: 2 :: Views: 1837