1000 Threads found on edaboard.com: Adc Fpga
I have used adc and ALTERA fpga ( ACEX1K) on my board.. but while selecting, u have to take care of these things...
anyways... u can use boost up converter... ( 5V to 3.3V) many companies are providing this ICs...like TI, intersil... search there... dont use resistors... its not a good practice..... and before selecting converter IC.. check curr
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-13-2004 02:47 :: jay_ec_engg :: Replies: 4 :: Views: 770
How are you processing the output of the adc? fpga/DSP.
It seems like you using some processor. You need not map the values. You may just use some logical operations to convvert it into 2s complement. Some of them are suggested in previous responses. Check what is the reference voltage to the adc. This will determine whether the (...)
Microcontrollers :: 12-15-2003 02:11 :: brmadhukar :: Replies: 12 :: Views: 7613
We have a QPSK modulated signal 700 Mhz IF, 80Mhz BW to demodulate.The bit rate is 100 Mbit, roll-off is 0.65.
Now we have to select an RF-adc,fpga board to demodulate it.
The RF part can be handled by an I&Q demodulator circuit.
Our question is; what should be the minimum sampling rate of the adc's?
What should be their (...)
Digital Signal Processing :: 05-12-2014 10:54 :: kurtulmehtap :: Replies: 1 :: Views: 470
I m implementing fuel flow control unit based on fpga.i am using sensors,adc,fpga and stepper motor.i interfaced the stepper motor and now i want to interface temperature sensor (LM based on the temperature i am controlling sepper motr.Like it reaches max temp(80) then it has to reduse the temp by rotating motor anticlock p
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-06-2014 07:35 :: sharanabasappa j k :: Replies: 2 :: Views: 213
Im also interested in building a DSO.
I've found this site that uses adc+fpga+PC
The general idea is clear and has some VHDL code.
Analog input is not completely posted.
There is also another post in this forum with more info.
Hope this help!
Hobby Circuits and Small Projects Problems :: 04-13-2004 09:08 :: martingn :: Replies: 6 :: Views: 1299
I want to search for some demodulatin algorithms for burst FSK.
I had built a FSK transmitter and two FSK receivers to do burst data communication between two computer via wireless channel. The data rate is 9600kbps/19200kbps. One receiver is analog demodulator and using philips SA605 fsk demodulation chip, the other using adc/fpga to
RF, Microwave, Antennas and Optics :: 04-08-2005 10:00 :: ddt694 :: Replies: 3 :: Views: 2466
I want to design a fir bandpass filter.
its parameter: fc1=2MHz,fc2=3MHz, fs1=1.6MHz,fs2=3.4MHz. As=-45dB.delta=0.5;
I design a hardware system that has adc--fpga--DAC.
can anyone give me its code?
Digital Signal Processing :: 04-13-2006 20:40 :: Jackwang :: Replies: 0 :: Views: 952
I do not have any image in the file. It is just the sensor data I am getting from the adc/fpga combination.
Then it will not be a recognizable graphics format such as GIF, PICT, PNG, BMP, TIFF, etc.
You will need to learn how to create the image onscreen. You'll need to plot each pixel, draw each shape, etc.
Software Problems, Hints and Reviews :: 01-21-2014 00:41 :: BradtheRad :: Replies: 5 :: Views: 264
I need to know how to start designing a
digital AM receiver. I need a tool to help choose
proper device in chain due to receiver standard
parameters (Frequency, Sensitivity, Dynamic Range, ...).
I don't know how the structure must be and
don't know what devices and ICs may be used.
I have experience in digital and analog. I am
RF, Microwave, Antennas and Optics :: 10-24-2014 14:32 :: djnik1362 :: Replies: 2 :: Views: 344
I request any question about adc with fpga or PLD.
How can I make adc with fpga or PLD?
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-22-2004 02:40 :: picus :: Replies: 3 :: Views: 1931
I am working on an fpga based DSO project. I would like some input on the fpga/adc clock. The project utilizes 2 adcs capable of up to 250MSPS (Maxim 1121s) and I plan on using a Xilinx Spartan fpga. For acquisition there needs to be several timebases. These include: 10Mhz, 25Mhz, 50Mhz, 100Mhz, 125Mhz, (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-28-2004 09:39 :: Fish4Fun :: Replies: 4 :: Views: 2056
Hi, this is my first time connecting an external component to the fpga. The adc's output can be 5 v .. I'm using digilent spartan 3 board, where Vcco is connected to 3.3 V .. should I interface the adc to it direcrly since the fpga has internal clamp diodes ? or is it better to use a tranciever?
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-03-2005 10:28 :: cmos babe :: Replies: 1 :: Views: 1418
Does there exists fpga that have adc integrated into the chip.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-13-2006 05:17 :: doofus32 :: Replies: 1 :: Views: 1096
I have an fpga and a adc which uses LVDS signals. Will it matter if I cross the pairs of LVDS signals from the fpga to the adc (i.e. p->n and n->p) so that it is easier to route.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-09-2006 10:37 :: wossy :: Replies: 1 :: Views: 809
if the adc here is Anolog Digtial Converter, the first thing to design the interface is send a clock to adc.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-28-2006 07:10 :: coolsniper :: Replies: 8 :: Views: 12412
fpga has more logic and ram memories.
cpld if faster, but adc is not that fast even if it is high speed.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-20-2006 16:42 :: EDALIST :: Replies: 2 :: Views: 1424
use SPI interface of adc to connect with fpga for data read and write operation.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-26-2007 03:48 :: bansalr :: Replies: 3 :: Views: 1687
it depends on your adc you selected. because usally some pins of adc may have differential and some may be single ended. and also if u have to give a clock to adc from fpga then also the pins should be selected
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-20-2008 08:07 :: rajsrikanth :: Replies: 6 :: Views: 2179
1. any ram will be useful, but remember you need interface, if you use ddr, you'll need a ddr controller etc. the modules are available but that needs more space. Maybe you can use internal memory (some fpgas have it) but not to store 25 seconds of 24 bits sampled audio.
2. N?AudioSeconds*SampleRate*NumberBitsUsed (number used in memory to store
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-21-2007 09:08 :: drp :: Replies: 6 :: Views: 3684
I am interfacing adc with DE2 board. I am using adc 0809. My problem is that adc is giving output voltage as 5V for logic 1 and fpga as 3.3V as logic high. Will there is any problem in connecting it directly or should i use any other adc IC which gives o/p with 3.3V as logic high (compatible with (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-19-2008 02:44 :: atif.india :: Replies: 3 :: Views: 3440
I want VHDL code for interfacing adc (SP774BT) to fpga>>>
I have attached my datasheet
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-23-2009 04:37 :: hrushi53 :: Replies: 0 :: Views: 1147
I have an 12V analog signal that I want to convert to 1 bit digital and feed to an fpga.
(1) how do I make a 1 bit adc for an fpga
(2) How do i interface it to the fpga.
Any references would be helpful
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-18-2009 10:31 :: roddyalan :: Replies: 0 :: Views: 913
First of all you have to specity what you mean by high-speed, high speed in adc terms can be anything from 1MSPS to 1GSPS, then it all depends on what you want to do with the data after you captured them.
Any fpga is good for 1MSPS adcs but there no fpgas as I know who can support an adc at 1GSPS (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-16-2009 13:57 :: farhada :: Replies: 3 :: Views: 1976
can you tell me what is the adc interface(spi,i2c or parallel) and at what speeds you will be controlling it with the adc...because if the speed is more u might have to terminate the lines properly
Professional Hardware and Electronics Design :: 11-18-2009 11:27 :: barath_87 :: Replies: 1 :: Views: 1896
This is a straight forward adc. Just connect all the data lines to the fpga. Read the datasheet carefully. its an easy task only.
All the best
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-20-2009 23:20 :: sudhirkv :: Replies: 2 :: Views: 859
I have constructed the VHDL code for master(fpga) and slave (adc).
What are you trying to achieve? If you want to control the adc, you have to design a SPI master interface. A VHDL code for the slave would be needed only to simulate the slave's behaviour.
For the code, i found out some errors in master and slave(i think is t
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-12-2009 08:17 :: FvM :: Replies: 10 :: Views: 2192
Thats what I was expecting, glad you stated it explicitly!
Assuming you'll be targeting Xilinx devices.
It has what you call Delay Locked Loop(DLL), instead of PLL. To utilize DLL in your design you have to generate and instantiate HDL module in you design. Xilinx core generator will take parameter like multiplication/division factor to gene
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-21-2010 00:46 :: Jack// ani :: Replies: 5 :: Views: 820
Are you sure pls, that your Ev.-Board is problem less to control if you will drive it from normal 5V supplyed logical gates?
Is it not a missed GND wire or some similar in system?
Added after 21 minutes:
Sorry, what is exactly your input pls?
Signals from the 5V adc logic or you wish to drive the
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-04-2010 10:03 :: karesz :: Replies: 9 :: Views: 2347
i need adc core for Spartan 3E fpga kit.....
and how to connect it with MICRO BLAZE Processor???/
plz help me out...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-21-2010 03:18 :: kajulkumar :: Replies: 0 :: Views: 579
There are a couple of other things you will need to consider as well:
The front end adc will have a high speed parallel -ish interface (maybe even LVDS). The fpga will need to be able to handle these signals, route these to a buffer memory and psuhing it out.
Because you want to store 1Msamples (8bit), you will need 8Mbit of memory inside the
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-11-2010 03:55 :: lucbra :: Replies: 5 :: Views: 2416
I am trying to interface adc 0808 with spartan 3E fpga.can anyone please tell me how to do verilog program of this?.adc 0808 works at 450 KHz and fpga 50 i have to use different adc or i can do it with 0808.
thank you for your time and help
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-22-2010 15:42 :: longbeach2 :: Replies: 4 :: Views: 1597
I need vhdl code for interfacing on board 8 bit adc-DAC to fpga SPARTAN 2
pl. help me
Hobby Circuits and Small Projects Problems :: 10-27-2010 05:37 :: Anuja Diggikar :: Replies: 0 :: Views: 2682
You have to look at the data sheet of the adc used in your board for knowing the registers to be configured & timing to be followed. State machine based implementation for timing diagram & configuring registers in RTL has to be written.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-06-2011 23:29 :: ravics :: Replies: 4 :: Views: 1568
What adc are you using? how does it work? you have to read the datasheet and learn how the adc operates.
generally what you'll need to do is:
you will have to communicate with the adc, tell it what to do and get the converted data out of it..
1. set a bit of the adc to start conversion.
2. wait till the "done" (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-27-2011 10:37 :: keremcant :: Replies: 3 :: Views: 597
The adc is a high speed device which requires sophisticated layout technique. I'm under the impression, that the analog circuit design as well as the fpga interface implementation is far beyond your level of electronics knowledge. What's your point of measuring a 100 us time constant with a 6 Bit 400 MHz adc? You'll achieve much more exact (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-20-2011 06:33 :: FvM :: Replies: 17 :: Views: 1171
I am starting to research the market to buy a signal processing board for communications signals, including at least 1 adc (150Msps, 14bit), 1 DAC (200Msps, 14bit) and of course an fpga.
My purpose is to perform signal processing to signals with bandwidths of 40MHz maximum, and I am having a lot of trouble while choosing an fpga (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-09-2011 15:42 :: argam :: Replies: 1 :: Views: 660
I need help to design a receiver :
I use a AD7626 adc in "self-Clocked mode" (page 23 in datasheet : )
In this mode, the clock is not present, the data contain an header '010' which permit to the receiver to recover the clock. I'm a beginner in fpga design and I would
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-19-2011 07:55 :: houly :: Replies: 22 :: Views: 1592
Hi, thanks in advance
I want to implement a trained Neural Netw in fpga(Spartan 3E), I know it's not the first time but my question lies in hardware level.
you know to train a Neural netw I need some sample data Input,but the system after implementing is going to use the out put of adc of board as the neural network Input( :?: )
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-01-2012 06:09 :: Allahyarzadeh :: Replies: 0 :: Views: 605
Hi, thanks in advance
I asked this question in fpga forum but it seems hardware guys didn't know, maybe you software guys know it, or at least encountered such problem:
I want to implement a trained Neural Netw in fpga(Spartan 3E), I know it's not the first time but my question lies in hardware level.
you know to train a Neural netw I need s
Heuristic methods, Machine Learning, AI, and Soft Computing :: 03-02-2012 10:45 :: Allahyarzadeh :: Replies: 0 :: Views: 1256
I am trying to configure an adc using an fpga. I can read the default values from the adc register properly, but I'm unable to write to those registers.
The fpga clock is 48 MHz and serial clock for the adc is 8 MHz. The VHDL code that I've written is given below.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-13-2012 22:25 :: aroy :: Replies: 4 :: Views: 508
You didn't tell if BUSY_adc has a defined timing related to the fpga clock or not. If not, timing constraints don't help. Then the signal must be registered to the fpga clock domain before being evaluated in expressions like the shown one.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-04-2012 01:55 :: FvM :: Replies: 3 :: Views: 710
is it possible to implement an adc inside a fpga? if it is possible how much time and energy does it need?
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-13-2012 09:09 :: mahmoudathab :: Replies: 4 :: Views: 533
can anyone pls help me with a program for 'adc configuration for fpga':-(
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-06-2012 00:50 :: shalu mariya :: Replies: 0 :: Views: 261
I couldn't find any info about a board under the name of:
Please post a link to the board manufacturer's website or a datasheet for the 14 bit adc.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-04-2013 08:37 :: shaiko :: Replies: 4 :: Views: 434
There wont be any different in serial interface and parallel interface of adc.
If you developed for one channel it can be repeated for 16 channel. Upto my knowledge there wont be any difference for each channel.
If it is yes please share the data sheet.
Things has to taken care while design adc interface are sample rate and sampling frequency and
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-28-2013 06:10 :: sureshaa :: Replies: 3 :: Views: 945
Hello to everyone,
I am very new to the world of fpga boards, and digital data converters, and that I deal with signal processing hardware.
I am going to work with a TR4 development board produced by Terasic, such a board is mounting a Stratix IV fpga which is meeting my performance requests.
Now the point is that I would like to connect an A
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-13-2013 10:00 :: 8Strings :: Replies: 0 :: Views: 319
You mention "real" delta sigma adc.
I didn't yet. It would use an integrator front end with respective linearity.
I'm talking about possible modifications to the simplified SD frontend utilizing LVDS receivers. I have no idea if it gives noticeable improvements, just a suggestion to try out.
Digital Signal Processing :: 09-13-2013 07:29 :: FvM :: Replies: 10 :: Views: 865
Hi, I need vhdl code for interfacing on board 8 bit (0808) adc-DAC to fpga SPARTAN 2 pl. help me
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-19-2013 02:16 :: Er Ravi Pratap Singh :: Replies: 0 :: Views: 543
I'm a beginner in VHDL and want to interface adc(ADS7800) with fpga virtex-5
can anyone help me in this.?
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-01-2014 10:23 :: rohit bisht :: Replies: 2 :: Views: 768
The fpga and adc are communicating as follows :
fpga asserts convert_start for 14 us , adc sends adc_busy signal 60 ns after the rising edge of convert_start and adc_busy remains high for 3 us.
After that fpga reads data from the data lines.
In current (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-25-2014 09:56 :: verylsi :: Replies: 8 :: Views: 549