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245 Threads found on Adc Fpga
CCTV is an analog camera you need a video adc to interface with DSP or fpga.resolution depends on the camera you purchase,you could go thru the data sheet for the particular camera. Type of image format depends upon the video adc you select,you have RGB format,YCbCr format. Jpeg algorithm has to be done additionally using DSP or ARM9 (...)
It because the adc (MCP3008) outputs 10 bit value. Obviously, you didn't yet read the interface description in the datsheet. MCP3008 uses at least 17 clock cycles for input selection and data aquisition, with a standard SPI master, 24 clock cycles are used.
Discrete WT tree structure suits very well to digital computation. Signal or video (adc count row or pixel color row) doesn't matter. Once you have DWT coefficients you decide which way to compress (Run Length, ...).
The idea sounds good at first, but it will be problematic. Guitar pickups produce a weak signal. The amplitude is barely sufficient to feed to an adc. Therefore you still should expect to amplify it in the normal analog manner. After that, you can feed it to a microcontroller. The adc will turn it into digitized audio. You'll have to store each
118965118964118963 Respected All Readers and Electronics Experts, Hello and a Good Day to all of you. Its my 4th or 5th post on EDA Forum ever since I joined it. Fortunately, I always found excellent solutions to my queries, hence my experience here has been excellent and I hope for
Not sure waht you mean with "adc program". Building an adc requires specific analog hardware external to the fpga. Or are you dealing with a MAX10 device which exposes a built-in fpga? Regarding schematic entry, Quartus doesn't offer an option to convert HDL to schematics, except for the RTL netlist viewer which gives a (...)
I am working on DSP project in which i have to work with fpga(spartan 3 - xc3s5000) adn adc(ltc2255) , dac(ti-2904) . But i am facing a problem . The clock frequency of fpga is 40 Mhz and sampling frequency of adc is around 80 Mhz (it can not be changed ) . I am giving a clock pulse of 10 Mhz in dac (i can change the input (...)
Relating the apparently incorrect received adc output to LVDS signal quality isn't but an unsubstantiated guess, I think. There could be a lot of different design problems causing the shown picture, e.g. fpga timing issues. I understood so far that you have parallel adc data with 250 MS/s. The sampling window for the LVDS data shouldn't (...)
The solution is not completely obvious, there are different options: - Implementing a common data bus for all adcs, sequentially accessing the data Advantage: less fpga pins Disadvantage: more complex logic - Individual data lines for each adc Advantage: Simple logic, fast access without sequences. Some adc (...)
The DAC interface looks correct at first sight. In case that GPIO_1(31) is connected to adc OF output, it must not be driven but should be tristated. And there's no actual use of toogling the adc output enable. It's usually mentioned that a divided clock is bad design practice and a clock enable or PLL generated clock should be used instead. You
i want interface spi and i2c adc's with fpga spartan 3e board with this i have attached data sheets of adc's115854115855
Problem: I have data sampled in an adc at 337.5 MHz(actually it is sampled at 1335 MHz,but for sake of DDR3RAM i am slowing down the rate at which data comes out,using 1:2 demux provided within adc) which needs to be written to a DDR3 RAM via a Virtex 7 fpga.(I am using Xilinx Vivado Design Suite) My progress: To writ
Hello everyone, right now i have the adc module (12-bits) which i convert it to BCD and then ASCII number since hyperterminal understand ASCII code. For UART TX module, i use the one in and it works but hyperterminal output multiple times like this . I believe some cont
I decide to use 4 250MSps adc interleave to 1000MSps and connected to Spartan 3 fpga for processing, so I wonder can spartan 3 internal block can withstand this 1 G Hz frequency ?
I need schematic diagram for pcb design of adc/DAC interface using THS1030 and THS5651, for interfacing with my cyclone iii fpga starter kit.
Here is a manufacturer- and distributor-independent adc selection table, from which you can select an appropriate adc, considering your required parameters.
Hi everyone, I am just a beginner and i wish to interface an adc ( Pmod AD5) with an fpga (spartan 6). I am unable to come up with the correct VHDL codes. The datasheet to refer to is the AD7193. Can anyone help?? any help would be highly appreciated... Thanks :D
We are using fpga development board to get data from adc and this board has USB 3.0 interface in device mode. We need to establish a USB 3.0 communication link with SSD(Solid state drive) which is also in device mode. We therefore need USB 3.0 host controller which stores data coming from fpga board to SSD. What is the best way to (...)
1) Convert your analog signal to digital 2) Perform the FFT. The real and imaginary parts come from the FFT, not from adcs! 3) The resolution of the adc has ABSOLUTELY NOTHING to do with the FFT size.
Hi, everyone, Please help me in selecting a suitable fpga board for designing controller for my '12V-48V Bidirectional DC-DC converter', which one I should prefer 'Spartan 6' or Spartan 3E, or something else for my converter control. My requirements are- 1. Inbuilt adc and DAC, 2. High Speed 3. Easy to operate,
Hello, I am currently using a FLASHY D adc card from KNJN. I need to test the card, and to make it work with an fpga. But there are some problems when I acquire the signal. The period of the input signal is not the same as the output one. I don't Know the input circuit of the adc but I suspect that it is one of these [URL="http:/
Hi All! A am a newbie in Simulink & Matlab programming, but I need to implement QAM64 modem in fpga. The task is - do digital mixind I&Q channels in transmitter for sending it to DAC, then separate its in receiver after adc. I found the HDL optimized model
No. fpgas only have discrete inputs (ie. each pin is '1' or '0') You will need an external adc to input values to the fpga.
Hi sir, I m implementing fuel flow control unit based on fpga.i am using sensors,adc,fpga and stepper motor.i interfaced the stepper motor and now i want to interface temperature sensor (LM based on the temperature i am controlling sepper motr.Like it reaches max temp(80) then it has to reduse the temp by rotating motor anticlock p
I think there are no limitations in modelling the adc behaviour in a digital simulator like Modelsim. You'll input an "analog" stimulus (a real signal) and perform the quantization in your adc model. Although it's not the primary application of a digital simulator, you can even model the behaviour of an external analog circuit by describing it i
First of all, you'll either need an fpga with a built-in Analog-to-Digital converter (like a Xilinx Kintex, for example), or you'll need an external device. Pressure and temperature and such are relatively slow signals, so you won't need a very fast adc for those, but voice will require a faster device. You don't say anything about resolution: 8
i need to take 24 bit data from ads1271 ic , it need some control signals through fpga, while i trying to generate sync signal it depends on dout of ic. the output of ic is 24 bit data through dout. when data availble in dout it is high, then sync low(after 1 clk period it will high) as early as dout return to low, from that on wards for ever
Hello all, The fpga and adc are communicating as follows : fpga asserts convert_start for 14 us , adc sends adc_busy signal 60 ns after the rising edge of convert_start and adc_busy remains high for 3 us. After that fpga reads data from the data lines. In current (...)
You can save a lot of design work by using an fpga kit with a high-speed interface (like multi channel LVDS) suitable for adc connection and make a sutable adc front-end board if you don't want to refer to an existing plug-in board.
For high sampling rate in Gs/s of scope passing data to fpga ,interpolation will be used , for a 8 bit adc , multiple and sum in sinc interpolation will result in 16 bit data . 255 pixel of lcd is representing 8 bit data,but after interpolation 16 bit is comes out , how to put this 16 bit into 8 bit "heights" ?
Hi All, We have a QPSK modulated signal 700 Mhz IF, 80Mhz BW to demodulate.The bit rate is 100 Mbit, roll-off is 0.65. Now we have to select an RF-adc,fpga board to demodulate it. The RF part can be handled by an I&Q demodulator circuit. Our question is; what should be the minimum sampling rate of the adc's? What should be their (...)
Hi daer all; I have a question that for an 8-bit adc for low-speed industrial applications what is the accepted minimum ENOB for interested bandwidth? I designed and implemented my Sigma-delta adc on fpga; but the ENOB for lower frequencies (20hz) starts from 6.4 and for highest frequency in the bandwidth (8khz) is 4.9 are these values
hello. i am trying to operate by robot for specific application with fpga spartan-3.i need to interface adc with fpga. please anyone could share a verilog code for interfacing adc IC with fpga spartan-3.its urgent.
Hello, I am using Virtex-4 RocketIO MGT with 12 RX channels. It works at 6.4 GS/s. I am using MatLab to see the output of these different channels. At present the channels sometimes get synchronized after several reset or re-programming fpga or several read from RS232 port. adc is the input. I have redesigned the GT11_INIT_RX 'fsm' generated
Hello. I'm a beginner in VHDL and want to interface adc(ADS7800) with fpga virtex-5 can anyone help me in this.? regards.
Hi, I need vhdl code for interfacing on board 8 bit (0808) adc-DAC to fpga SPARTAN 2 pl. help me
I'm having trouble understanding how the use of wideband DDC in a real-world system results in lower data transfer requirements compared to just transferring the bulk adc samples. There is a well known Internet-based shortwave receiver with this design: 16-bit adc, 77.76 MHz sample clock, 8 fpga DDCs with decimation of 8 and 3/4, each (...)
Hi All, In our design, we have an adc which gives out differential parallel outputs.The adc operates at 3.3V. The differential output is interfaced to fpga, which operates at 2.5V. Is it necessary that both transmitter and receiver should be at the same voltage levels? Thanks & Regards, Naveen
Hi, I'm a newbie in fpga's and vhdl, we are using spartan-6 lx150t development kit, this board consists of one max7500(temperature sensor) adc with two wire i2c protocol. please anyone guide me to implement i2c interface between spartan 6 and the adc. any tutorial or links will be helpful. Thanks
Hello All !!!!! I am trying to implement FIR filter on fpga. I am not able make out how to go about it. I have calculated the coefficients and written a verilog code.There is 12 bit adc which will provide the input. I am thinking of converting the 12 bit input into decimal, then apply the filter equation, then convert the answer into binary again
Hello all, I want to realize delta-sigma adc using fpga, where digital processing (the cic filter) is implemented in fpga and only R and C are the analog parts. LVDS is used as comparator. The block diagram is below. 96110 The problem is that the adc ouput is not what I expect. - when voltage of inputs are belo
hello, i need a vhdl code for fifo memory to store binary values from a high speed 8 bit resolution adc. can help me give the code and the ucf file for implementing it on spartan 6 sp605( fpga kit).?? thank you you can automatically generate it with xilinx core generator (coregen) you can find it under :
Look at Cypress semiconductors PSoC controllers. It has some useful features. You can configure any pin to any port or any function just like a fpga. example you can configure any pin to a analog pin, UART pin, I2C pin, USB, etc...., It has build in & configurable adc/DAC. You don't need external OPAMP because it has buid in digital gain controled
Hi, I am making use of the PMOD AD1 (AD7476-12bit) for my application. I have used a FSM to interface the PMOD to the fpga. From the timing diagram from the data sheets available, the adc's poweron is dependent on the nCS signal. And I have a doubt that what would happen to the data converted (SDATA), if the nCS pin is pulled up even before
Hi Experts, I am using Virtex 4 ML403 Evaluation Platform fpga kit, on this kit a product of TI is used for audio data converting named LM4550. This IC work on the AC 97 CODEC which take serial data as an input and output. This IC work on different 16 bit registers to route data either through the adc to DAC or connect input to the output. A
Dear all Hi; I've implemented sigma delta adc on cyclonII DE1 fpga. the analog input is digitized at the multi-bit output now I want to evaluate the output by measuring the Signal to Noise Ratio (SNR) and ENOB and power spectrum but I dont know how to do that in practice? using which software or which device? and how to get the diagrams for S
Hello to everyone, I am very new to the world of fpga boards, and digital data converters, and that I deal with signal processing hardware. I am going to work with a TR4 development board produced by Terasic, such a board is mounting a Stratix IV fpga which is meeting my performance requests. Now the point is that I would like to connect an A
how to interface ir sensor to fpga through adc?
Hi Could any one introduce an evaluation board containing spartan 3 fpga,2 analog to digital converter (minimum: 12 bit/4 Msps) and gigabit ethernet connection? I have already found some boards and kits in xilinx site which have some of these features but not all of them. If you know any similar products from other suppliers please tell me.
I want to interface ICL 7135 adc with nexys 2 kit provided by digilent. How to do that?? it contains PMOD connectors. i think that might be helpful, i just want to know, where to connect my adc.