255 Threads found on edaboard.com: Adc Fpga
I need to work on creating a data acquisition IP for my custom adc module. I do not have much knowledge on data acquisition module Can any one help me not find out the features of DAQ module. My DAQ module is not going to be done any data processing.
I want to know what are the register should include in DAQ IP. ANd DAQ features
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-31-2017 08:18 :: viyaaloth :: Replies: 1 :: Views: 223
I am trying to build a scope based on a MCU with PC to display waveform. The MCU integrates adc, RAM and transmits captured and processed data to PC. The only thing I can think of to implement digital trigger inside MCU is that after each adc sample, the core will read it and calculate if it is a trigger condition.
I wonder if it is the right way?
Microcontrollers :: 03-12-2017 13:38 :: nickwang1982 :: Replies: 4 :: Views: 360
I need SS clock for fpga while adc should be clocked from reference clock (clock without SS, that I plan to use as reference of SS IC).
So I need modulated clock in phase with the reference one. (Of cause I extend input constrain for fpga, it is possible).
The feature required for me is called "timing-safe" in ON Semi documentation. (...)
Electromagnetic Design and Simulation :: 10-20-2016 18:23 :: _yes_ :: Replies: 6 :: Views: 386
i want to make oscilloscope
stm32 with cpld epm240 and ad9288@100mhz
i will use 320*240 lcd
the question is
i want to save and record adc buffer only
the epm240 have internal memory 8192 bit
can i use it in my project or it's rom not ram
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-16-2016 18:17 :: 5282 :: Replies: 7 :: Views: 575
i have 6 adc, i will connect them to fpga (spartan 6 kit) and comunicate with seriell and with SPI. I have never made pin connections of fpga before, i dont know if it is like Microcontroller.
i checked the pinout datasheet of the spartan 6 and, all the pins which is written MISO, CMPMISO are already connected to flash.
are they (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-03-2016 14:54 :: deniz88 :: Replies: 3 :: Views: 243
I am using quad spi to talk to an external adc device. I am unable to read data back from adc. quad spi IP is configured to master.
when I hook up my board to logic analyser, I do some read data but I am not able print it out or use it for any calculation. Also I see that data from adc on logic analyser is available as the same clock that (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-29-2016 07:57 :: twainerm :: Replies: 3 :: Views: 468
i am making an IGBT gate driver. Ground of the driver will have high voltage like 3000V and Vc of the driver will be 3015V.
there will be also fpga which will read datas such as Ig, Uce, Uge... from adc.
I am a bit confused how should be fpga part of the circuit,
should it also has 3000V ground? it doesnt sound good because (...)
Power Electronics :: 06-20-2016 22:35 :: deniz88 :: Replies: 2 :: Views: 321
I have a question about connect high frequency adc(same FMC160) to a fpga ,
Max clk frequency is 500MHz but adc frequency sapmling is 3.6GHz
how manage DATA of adc in fpga,
how read data in fpga?
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-26-2016 07:10 :: Mansoor1364 :: Replies: 2 :: Views: 284
When i change the adc Clock (Clock Divider from 4 MHz to 44.1 KHz ) i am unable to hear anything . Why is it so. The test bench shows that the adc clock is divided to 44.1 KHz but its not giving an on board output.
Suggests you start reading the adc datasheet. It's quite obvious that the adc clock input must be a multiple (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-05-2016 09:38 :: FvM :: Replies: 1 :: Views: 422
A good starting point would be to begin reading the adc section of the Starter Kit Board user guide that houses the Spartan 3E (e.g.- ug230.pdf).
After getting to know the resources you have on the Spartan 3E fpga dev. board and comparing it to your requirements you can decide to move forward.
I found the following thread at the Xilinx Forums
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-13-2016 09:55 :: dpaul :: Replies: 2 :: Views: 372
This thread from the Xilinx forums might help you:
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-10-2016 09:30 :: dpaul :: Replies: 2 :: Views: 447
It because the adc (MCP3008) outputs 10 bit value.
Obviously, you didn't yet read the interface description in the datsheet. MCP3008 uses at least 17 clock cycles for input selection and data aquisition, with a standard SPI master, 24 clock cycles are used.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-08-2015 18:05 :: FvM :: Replies: 58 :: Views: 2510
Discrete WT tree structure suits very well to digital computation. Signal or video (adc count row or pixel color row) doesn't matter. Once you have DWT coefficients you decide which way to compress (Run Length, ...).
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-20-2015 19:12 :: primozb :: Replies: 3 :: Views: 455
The idea sounds good at first, but it will be problematic.
Guitar pickups produce a weak signal. The amplitude is barely sufficient to feed to an adc. Therefore you still should expect to amplify it in the normal analog manner.
After that, you can feed it to a microcontroller. The adc will turn it into digitized audio. You'll have to store each
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-15-2015 06:26 :: BradtheRad :: Replies: 4 :: Views: 572
First, there are no adcs, at least that I'm aware of, that are current input; you'll need a current to voltage converter circuit. And since you're adding that converter circuit, you might as well put some filtering there.
Now,as to your original question, what resolution and speed do you need? THAT determines what a suitable adc would be. Are
Digital Signal Processing :: 07-06-2015 15:08 :: barry :: Replies: 26 :: Views: 2037
Not sure waht you mean with "adc program". Building an adc requires specific analog hardware external to the fpga. Or are you dealing with a MAX10 device which exposes a built-in fpga?
Regarding schematic entry, Quartus doesn't offer an option to convert HDL to schematics, except for the RTL netlist viewer which gives a (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-16-2015 05:41 :: FvM :: Replies: 2 :: Views: 508
Besides all considerations of reasonable signal processing design, there should be no problem to pass only 1 of N samples to the DAC. adc and DAC have both parallel interfaces and can be easily connected to the fpga.
Seeing no output could be e.g. caused by:
- Fault in adc or DAC interface design
- Datapath between (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-06-2015 08:30 :: FvM :: Replies: 1 :: Views: 523
Relating the apparently incorrect received adc output to LVDS signal quality isn't but an unsubstantiated guess, I think. There could be a lot of different design problems causing the shown picture, e.g. fpga timing issues.
I understood so far that you have parallel adc data with 250 MS/s. The sampling window for the LVDS data shouldn't (...)
Professional Hardware and Electronics Design :: 05-27-2015 12:44 :: FvM :: Replies: 8 :: Views: 931
The solution is not completely obvious, there are different options:
- Implementing a common data bus for all adcs, sequentially accessing the data
Advantage: less fpga pins
Disadvantage: more complex logic
- Individual data lines for each adc
Advantage: Simple logic, fast access without sequences. Some adc (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-21-2015 09:10 :: FvM :: Replies: 7 :: Views: 710
The DAC interface looks correct at first sight. In case that GPIO_1(31) is connected to adc OF output, it must not be driven but should be tristated. And there's no actual use of toogling the adc output enable.
It's usually mentioned that a divided clock is bad design practice and a clock enable or PLL generated clock should be used instead. You
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-04-2015 16:05 :: FvM :: Replies: 4 :: Views: 1677
i want interface spi and i2c adc's with fpga spartan 3e board with this i have attached data sheets of adc's115854115855
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-24-2015 08:50 :: Thirunavukkaras :: Replies: 7 :: Views: 717
Problem: I have data sampled in an adc at 337.5 MHz(actually it is sampled at 1335 MHz,but for sake of DDR3RAM i am slowing down the rate at which data comes out,using 1:2 demux provided within adc) which needs to be written to a DDR3 RAM via a Virtex 7 fpga.(I am using Xilinx Vivado Design Suite)
My progress: To writ
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-24-2015 04:04 :: rahdirs :: Replies: 10 :: Views: 1566
Hello everyone, right now i have the adc module (12-bits) which i convert it to BCD and then ASCII number since hyperterminal understand ASCII code. For UART TX module, i use the one in and it works but hyperterminal output multiple times like this . I believe some cont
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-26-2015 09:56 :: darklumi92 :: Replies: 1 :: Views: 1101
I decide to use 4 250MSps adc interleave to 1000MSps and connected to Spartan 3 fpga for processing, so I wonder can spartan 3 internal block can withstand this 1 G Hz frequency ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-08-2015 06:01 :: lgeorge123 :: Replies: 7 :: Views: 880
I need schematic diagram for pcb design of adc/DAC interface using THS1030 and THS5651, for interfacing with my cyclone iii fpga starter kit.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-26-2014 06:07 :: Varun Chitransh :: Replies: 1 :: Views: 702
Here is a manufacturer- and distributor-independent adc selection table, from which you can select an appropriate adc, considering your required parameters.
Analog Circuit Design :: 12-05-2014 14:21 :: erikl :: Replies: 1 :: Views: 668
I used the clock divider to set the clock of the adc (according to dataheet 4.8kHz)
4.8 kHz is the maximum sampling rate, not the clock frequency. The adc clock frequency is generated by a crystal on the module. You'll generate a SPI interface timing according to the datasheet specification. Maximum SCLK frequency is 5 MHz, 1 or 2
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-04-2014 06:35 :: FvM :: Replies: 7 :: Views: 1492
We are using fpga development board to get data from adc and this board has USB 3.0 interface in device mode. We need to establish a USB 3.0 communication link with SSD(Solid state drive) which is also in device mode. We therefore need USB 3.0 host controller which stores data coming from fpga board to SSD.
What is the best way to (...)
Microcontrollers :: 10-27-2014 13:32 :: moni_ :: Replies: 0 :: Views: 487
1) Convert your analog signal to digital
2) Perform the FFT. The real and imaginary parts come from the FFT, not from adcs!
3) The resolution of the adc has ABSOLUTELY NOTHING to do with the FFT size.
Digital Signal Processing :: 09-22-2014 15:15 :: barry :: Replies: 10 :: Views: 2067
If builtin adc/DAC is a requirement then by definition "something else".
Besides, you could check freescale for some decidedly non-fpga-but-useful ICs that can be used for this type of thing.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-18-2014 18:21 :: mrflibble :: Replies: 3 :: Views: 919
I am currently using a FLASHY D adc card from KNJN.
I need to test the card, and to make it work with an fpga.
But there are some problems when I acquire the signal.
The period of the input signal is not the same as the output one.
I don't Know the input circuit of the adc but I suspect that it is one
of these [URL="http:/
Analog Circuit Design :: 09-10-2014 13:49 :: DRO :: Replies: 0 :: Views: 334
A am a newbie in Simulink & Matlab programming, but I need to implement QAM64 modem in fpga.
The task is - do digital mixind I&Q channels in transmitter for sending it to DAC, then separate its in receiver after adc.
I found the HDL optimized model
Digital communication :: 09-02-2014 05:33 :: ipruzhinin :: Replies: 0 :: Views: 617
An analog-to-digital converter (adc, A/D, or A to D) is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-21-2014 15:28 :: FvM :: Replies: 11 :: Views: 738
The LM 35 has an analog output therefore - you cannot interface it directly with an fpga.
You'll have to use an adc to convert the output of the LM35 to a digital signal.
Does your fpga kit have an adc onboard ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-08-2014 12:21 :: shaiko :: Replies: 2 :: Views: 2101
I think there are no limitations in modelling the adc behaviour in a digital simulator like Modelsim. You'll input an "analog" stimulus (a real signal) and perform the quantization in your adc model.
Although it's not the primary application of a digital simulator, you can even model the behaviour of an external analog circuit by describing it i
Digital Signal Processing :: 07-24-2014 10:46 :: FvM :: Replies: 5 :: Views: 604
First of all, you'll either need an fpga with a built-in Analog-to-Digital converter (like a Xilinx Kintex, for example), or you'll need an external device. Pressure and temperature and such are relatively slow signals, so you won't need a very fast adc for those, but voice will require a faster device. You don't say anything about resolution: 8
Power Electronics :: 07-16-2014 16:23 :: barry :: Replies: 6 :: Views: 489
i need to take 24 bit data from ads1271 ic , it need some control signals through fpga, while i trying to generate sync signal it depends on dout of ic.
the output of ic is 24 bit data through dout.
when data availble in dout it is high, then sync low(after 1 clk period it will high) as early as dout return to low, from that on wards for ever
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-09-2014 05:50 :: surerdra :: Replies: 1 :: Views: 580
It sounds simple but as soon as I check for adc_busy signal the adc_busy signal stops coming at it doesn't, the adc response is not changed by the fpga reading the busy signal output. Rest assured that the problem is with your code, not the adc.
New logic works fine with simulation.Any synt
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-26-2014 01:37 :: K-J :: Replies: 8 :: Views: 1001
You can save a lot of design work by using an fpga kit with a high-speed interface (like multi channel LVDS) suitable for adc connection and make a sutable adc front-end board if you don't want to refer to an existing plug-in board.
Hobby Circuits and Small Projects Problems :: 06-23-2014 21:29 :: FvM :: Replies: 10 :: Views: 742
For high sampling rate in Gs/s of scope passing data to fpga ,interpolation will be used , for a 8 bit adc , multiple and sum in sinc interpolation will result in 16 bit data . 255 pixel of lcd is representing 8 bit data,but after interpolation 16 bit is comes out , how to put this 16 bit into 8 bit "heights" ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-20-2014 12:25 :: lgeorge123 :: Replies: 6 :: Views: 880
We have a QPSK modulated signal 700 Mhz IF, 80Mhz BW to demodulate.The bit rate is 100 Mbit, roll-off is 0.65.
Now we have to select an RF-adc,fpga board to demodulate it.
The RF part can be handled by an I&Q demodulator circuit.
Our question is; what should be the minimum sampling rate of the adc's?
What should be their (...)
Digital Signal Processing :: 05-12-2014 14:54 :: kurtulmehtap :: Replies: 1 :: Views: 779
Hi daer all;
I have a question that for an 8-bit adc for low-speed industrial applications what is the accepted minimum ENOB for interested bandwidth?
I designed and implemented my Sigma-delta adc on fpga; but the ENOB for lower frequencies (20hz) starts from 6.4 and for highest frequency in the bandwidth (8khz) is 4.9 are these values
Digital Signal Processing :: 04-16-2014 03:40 :: membership :: Replies: 0 :: Views: 408
MICROchip adc IC.
You really don't want a solution do you? Post specific part numbers and links to datasheet you non-specific monkey! That gets you solutions faster.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-11-2014 13:27 :: mrflibble :: Replies: 4 :: Views: 2424
I am using Virtex-4 RocketIO MGT with 12 RX channels. It works at 6.4 GS/s.
I am using MatLab to see the output of these different channels.
At present the channels sometimes get synchronized after several reset or re-programming fpga or several read from RS232 port. adc is the input.
I have redesigned the GT11_INIT_RX 'fsm' generated
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-02-2014 12:45 :: kaiserschmarren87 :: Replies: 6 :: Views: 660
I'm a beginner in VHDL and want to interface adc(ADS7800) with fpga virtex-5
can anyone help me in this.?
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-01-2014 15:23 :: rohit bisht :: Replies: 2 :: Views: 1952
Hi, I need vhdl code for interfacing on board 8 bit (0808) adc-DAC to fpga SPARTAN 2 pl. help me
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-19-2013 07:16 :: Er Ravi Pratap Singh :: Replies: 0 :: Views: 1486
I'm having trouble understanding how the use of wideband DDC in a real-world system results in lower data transfer requirements compared to just transferring the bulk adc samples.
There is a well known Internet-based shortwave receiver with this design: 16-bit adc, 77.76 MHz sample clock, 8 fpga DDCs with decimation of 8 and 3/4, each (...)
Digital Signal Processing :: 12-13-2013 20:42 :: nz_dsp :: Replies: 0 :: Views: 392
In our design, we have an adc which gives out differential parallel outputs.The adc operates at 3.3V. The differential output is interfaced to fpga, which operates at 2.5V.
Is it necessary that both transmitter and receiver should be at the same voltage levels?
Thanks & Regards,
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-11-2013 06:49 :: snaku :: Replies: 1 :: Views: 431
I'm a newbie in fpga's and vhdl, we are using spartan-6 lx150t development kit, this board consists of one max7500(temperature sensor) adc with two wire i2c protocol. please anyone guide me to implement i2c interface between spartan 6 and the adc. any tutorial or links will be helpful.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-21-2013 06:14 :: rg.naveen :: Replies: 1 :: Views: 934
Hello All !!!!!
I am trying to implement FIR filter on fpga. I am not able make out how to go about it. I have calculated the coefficients and written a verilog code.There is 12 bit adc which will provide the input. I am thinking of converting the 12 bit input into decimal, then apply the filter equation, then convert the answer into binary again
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-19-2013 15:50 :: embeddedaebi :: Replies: 0 :: Views: 659