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Adc Noise Simulation

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23 Threads found on edaboard.com: Adc Noise Simulation
I am building sigma Delta adc, i want to include the effect of thermal noise in the sustem.. Is there any way to include noise source to represent resistors' thermal noise ?? a random source generator or something ?
Hi all, I am trying to simulate an adc on verilog-A, using MOSFET models generated from TCAD tools. In order to quantify adc performance in terms of SNR etc. I need to include noise in my simulations too. Can someone help to identify where I can include noise sources in the simulation (...)
I'm trying to simulate SNR for my circuit which is not related to adc, DAC or Sample-hold. Can I use DFT to simulate SNR which seems a popular method to do for adc and DAC? Does the DFT give correct signal and noise information at frequency bin of interest? Thank you,
hi all, i have design a sigma delta adc. the fft results of both "matlab" and "veriloga" and "veriloga_sw & mos_amp" is fine. if the veriloga sw be changed to cmos-sw, the dc noise peak arise, & independent of fft point number. the 1/R_sw/C_s ~= 6*(2*pi*f_sample). my english is very poor, thanks for your help!! Add
You are right, it will take quite a long time, but even one run might give you an idea of your DNL/INL. The SFDR is very closely related to the INL of the adc, so you do not really have to have a DNL/INL plot. Moreover, a simulated DNL/INL does not make very much sense. The papers you refer to - I bet - have measured DNL/INL. About the noise,
Hi, Can any one help in doing in noise simulation of SC integrator - part of a incremental sigma-delta adc? Any good reference or simulation type details will help a lot. Thanks Sanku
in pipelined adc,such as 1.5-bit-per-stage,if there is no front end S/H,then the main source of thermal noise is the KTC noise;in simulink behavioral simulation,in order to take KTC noise into consideration,we can add a noise submodel into the ideal model of every stage,just as the below (...)
Hello, I want simulate my first first order delta sigma adc, attached schematic. I can simulate it and I see behind the LP again my input signal. My problem is I cant see the noise shift to higher frequency. I simulate transient and adjust transient noise (noisefmin noisefmax and (...)
The SNR that I had received while calculating in Matlab for a specific NTF is around 80 dB. I realised the same using ideal op amps and the SNR was the same. But the SNR after using nonideal op amps went down to 40 dB. What can be the reasons for the degradation? Added after 17 minutes: and also suggest wh
I am running into a problem when I was trying to simulate my DSadc in spectre. The entire system is using ideal components (no transistors, but there are VCVS, R, C) and Verilog models. When I was doing transient sim using "Liberal" setting, for about 60us, it was running fine and giving correct output (noise shaping and all that) but then at about
I am running into a problem when I was trying to simulate my DSadc in spectre. The entire system is using ideal components (no transistors, but there are VCVS, R, C) and Verilog models. When I was doing transient sim using "Liberal" setting, for about 60us, it was running fine and giving correct output (noise shaping and all that) but then at about
i have designed a pipeline adc(10bits 1.5bit per stage)in simulink, but there are many problems: the ideal behavior is normally well,but when i take noise(kT/c) and transfer function (the gain of mdac 2p1/s+p1, p1 is the dominant pole) into account, it doesn't work well. first,the value of Nrecord is very
It's hard to include random noise in SPICE simulation. But you can try verilog-a/ams for evaluating their impact on adc performance.
HI all i am simulation a pipeline adc. I give a sine input, and do .tran simulation in hspice. Then catch the 10-bit digital code to do fft in matlab. Then i want to know, the fft results can give the SNR results? And is the noise compont included in the tran simulation results? What (...)
Some literature will state their T/H circuits are designed for 8-bit linearity. Which simulation they run and which spec they judge whether it is 8-bit linearity? In my opinion, since T/H circuit input and output are all analog circuits. No INL/DNL spec can be put there. Are they measuring SDR and compare it with SNR requirement of certain No.
Hi Everyone, I have just designed a 8-bit folding interpolation adc. When I simulate my adc, I cannot get to 8-bit of resolution. The SNR that I got from the power spectrum is only -30dB. The noise level is at -40dB. Is there any technique I can use to lower the noise level in the adc. Can anyone who has (...)
in simulation, I do FFT of an adc's output, according to this result, it is easy to get SFDR, but how can I get SNR, THD and SNDR? thank you very much!
jswei303, You are talking about measurement or simulation results ? Because if it is measurements, what you see can be caused the noise - even if you put a perfect DC voltage at the input of an adc, you'll see different codes coming out, from sample to sample.
Hi, all I have designed a 3 order sigma delta SDM. after the chip come back. the second order harmolic distortion is -70db, and the noise floor is about -100db, How can I to reduce the second order harmolic distortion. Best regards Crossbow
Some of the most important specs for S/H in pipeline adc include SNR and THD. You can simulate these parameters in HSPICE, without using spectreRF features. To do this, you need to calculate the kT/C noise and OTA noise contribution carefully due to inherent alias. Other than this, the THD performance can be simply measured by perform FFT on (...)
We design chip in which input signal is chopped at 4Khz. After amplification this signal is manipulated in adc with sampling frequncy 1MHz. I have simulation results ( on PSpice) for the noise at 4KHz and 1MHz. My question is: Is there any rule to calculate (on the base of the noise at both frequncyies), the real (...)
Is it possible to simulated DNL and INL for a 10-12bit adc? From what i know, to obtain DNL and INL, there is the back-to-back of adc and DAC method and the histogram method. However, these method are normally for adcs that are already fabricated and it will take years to do the simulation (or am i wrong?) as we need a (...)
if we design a adc or pll or opamp, is the noise analysis essential?