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32 Threads found on edaboard.com: **Adc Snr Fft**

Hi, I have designed an **adc** in cadence virtuoso and i want to calculate the metrics such as **snr**,SINAD,ENOB etc. For example i want to calculate ENOB. I read everywhere that i need to do an **fft** my input, or simply use the spectrumMeas function. So i am using a sinuid input of 875MHz as fin and 2GHz as flck. In the field in spectrumMeas i use (...)

Analog Circuit Design :: 10-27-2016 04:27 :: Pavlanto :: Replies: **0** :: Views: **549**

hello
i was simulating of a first order **adc** using code given in book of richard scherier. for calculating **snr** he uses (page 265)
**snr** = calculate**snr**(spec(1:ceil(N**fft**/(2*OSR))+1), tone_bin)...
where spec is spec = **fft**(v.*ds_hann(N**fft**))/(N**fft***(nLev-1)/4); (...)

Digital Signal Processing :: 12-05-2014 06:05 :: sona_ :: Replies: **1** :: Views: **906**

Are there materials about the detail **fft** analysis of **adc**, such as how to determine the source of HD2, HD3 or higher HD?
May be this treatise can be helpful?

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-27-2013 14:49 :: erikl :: Replies: **7** :: Views: **1369**

hello Eminent.Engineer,
I hve also designed a delta sigma **adc** and i calculate the **snr** order to caculate the **snr** after the modulator you must make the fast fourier transform function (**fft**) by MATLAB after the modulator.
About the decimation,until now i have designed the complete **adc** in Smulink (MATLAB) (...)

Digital Signal Processing :: 04-01-2013 16:48 :: fasto2008 :: Replies: **4** :: Views: **2442**

method 2 is one i have used before. i set the dac to have 2 bits mode resolution than **adc**.

Analog Circuit Design :: 12-26-2011 08:27 :: steadymind :: Replies: **1** :: Views: **603**

hi folks.
i am trying to test the 10 bit pipelined **adc** schematic i designed. The procedure i am following for finding the SNDR is " take a sinusoidal input signal nearer to full scale range.Using an ideal DAC reconstruct the signal. Plot its **fft** ,say for 1024 points,take those values and find SNDR, THD, SFDR , **snr** from matlab by giving (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-14-2011 05:36 :: chandra3789 :: Replies: **1** :: Views: **1042**

hi, all,
i design a **adc**, and now it is tested, but i have no any software to get **snr** and THD+N THD..., but some digital data is sampled from a logic analysis device, and a piece of MATLAB procedure is need to get **snr**, THD+N, THD and the **fft** figure, but i can't compile the procedue.
can you upload the procedure the (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-24-2011 12:38 :: huangjw :: Replies: **0** :: Views: **911**

hiiiiiiii
I'm working on sigma Delta **adc**
CAN ANY1 PLEASE HELP ME ON WORKING WITH CADENCE SPECTRE FOR **snr** CALCULATION
HOW MANY CYCLES I SHOULD RUN THE TRANSIENT ANALYSIS??
IN ORDER TO CALCULATE **snr**
PLEASE HELP ME IN FIGURING OUT THESE VALUES...
how to come to conclusion to **fft** fundamental frequency of input (...)

Analog Circuit Design :: 02-07-2011 17:06 :: kapil411 :: Replies: **3** :: Views: **4048**

I remember calculating SFDR for 100 Mhz **adc**. I see if I can find the C code for it and extrapolate equation and post it here. That might help you on the **snr**.

Digital Signal Processing :: 09-05-2010 02:15 :: eziggurat :: Replies: **3** :: Views: **3448**

I have tried to estimate the **snr** of the sigma delta conversion after the sinc^3 filter and got lots of noise at the low frequency end. It looks like the opposite of noise shaping, see attached. When **fft** of the bitstream is plot the **snr** is almost twice as high for the same frequency. Am I using the sampling rate a lot higher than the signal I (...)

Analog Circuit Design :: 04-19-2010 21:45 :: ElEngineer :: Replies: **1** :: Views: **1950**

Dear All,
In N-**adc**s why we need to follow coherent sampling method for calculating **snr**.
Bye.

Analog Circuit Design :: 11-01-2009 14:19 :: coolstuff07 :: Replies: **2** :: Views: **1738**

Hi guys,
I am currently designing a column parallel single slope **adc** for a CMOS image sensor.
I have done the DC, AC and Transient analysis. I am aware that I need to do .**fft** to determine the **snr** and ENOB.
Are there any other simulations that I may have missed? Appreciate all the help I can get. Thank you all!
hyuuga_patik

Analog Circuit Design :: 07-16-2009 02:15 :: hyuugapatik :: Replies: **2** :: Views: **1471**

ideal **adc** + actual DAC
the input signal is sine wave
then **fft** the output signal of the DAC

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-07-2009 08:10 :: lwjbh :: Replies: **2** :: Views: **1665**

Hi all
I use the HSPICE to simulate the whole pipeline **adc**.
I want to check its **snr**. So i run the tran. simulation with 2048 points, then transfer the .tr0 file to matlab to **fft** to get the **snr** value.
If i use 0.01ns transient step in tran simulation, the **fft** results is about more 60db (My (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-23-2008 04:28 :: gdhp :: Replies: **3** :: Views: **1593**

HI...
I AM PRASADH, I AM DOING MY PROJECT ON FLASH **adc** IN CADENCE..
HOW CAN I DO THE **fft** ANALYSIS IN CADENCE SPECTRE FOR MY CIRCUIT..
ACTUALLY I HAVE TO MEASUER SFDR,SNDR FOR MY CIRCUIT .
CAN ANYONE HELP ME PLEASE....
THANK YOU

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-07-2008 09:53 :: prasadel06 :: Replies: **5** :: Views: **2182**

Hi, I have some question regarding the script I got. Part of it is as follows:
.
.
.
% Create the minimum, 4-term Blackman-Harris window for **fft**
pwr_win=0;
for i=1:Nt %where Nt is the no. of **fft** bins
window(1,i)=0.35875-0.48829*cos(2*pi*(i-1)/Nt)+0.14128*cos(4*pi*(i-1)/Nt)-0.01168*cos(6*pi*(i-1)/Nt);
p

Analog Circuit Design :: 03-18-2008 01:19 :: pseudockb :: Replies: **0** :: Views: **1609**

HI all
i am simulation a pipeline **adc**. I give a sine input, and do .tran simulation in hspice.
Then catch the 10-bit digital code to do **fft** in matlab.
Then i want to know, the **fft** results can give the **snr** results? And is the noise compont
included in the tran simulation results?
What performance of (...)

Analog Circuit Design :: 01-09-2008 03:24 :: gdhp :: Replies: **3** :: Views: **3312**

hi ,
i have implemented an flash **adc** in .35u process.......i want to check its dynamic specification..........please tell me in detail how to perform the test........(**snr**,sfdr)
i have designed a new rom and want to cehck the error rate..........plzsz help me out in this

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-08-2007 05:06 :: niket_jmd :: Replies: **5** :: Views: **1179**

for calculating the SFDR for an **adc** .
coudl u please tell me the origin of this spurious signal ..
in **adc**

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-03-2007 08:23 :: manissri :: Replies: **1** :: Views: **1075**

Hi, I am working on sigma delta modulator based **adc**.
I have output bitstream from the modulator and would like to measure **snr** and SNDR using **fft**.
How could I possibly separate the signal and noise from the output of modulator?
Also, is there anyway to separate the noise and distortion from the total noise from the modulator output (...)

Digital Signal Processing :: 07-26-2007 21:41 :: sehun1119 :: Replies: **3** :: Views: **1553**

Hi Everyone,
I have just designed a 8-bit folding interpolation **adc**. When I simulate my **adc**, I cannot get to 8-bit of resolution. The **snr** that I got from the power spectrum is only -30dB. The noise level is at -40dB. Is there any technique I can use to lower the noise level in the **adc**. Can anyone who has experience with (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-02-2007 13:09 :: chemaphy :: Replies: **4** :: Views: **1204**

in simulation, I do **fft** of an **adc**'s output,
according to this result, it is easy to get SFDR, but how can I get **snr**, THD and SNDR?
thank you very much!

Analog Circuit Design :: 06-07-2007 05:21 :: qqic :: Replies: **1** :: Views: **1631**

Hey, why do you want to measure the INL and DNL of a sigma delta **adc**? I am sure that you are not resolving any bits in analog domain. So, I have rarely heard about anyone talking of INL and DNL for a Sigma Delta **adc**.

Analog Circuit Design :: 01-29-2007 22:25 :: Vamsi Mocherla :: Replies: **5** :: Views: **1503**

hi! all~
i want to ask the questions about the pipelined **adc**'s **fft** calcculate for
**snr** SNDR
i try to see many papers,but never see the detail calculate way,
just only see some like that:
(1) SNDR=power of signal/(noise + distortion) or
SNDR=signal(db)-noise(db)-distortion(db)
(2) SFDR=power of signal/(max distortion)
(3) (...)

Analog Circuit Design :: 11-03-2006 07:07 :: kklljim :: Replies: **0** :: Views: **1135**

Some of the most important specs for S/H in pipeline **adc** include **snr** and THD. You can simulate these parameters in HSPICE, without using spectreRF features. To do this, you need to calculate the kT/C noise and OTA noise contribution carefully due to inherent alias. Other than this, the THD performance can be simply measured by perform **fft** on (...)

Analog Circuit Design :: 09-15-2005 23:03 :: willyboy19 :: Replies: **13** :: Views: **2867**

Hi, all,
how to calculate the **snr** and SNDR of the bit stream (1-bit stream) of sigma-delta modulator, and the **snr** and SNDR of the output data of the all **adc**. need your helps. Thanks in advance.
regards,

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-01-2006 06:49 :: wonbef :: Replies: **4** :: Views: **2373**

Understand the defination of DNL/INL then you can begin to simulate it. Do you know how to evaluate the DNL/INL of an actual **adc**?
**snr** is calculated after **fft** analyse using Hspice.
Dear All,
How to simulate INL , DNL , **snr** by Hspice . When I do Histogram analysis,it needs many cycle. If I design 12Bits (...)

Analog Circuit Design :: 05-09-2006 10:08 :: philipwang :: Replies: **4** :: Views: **1001**

Hi all,
I am design a 10bits pipeline **adc** and by followingprevious articles I use Matlab to do **fft**. But here are the problems I met.
fin=100Khz, fs=10Mhz,
N=8192(number of data points in **fft**),
M=83 (integer number of cycles within the sampling window),
First I used coherent sampling method to do **fft** and I got a (...)

Analog Circuit Design :: 01-17-2006 09:17 :: yushen_yang :: Replies: **1** :: Views: **1431**

i don't know there is really any option or not which can extact ur waveform into a text form or any other form. because i am also trying it with cadence simulator( cadence also uses spice to generate the netlist).
But u can get the value manually and put the value in matlab to get the **snr** of **adc**.

Analog Circuit Design :: 09-06-2005 13:44 :: surajit :: Replies: **5** :: Views: **1292**

You can use the sandwork to read the HSPICE simulation result and use the **adc** analyzer in sandwork to do those measurement.

Analog Circuit Design :: 08-17-2005 00:41 :: eda_heat :: Replies: **9** :: Views: **3399**

How can I measure **snr** from sigma delta **adc** and decimation after that but not to predict the **snr** ?
In frequency domain low pass filter has perfect magnitude spectrum but I can't get the perfect mmse **snr**?I have already considered the delay on it.
If anyone has opoins plz tell me,thx.

Digital Signal Processing :: 12-26-2004 06:54 :: boeysue :: Replies: **7** :: Views: **3679**

hello!!
Somebody can tell me !! How to calculate SNDR of **adc**??
How to find Matlab program that to analysis dynmic parameter of A/D Converter ??
thanks !!!

Analog Circuit Design :: 09-03-2004 06:11 :: chrischen :: Replies: **3** :: Views: **4030**

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