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48 Threads found on edaboard.com: Ads Verilog
I have an equation that describes the linearity of my amplifier. and I want to make a plot based on the equation. How could I do that in ads? this the equation I have vo=a1+a2vi+a3vi^2, and I want to plot vo vs is very easy. Use SDD(Symbolically Define Device) or verilog-A. edadocs.softwa
Hello, How do I transfer a va file into ads? I want to transfer a tunnel fet verilog a file into ads.
What does PSO stand for (maybe it is Phenomenally Silly Obfuscating...acronym?) I'm going to guess Particle Swarm Optimization. It's a Computer Science concept. The 'swarm' and 'iter' (iteration) lean that way. There are some things better left to processors.
Naw, I think the new engineering education system pushes for how to get your answers from edaboard, hence the desperate pleas of need this ASAP being sent from their phone during their interview ;-)
sorry about the confusion the diagram is the correct description, I switched between signal1 and signal2 in the description. - - - Updated - - - sample the signal (after synchronizing it to the clock) and perform a falling edge detection using a FF to delay the signal (after the synchr
I am doing this with a SDD2P component at the moment which means that the resistor element I was looking for is a current source which is not quite the same.It's very easy. Attached example is a voltage controled resistor where R=Roff for VcVon [QUOTE=jadema
There seems to be quite a few older thesis papers on this subject, have you read any of them? They might give you some insight into the OFDM implementation, though I'm sure the actual HDL details will be missing. Thank you for your helpful response may i have some of them?
Modelsim reports multiple drivers with an X not U. No it doesnt. 'U' driven with anything results in 'U'
Remove any verilog beyond 2001 and/or VHDL beyond 1993 (or maybe 2002) and try compiling the file again. Or switch to Altera, Quartus-II support for more recent versions of the language standards is much better than Xilinx. Vivado 2015 has better 2008 support than Quartus!
Thanks ads we for the reply.. But my plan is to read a certain database Using UART In fpga... That is to interface with the HDD... So please suggest the possible solution for this.,..
I want to know if I can use Blocking assignment = instead of <= above - shouldn't that be better? Apart from the problem explained by ads-ee. why do you think the blocking variant should be better? It replaces the regular CIC integrator part by a different circuit. It reduces the propagation delay by two clock cycles at cost of maxi
I will let you in a secret: 9 out of 10 papers generate vacuum when it comes to implementation details. So, no you should in fact not use floating point like the paper says. You should use fixed point like ads-ee who has a clue says. ;-) Or even better yet, you yourself should do some calculations and work out your error budget so that you know
From the LRM IEEE Std 1800-2012 11.4.5 Equality operators: 114821 which means the result is always false as the compare fails. The equality operator you want to use is === or !===: 114822 More importantly this type of code is NOT synthesizable, if this is used only in a testb
Hello all! I tried to learn how to add a verilog-A model into ads. I had two different models and followed the same procedure in ads. For some reason non of the projects worked, and they gave me different error messages. I attached my projects to this message. I would appreciate if someone could tell me what I did wrong. Best (...)
Also I'm not sure how you compiled this code in Quartus. You are comparing a 5-bit constant with a 4-bit count value, that should throw an error in synthesis. VHDL (unlike verilog) doesn't allow shenanigans like this. signal count: STD_LOGIC_VECTOR(3 downto 0); constant SEC6: STD_LOGIC_VECTOR(4 downto 0) := "110
Systemverilog DPI (Direct Programming Interface) is the equivalent to verilog's PLI & VPI. All three are used to add system task (e.g. $display, $random, etc) to SV/V.Not quite equivalent enough for me. The PLI/VPI is a C interface to the simulator that is still relevant for Systemverilog. It lets tool developers add
hi there, I'm pretty new to ads and verilog-A (Version 2012 here!!!). I'm trying to build a custom model (starting with the most simple example of a resistor). I know how to write the code and have a basic knowledge of setting up simulations in ads. I went through all the tutorials and ads help to get an understanding (...)
Then you need to read a book on VHDL (or verilog)... c <= a*b; :thumbsup:
You mean a parameter (Generic is VHDL). assign some_signal = {width_paramter{1'b1}}; Right, exactly!
That inout port better be a top level port that is a bidirectional pin. You shouldn't be using submodules with inout ports. With that said. module bidir_io ( inout bidir_pin ); wire out_oe; wire out_sig; wire in_sig; assign bidir_pin = out_oe ? out_sig : 1'bz; assign in_sig =
thank you ads-ee.. now, I understand the purpose... on that note I would also like to know if it needs a aditional learning to design such a test bench or how do I get started with it... - - - Updated - - - I would like to see one such simple test bench... can someone help me... . . . PS: I googled before a
I can't believe the gall of Greeshu. Sent me a private message asking me to write the verilog for this Mario game. Obviously doesn't want to do any kind of work. What a troll... If you get PMs like that, please report them. Warning given. Keith
ads-ee is correct.... just check this code..... always @ (posedge clk) begin if (reset) begin out <= 0; temp <= 0; in <= 1'b1; //just for testing make it "1"... end else begin //$display(" value of in %d",in); //temp <= in; //$disp
A little formatting might make it more readable... Fully agreed. I was just reciprocating laziness, and as such did a quick copy/paste from that other thread with the kind of code snippet I'd use. ;)
HSPICE is a simulator, i think you are refering SPICE. I think SPICE is much more widely used in simulation, but I don't think it easy to program. verilog-A, in my view, is much more easier to program a circuit, but not all tools support it. I have no idea about whether Cadence IC supports verilog-A, but I know Agilent ads supports it.
hi all.... I want to know how it is possible to add a modul in agilent ads that contains verilog code,I have some verilog code for some logical block but I dont know how can I make linke between verilog and ads... I realy need that,please help me,,,,,,,,,,:sad:
Hello, Is there some AMS simulators (running on Windows) with full verilog-A, verilog-AMS syntax support. Some years ago I tried Smash and ads Agilent, but at that moment they had only restricted verilog-A, verilog-AMS syntax support. Regards, Pavel.
See "Laplace Transform Filters" in Analog Operators and Filters - ads 2009 -*Agilent EEsof Documentation Center And see the followings.
Hi there, I'm trying to design a crowbar overvoltage protection circuit in ads, and I was wondering what the best way to implement the SCR (or thyristor) is? Thanks, Mike.
Hi! I am trying to use the Hspice compatibility feature of ads, the .sp file I wrote include a verilog-A module. I am attaching the .sp and file here. For illustration, I use a file for a resistor downloaded online. But after I import the .sp file, ads seems can't compile the file correctly. The simulation status is the follo
Hi, Anyone installed their Cadence on Linux platform with ads dynamic Link? The Co-simulation is able to run on Solaris 10 unix platform. When run on Linux, the ads is unable to compile the verilog-A model files. The error looks something like this. "Error encountered during netlist parsing, .. file. ... *.cml not found. Anyone has a
if you are using ads you can just put a noise source in series with your resistor
It's easy to use verilog-A model in Cadence enveroinment. But it seems that it's difficaut to use user defined verilog-A model in ads. Is that? Can someone share a simple mathod to use user defined verilog-A model in ads?
Hi You should write ael component definition... And verilogA based component is working I have upload example for You AEL manual (in ads help) helps to understand "creat_item" Regards
Hello, I want to insert some analog blocks written in verilog-a code in ads2004A. I have done this in Cadence but in @DS there should be a different process. My question so, is how to insert the blocks.I could install the verilog-a design kit, and can see the verilog-A loader in the (...)
I have Advanced Desing System 2004A (ads2004A), and I want to write a verilog-a component.. I found in its manual that I can do that by adding "verilogA_Load component" from the "Devices-verilog-A palette" ... But I can't find that palette in my 'A'DS version.. then, I have some questions: 1) According to the manual, can I (...)
I have Advanced Desing System 2004A (ads2004A), and I want to write a verilog-a component.. I found in its manual that I can do that by adding "verilogA_Load component" from the "Devices-verilog-A palette" ... But I can't find that palette in my 'A'DS version.. then, I have some questions: 1) According to the manual, can I (...)
how can I insert verilog-A in ads (A.D.S) "Analog/RF Network" environment?
A few names that can do this job: Cadence Virtuoso, Microwave Office, ads. You can try Transient Analysis or Harmonic Balance (or both).
Does anyone know how to get a verilog-A module into the ads-simulator? Is it possible without making a new design-kit like the one which follows with ads (tiburon-da_veriloga) ? :?:
Hi all, Does any one know how to build a new verilog-A model in ads2004a ? i already know how to open and modify a built model (the models that came with the kit) but i tried to make my own model. i wrote the code and put it in the directory of the auto compilation search path (project_dir/veriloga) and the ads shows that (...)
Major vendors to look at are probably AWR (Microwave Office), Cadence (SpectreRF), Agilent (ads), Mentor (EldoRF), and Ansoft (Ansoft Designer).
Hi, I want to insert some analog blocks written in verilog-a code in ads2004A. I have done this in Cadence but in ads there should be a different process. My question so, is how to insert the blocks. There is a folder named "veriloga" where the veriloga files are stored but then i don't know what to do. (...)
Hi, can someone provide a model for the SRD? I need to use it in ads for a comb gen. design. I tried looking in some datasheets but they only provide the diode parameters without much explanations. Many Thanks!
Analog/RF circuit designers don't like any programming language like VHDL,verilog,even verilog-A/AMS for analog,but prefer drawing simulation tool--Simulink, ads for system verification. I never heard verilog-A can be synthesized now, but some EDA companys are attacking this target.
Is it possible to import HDL (VHDL or verilog) into ads? How about C or C++ codes? What i saw in ads is HDL generation from schematic or design. But i could not find anything about importing HDL (digital design) or C (high level language) codes from outside. Any helps will be appreciated. Thanks in advance, KH
Hi, I would like to do a mixed signal simulation. The system under simulation has an ADC (sigma-delta type) attached with subsequent digital circuit (I have already written the digital part using verilog (RTL)). Right now, I want to do a power estimation of my digital circuit, under a typical ADC. However, I don't have experience in analo
device modeling now is moving to verilog-A? does anyone has experience in design using this language? I mean using the model file provided by the foundaries? @ds has released its simulator/compilor for these modeling. @ds2003c is supporting this kind of simulation. There are some website for these: