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114 Threads found on edaboard.com: Ahb Bus
It's the forst time I'm dealing with bus. If you find AXI4 overwhelming for the first time, start with ahb-Lite spec, then go for AXI4-Lite and finally AXI4 itself. If you are going to write a BFM on your own well then good enough. Getting a free BFM (to understand how they are coded and how they work) can be challenging. Her
Hi. I found coretex M0 MCU module's bus interface has not HbusREQ and HGRANT, and HRESP when i trying to implement with ahb bus. Is there anyway to use ahb not ahb_lite. I can't use multi-layer interconnect system. only I can use ahb.
i am doing a project on AMBA-ahb interface with the referance AMBA specification 2.0.can any body help me to get the source in uvm(slave side).
i am doing a project on AMBA-ahb interface with the referance AMBA specification 2.0.can any body help me to get the source in uvm.
Please re-read the definition of a "bus" and re-think about your question. Else, are you asking about the no. of gate equivalents for an AXI/ahb interconnect matrix?
Have you decided on your Master and Slave modules? The ahb bus would provide data to be transferred between b/w the M and S. Without a Master and Slave an ahb i/f would be meaningless. Download the ahb Lite spec from ARM and read it too. oh, btw - Have you solved the problem of your thread - What am I do if I have to (...)
One proven and tested way to do this is to use a BFM (bus Functional Model). The BFMs generally cannot be synthesized and they are connected in a test-bench. e.g.- AXI BFM, ahb BFM, etc. I will not explain how BFMs work as a google search on the above will yield all infos you are looking for!
I have question on ahb bus ? Question ? 1 (related to issue faced in closing timing.) Basically I am new to ARM & its bus protocol, I have just started to work on it, so have lot of questions. I am referring to this diagram e.g . Can I say that arbiter + muxes + decode selection
Hi All, Why AXI bus is faster than ahb? Thank you!
Hi All, How does the multi-layer ahb bus work? Are there any useful articles you can recommend? Thank you!
It should basically check for the correctness of the ahb protocol..Whether it is in sync with the ahb standard...
Hi. I am willing to connect between ahb bus and sram. So I need the bridge that it can be connected ahb bus and sram. I have got sram.model but i don't know how can connect between sram and ahb bus. Is these any supported bridge?
There's no hsplit in ahb-lite.
FULL invert can be used to drive hready in write. Empty invert can be used to drive hready in read. But it would hold ahb bus for too long when fifo is full or empty. Or you can poll full/empty before do real write and read.
Hi i have a little confusion on the ahb Protocol and i need help. 1) why we use a delayed version of HMASTER on the HWDATA MUX (the multiplexer that used to connect the data bus of master to the slave) 2) i know that we keep the pipelining on ahb Protocol by delay the data(HWDATA) one cycle before the address(HADDR) (as i understand)
what is the major difference between verilog HDL and VHDL???? Which is best in designing the AMBA ahb, ASB,APB,AXI????? The biggest difference is VHDL's a strongly typed language and is significantly more verbose than Verilog. Either language will work well at implementing any if those bus protocols. Both lan
IF you have a multi master ahb bus Matrix and if you wants to go with self-motivated arbitration scheme, then you can go with a Round Robin arbitration scheme. Check the master zero first, if there is a request for any transaction then do the transaction then check for master one, then do the same. if the master is not requested for any transaction
You can, but throughput isn't very good, as APB takes at least two cycles per transaction. Better to use ahb.
Hi All, Could someone provide SHORT and CLEAR guides for ahb, OCP and AXI bus protocols ? Are there GOOD books for these subjects? Thank you!
can anybody explain the speed and data rate of AMBA ahb AMBA APB AMBA AXI ??
Hi, I from my understanding, we can configure the ahb transaction in many modes like burst of 16, 8, 4, 2, single etc. For example if we are configuring the burst of 16 with data width of 32 bits, which means in a single transaction there will be a transfer of 32*16 bits, within 16 clock cycles (here i am neglecting the initialization and the tran
Hi, I am confused with concept of burst transfer type related to AMBA ahb protocol. (1) If I am using 32 bit data bus then can size of my transfer i.e HSIZE exceed 32 bit? (2)What does 8 beat burst mean and what is maximum transfer size of my data in a burst if my bus width is 32 bit? Please explain me with an example!!!!!:roll
Hi, (1) How to determine number of bus cycle for read operation/write operation for AMBA ahb protocol. If I say bus cycle required for read /write is 4T states, then is it appropriate to say that for any amount of transfer on the bus the number of T states required is 4? (2) Does clock frequency is related to (...)
Hi, I am implementing arbiter module for AMBA ahb protocol for real time masters in verilog HDL. I want to know what value should I specify for HCLK signal. And what value should I consider for as my bus speed/bus bandwidth/bus rate? At least suggest me the source from where I can get this information. Waiting for your (...)
Hi; I am implementing arbiter module for AMBA ahb protocol in verilog HDL. For that I am considering real time masters having constraints in terms of deadline and service cycle. Now I am stuck at a point and want to know how the master convey this constraints to arbiter so that the arbiter will do the scheduling and grant the bus to one of the
Given this is the block doesn't appear to be a GPIO interface from the ARM so you'll have to write some HDL (Verilog/VHDL) to interface the ahb bus to a set of GPIO pins from the Versatile fabr
Hello there, Advanced High-performance bus (ahb) ahb is a bus protocol introduced in Advanced Microcontroller bus Architecture version 2 published by ARM Ltd company. it has the following features: 1.single edge clock protocol 2.split transactions 3.several bus masters 4.burst (...)
In page 5-3 there is a note that tells: "It is recommended that slaves do not insert more than 16 wait states, to prevent any single access locking the bus for a large number of clock cycles. " Can someone explain the implication of having a ahb-slave which may insert more than 16 wait-state other than system performance.
how do i find the data rate of the amba ahb , e.g if i have a clk of 200Mhz and use a data bus of 16bits. does it mean data rate = 200Mhz x 16bits .. how does burst play its role that's because i want to calculate FIFO length and i have 1mbps data going out at the other end - - - Updated - - -
hi guys, i have to do some calculations of how to handle the ahb bus bridge (connecting 1Ghz ARM and WLAN) , e.g i have to make a formula ( or excel sheet) for the wlan speed to bridge clock speed , e,g if i connect a 11Mbps wlan through a bridge to this ahb bus operated at 1Ghz( although it would also spare time for other (...)
i am doing a project on AMBA-ahb interface with the referance AMBA specification 2.0 from ARM. can any body help me to get the source in vhdl.
Usually, you can tie it to "OKAY" all the time, if: 1): The slaves on the APB bus will never generate "error" response (that means every r/w transfer will success). This is usually the digital circuit does. 2): The slaves on the APB bus can response the r/w access quickly enough to met your ahb bus requirement. (this means (...)
I need to prepare a ppt on AXI as an introduction i need to put the following INFO. Please provide sample materials/resources on the below: 1) What factors to be considered for performance of the bus 2) introduction for terms latency, bandwidth, power and expansion 3) introduce terms of transaction basic, atomic, exclusive (lock) , spl
I am using a STM32F4 FSMC to address external 16-bit SRAM on a custom board. Everything is OK. I want to connect an external FPGA and I'm not so clear about the actual addressing. Please correct me if I'm being stupid, the MCU is 32bit, but the internal ahb address bus is bytewise. The external address bus is 16-bit, so A0 addresses 2 x (...)
Hi All, I am planning to design an ahb master and slave RTL but literally confused with the inputs that should be supplied to the master RTL. Can anyone of you throw light on what are all the inputs that will be needed by a master bus?
Hello everyone I have a question about AMBA ahb bus. I wanted to know if there are any similarities between the burst and split operations in AMBA ahb. I am aware of the differences but wonder if there are any similarities. Thanks in advance
You need a memory controller to interface between the RAM and the bus managing memory read/write operation. You need to understand ahb protocol first.
I'm new to hardware design and I'm trying to add user logic to an ARM Cortex system. Can anyone provide me an ahb slave bus interface? At least some example code to get me started. Thank you
Hi anbuonlymevlsi, As nisshith said, for a 4 bit ALU there is no need of any pipeline mechanism. Here is an example where we can insert a pipeline mechanisms. Have you heard about the ARM's AMBA ahb protocol, in that protocol there is a pipeline mechanism. There is a shared Address bus for read and write operation. So if we are performing a burst
Hi all... Is anyone know how to calculate the through put of AMBA AXI or ahb buses... Means if i am transferring a 32 bit 16 Burst transfer through the AXI bus at 96MHz, then what will be the data through put of the transfer... Thanks in Advance....
Hi all, Is it possible to run CORTEX-M0 (which has a 32bit data bus) using an 8bit SRAM ? If possible, the method would be the following, right? Method: a memory controller has to be used(built) that operates as a ahb-Lite slave. Furthermore it has to use wait states to read 4 bytes to built a 32bit word. Tome it seems, it can't be done wit
Hi I have a question about opencores pci to wishbone bridge. In the test bench, the designers have set the pci clock period to 30ns (33 MHz) and similarly set the clock period of wishbone clock to 10ns (100 MHz) to test it. From this it makes sense because pci bus has a frequency of 33 MHz and wishbone bus has a frequency of 100 MHz. But i
Hi, Here's a tutorial presentation I had created for ahb bus training at my office. I've kinda put in only the relevant info need so that by the time you're through with it you will know at least most of the ahb bus details. Hope its useful! Thx
hi all i want to interface PCI with ahb bus....help me out in finding a verilog code for ahb to PCI bridge
you can add extra logic to wrapper the ahb-lite bus to support the operation!
Hi Shaiko, Yes you are right, it doesn't immediately make sense to have that many addresses. But, keep in mind that ahb support bridges to other different bus architecture (APB, AXI comes to mind) and sometimes it is easier to carve up the ahb address space using only the a few bits at the top (to keep address decoding cost down). narfnarf
Start with a list of functionality that you intend to support. Not everything in the spec is required. If you want to include APB and ahb with AXI interconnect, then yes, you would need some sort of bridging function. You also need to look at what architecture you intend to support (i.e. section 1.2.2 Interface and Interconnect). If you are
Hello everybody, My question concerns Libero IDE 9.1 : Is it possible to add an APB (or ahb) bus interface to a user defined HDL module which is recognizable by the 'Auto Connect' command in canvas? I've seen an Application Note regarding this issue but the device used in there was a Fusion FPGA not an Igloo. I've also read the Libero IDE u
I hope you get it in AMBA bus specification easily
Always ahb bus is used in advanced soc core,but what is the advantage of it?