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15 Threads found on Ahdl Library
Hey guys, I have a basic question. I built an ideal opamp in cadence using veriloga, ahdl library, and VCVS. I don't know, maybe I made a mistake, but none of them works when I use them in a switched cap (SC) circuit. When we define an ideal opamp, we say that output would be difference between opamp inputs times a gain. So if I use this opamp in
hi , I have used the verilog-A model of opamp in cadence ahdl library as shown in the file 82569. It models the dominant pole of the opamp and slewing limitation. following values were taken for the opamp parameters : open loop gain = 1000, unity gain frequency = 50 MHz shown here the schematic 82571[/ATT
what is Aldec ahdl simulator .Actually i am using xilinx 9.1i version and for simulation part modelsim 6.3 and i am implementing polyphase filters with fixed coefficients and the coefficient width is 20 and for single subfilter the vhdl code is library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED
You can generate proper VHDL code by the PDA IP core generator built in the Aldec ahdl simulator, which implements similar distributed arithmetic.
Hello to everyone, It is the first time that I am designing a Sigma Delta modulator. I have started with the example (verilogA) of the 1st odrer Sigma Delta modulator provided by cadence in ahdl library. I have performed a transient analysis (the input signal is 100KHz and is sampled with a clock 10MHz) and the modulator is working fine (I can
Hi everyone, I was trying to simulate the settling time of a D/A converter in cadence. Because I'm using a DAC from the ahdl library and it's an idea one, therefore the simulation result doesn't contain a settling period. I'm thinking to use a RC circuit to simulate that case but I'm not sure how I should do it so that there is a settling behavior
Hi I am trying simple integrator circuit with cadence using op-amp from its generic analog library (ahdl lib). This simple design works fine with sine input that I get nice cosine output. But feeding it with a pulse source doesn't result in an expected triangular wave. Does anyone see anything wrong. The circuit and the wave scan is appended
I am trying to use the op amp in the ahdl library. Does anyone know what should I connect Vref port to? How does Vref will affect Vout? thanks
I am trying to use the op amp in the ahdl library. Does anyone know what should I connect Vref port to? How does Vref will affect Vout?
Ny library include a ahdl file How can I include it in Ocean script?
i am beginner in vhdl so may be some guru can correct if wrong . You are trying to perform math on std_logic_vector (sub operation). Actually it should be done if library std_logic_arith is included into source code. Bit i tested that on ahdl activehdl : fucntion "-" op1 with std_logic_vector and op2 Integer is not visible from library . (...)
Hi Scuhai, Since your data rate is 622Mbps, then your period will be 1/R(data rate). So, it will be 1.60ns. In the PRBS generator which u can get from ahdl library, under the "tperiod" option, you have to put the value of 1.60ns. Now after you are running the simulation, when you want to view the eyediagram of any node, you click "VT" in calcula
Hi I find a VCO from Cadence ahdl library, just as: ------------------------------------------------------------------- module vco(vin, vout); input vin; output vout; electrical vin, vout; parameter real vco_amp = 1.0 from (0:inf); parameter real vco_cf = 1500.0 from (0:inf); parameter real vco_gain = 1000.0K exclude
you can add the ahdl library into candence, then you can call the ideal opamp there to run simulation.
Do you mean Analog-HDL, Altera-HDL, (another one I don't remember)... ? If I remember correctly, Altera has some doc about ahdl (altera-hdl..)