36 Threads found on edaboard.com: Ahdl To Vhdl
You can use the xport utility.
Is there a Utility which converts ABEL or ahdl designs to Verilog or vhdl format
This is included as a utility in the xilinx tools and can
be found at %XILINX%/bin/nt/xport.exe.
It needs to be run via a DOS window.
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.04.2003 09:55 :: gnomix :: Replies: 2 :: Views: 3464
XPORT can translate ahdl to vhdl.
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.04.2003 09:50 :: shawndaking :: Replies: 0 :: Views: 1905
I have tried such "mechanical" conversions, and the result is generally not pretty.
Abel is lower level (more hardware oriented) than vhdl, and the language structure is very diferent, too. Therefore the conversion result is quite unreadable. Altera has something called ahdl, which is much closer to Abel, and porting Abel HDL to ahdl (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.06.2003 17:58 :: ted :: Replies: 2 :: Views: 4062
This program can convert ahdl, ABEL to vhdl
Software Links :: 29.08.2003 03:45 :: serein :: Replies: 7 :: Views: 6011
can anyone provide me FFT code in ahdl or vhdl as an example, bcz in @ltera website they just displayed a diagram nothing else.
for N=32 and data rate is 128 Ksbs.
I shall be very thankful to you.
RF, Microwave, Antennas and Optics :: 05.12.2006 19:51 :: Ravians :: Replies: 0 :: Views: 636
This is a very asked question .Several times we have debated about it .
No need to start over and over ..
Do some search at EDA all is here
HDL is both verilog and vhdl well as others ahdl etc
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.01.2005 12:06 :: eltonjohn :: Replies: 14 :: Views: 1553
a few years ago, i use ahdl to program altera's fpga. but now i use vhdl. vhdl is more powerful, agile and readable than ahdl.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.04.2005 12:20 :: ddt694 :: Replies: 3 :: Views: 820
unfortnatly i dont know vhdl programing. i need a seven sgment counter (4 digit) and a multiple cycle microprogrammed computer (CPU) designed in ahdl or vhdl.
could u do anything for me about these?
Electronic Elementary Questions :: 03.07.2006 18:18 :: rs_408 :: Replies: 5 :: Views: 1346
The library name is ahdlLib. It is in the cadence data base. It is easy for you to find it. there are many verilog-A model for you
Analog IC Design and Layout :: 11.03.2007 21:11 :: pfd001 :: Replies: 2 :: Views: 1602
Are both ABEL and ahdl "dead" languages?
I'm just wondering, because Xilinx tools still support ABEL, and Altera tools still support ahdl.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.04.2007 22:26 :: modelsim62c :: Replies: 2 :: Views: 1012
I have been lately working with an @ltera ACEX1K50 based design where the chip should be fast enough, but tooling produces lousy results. I had a related question earlier and received a valuable hint from ngjh (Many Thanks!)
But the next step is that in spite of search at @ltera web site and a question to their support I still find it difficult
ASIC Design Methodologies and Tools (Digital) :: 19.09.2002 23:48 :: ted :: Replies: 2 :: Views: 1470
Does anybody have a vhdl or ahdl sourcecode to generate an IEEE 488 controller like the 7210?
A friend of mine is looking for this for a long time, any hint where to get it (preferably for free) would be very nice ...
thanks and best regards
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.11.2003 11:36 :: C-Man :: Replies: 1 :: Views: 2656
Can I add some instruction or option to define specific FPGA (CPLD)device in my project. My Customer is given 'edif' or 'tdo' files for further sinthesis. I do not want him to implement another device except specified one for compilation. How to protect my design?
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.04.2004 07:22 :: sir-yuri :: Replies: 2 :: Views: 679
Also, ahdl may be replaced by vhdl-AMS.
Analog Circuit Design :: 06.01.2005 10:07 :: geconom :: Replies: 4 :: Views: 2157
Thank you very much!
If you like, would you like to explain your method (or code)? I am a freshman.
If you use schematic capture see for OPNDRN primitive.
If you use ahdl - code example bellow:
FOR i IN 0 TO 3
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.02.2005 10:24 :: Black Jack :: Replies: 4 :: Views: 2114
The difference b/w these cannot be defined. The difference exists in the constructs used to code in these languages. All 3 are H/W description ;languages vhdl & VerilogHDL are standard HDLs, ahdl is a propreitary language of Altera.
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.04.2005 08:48 :: Sparc :: Replies: 3 :: Views: 1224
Hi everybodies !!!
I 'm programming CPLD on Quartus2 5.1 sp1 web edition.
I'm an user of Max2plus, and I migrated to quartus2.
I am unable to obtain the same results.
I'm used to programm in ahdl, but quartus 2 does code simplification, and doesn't provide any means to empeach these simplification in ahdl.
I'm migrating to vhdl/Verilog, (...)
Software Problems, Hints and Reviews :: 24.08.2006 03:47 :: fguihot :: Replies: 1 :: Views: 859
i am beginner in vhdl so may be some guru can correct if wrong . You are trying to perform math on std_logic_vector (sub operation). Actually it should be done if library std_logic_arith is included into source code. Bit i tested that on ahdl activehdl : fucntion "-"
op1 with std_logic_vector and op2 Integer is not visible from library .
PLD, SPLD, GAL, CPLD, FPGA Design :: 31.08.2006 21:06 :: artem :: Replies: 4 :: Views: 758
Hi, i was wondering if anyone has had experience running vhdl files in Cadence environment. What I meant is that, you wrote some vhdl file in design.vhd and then supposingly import into cadence and it generate entity and structural and a symbol. This is as far as I got, but then when I try to simulate it, I encounter 2 problems:
1) I am not sure
Linux Software :: 14.12.2006 03:08 :: jowong1 :: Replies: 4 :: Views: 1806
Can someone help me understand what this code is doing. I was tasked with modifying the adress length from 32 bits to 31 bits, to 30 bits......and watch what happens.
--Connections active HIGH
clock :input; -- timebase input
run :input; -- runs and resets the address decoder
ASIC Design Methodologies and Tools (Digital) :: 17.03.2008 17:42 :: robismyname :: Replies: 0 :: Views: 1009
hey, a program in vhdl, ABEL, ahdl, C, Basic or what? please, be more specific!!!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.04.2008 07:47 :: btminzon :: Replies: 4 :: Views: 642
thank u so much.. because i m still a newbie to this area i m not familiar with ise, qu(at)rtus . i know little bit verilog and c progranning. can i write the logic in c or verilog with those tools? further help is really appreciate
anyway thanks u soo much j_andr
Yes, with Verilog or vhdl (both) or ABEL
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.07.2008 07:09 :: Black Jack :: Replies: 7 :: Views: 676
I'm looking for HDL code for mil-std-1553 RT. ahdl, vhdl or Verilog. May be schematic sourses or thmsng what looks like it) Ilgaz, could you post some info, or send t PM, plz.
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.01.2010 12:10 :: VolandXT :: Replies: 9 :: Views: 1644
what is Aldec ahdl simulator .Actually i am using xilinx 9.1i version and for simulation part modelsim 6.3 and i am implementing polyphase filters with fixed coefficients and the coefficient width is 20 and for single subfilter the vhdl code is
Digital Signal Processing :: 26.10.2012 14:38 :: kannan2590 :: Replies: 0 :: Views: 247
coding in vhdl...
- - - Updated - - -
i just to recognition one word only.....
i need coding in vhdl or ahdl or verilog
- - - Updated - - -
the word have 2 record to memory at de2 board, after that when somebody speak same word ledr at de2 board can on(dispaly)
Software Requests :: 16.12.2012 02:23 :: ganu4686 :: Replies: 4 :: Views: 17
I am now working on a shift register. The shift register is defined as WxMxN, wherein W is the input data width, M is the distance between taps, and N is the total tap number. Alter QuartusII provides Megawizard function to implement such shift register using RAMs. Is there a counterpart for Xilinx ISE?
This simple task
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.06.2004 06:58 :: Black Jack :: Replies: 4 :: Views: 1575
It depends what you want to simulate or modelling:
vhdl/Verilog (Modelsim, LDV)
Matlab (for very complex systems like receiver with rf frontend, sigma-delta converter, baseband processor)
C/C++ complex and difficult to read for other designers, but very fast
ASIC Design Methodologies and Tools (Digital) :: 18.03.2005 08:26 :: eda4you :: Replies: 16 :: Views: 1500
There will be no source code for a delay of 1 second because it is not possible to synthesize timings. Instead you have to use a counter which counts every rising edge of a clock signal.
clk = 10 MHz --> t = 100 ns
1 secound / 100 ns = 10.000.000 (10 M)
So you will need a counter which counts from 0 to 9.99
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.01.2005 03:06 :: cube007 :: Replies: 17 :: Views: 1358
I need Gaussian and uniform noise. I can’t use a function because I need to put it in a FPGA so I need to make it out of basic math (+, -, * etc..). I’ve used the MATLAB noise generators and they work great.
You can use LFSR (Linear Feedback Shift Register) to produce noise in certain band. For
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.02.2005 02:00 :: Black Jack :: Replies: 5 :: Views: 1741
I'm interested too.
I normally simulate the digital part seperated using synopsis.
You can use ideal digital model from ahdl library to speed up the mixed-signal simu.
However, I guess there are better solutions.
Analog IC Design and Layout :: 27.03.2005 19:10 :: globaleda :: Replies: 5 :: Views: 1008
i would like to know which tool is better for behavioral modeling, for example, for PLL or CDR.
please also tell me whether you are in company or in university. i would like to know what people use in these two different areas.
i think the candidates are Matlab, simulink, ADS, verilog-a or ahdl, etc.
Analog IC Design and Layout :: 25.06.2005 22:41 :: beabroad :: Replies: 23 :: Views: 2114
1. sepctre support all
2. you can write the code or
the lib ahdl include many example
Analog IC Design and Layout :: 26.09.2005 22:36 :: sunking :: Replies: 8 :: Views: 2385
In Cadence you can use ahdl and verlioga for behavioral analog modeling.
Analog Circuit Design :: 06.08.2006 06:45 :: pixel :: Replies: 6 :: Views: 2080
You can generate proper vhdl code by the PDA IP core generator built in the Aldec ahdl simulator, which implements similar distributed arithmetic.
Digital Signal Processing :: 25.10.2012 05:27 :: Aser :: Replies: 1 :: Views: 439
I generate Verilog/vhdl/ahdl using Quartus II by 7 click mouse
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.02.2013 16:58 :: slava_edf :: Replies: 5 :: Views: 1204
I will switch to this style with immediate effect :)
Remember that if you are instantiating Verilog, ahdl or black box components in your vhdl, you still need a component declaration.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.01.2013 05:02 :: TrickyDicky :: Replies: 6 :: Views: 211