15 Threads found on edaboard.com: Ahdl To Vhdl
Unfortunate the floating point vendor libraries aren't provided as vhdl sources, most likely they even haven't been written in vhdl or Verilog. They are designed to use the DSP hardware of different FPGA families in an optimal way, using respective low-level primitives. Altera e.g. is typically writing this stuff in ahdl.
For the same (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-09-2015 06:39 :: FvM :: Replies: 7 :: Views: 326
hey, a program in vhdl, ABEL, ahdl, C, Basic or what? please, be more specific!!!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-15-2008 07:47 :: btminzon :: Replies: 4 :: Views: 682
Can someone help me understand what this code is doing. I was tasked with modifying the adress length from 32 bits to 31 bits, to 30 bits......and watch what happens.
--Connections active HIGH
clock :input; -- timebase input
run :input; -- runs and resets the address decoder
ASIC Design Methodologies and Tools (Digital) :: 03-17-2008 17:42 :: robismyname :: Replies: 0 :: Views: 1102
Are both ABEL and ahdl "dead" languages?
I'm just wondering, because Xilinx tools still support ABEL, and Altera tools still support ahdl.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-12-2007 22:26 :: modelsim62c :: Replies: 2 :: Views: 1173
can anyone provide me FFT code in ahdl or vhdl as an example, bcz in @ltera website they just displayed a diagram nothing else.
for N=32 and data rate is 128 Ksbs.
I shall be very thankful to you.
RF, Microwave, Antennas and Optics :: 12-05-2006 19:51 :: Ravians :: Replies: 0 :: Views: 741
i am beginner in vhdl so may be some guru can correct if wrong . You are trying to perform math on std_logic_vector (sub operation). Actually it should be done if library std_logic_arith is included into source code. Bit i tested that on ahdl activehdl : fucntion "-"
op1 with std_logic_vector and op2 Integer is not visible from library .
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-31-2006 21:06 :: artem :: Replies: 4 :: Views: 821
The difference b/w these cannot be defined. The difference exists in the constructs used to code in these languages. All 3 are H/W description ;languages vhdl & VerilogHDL are standard HDLs, ahdl is a propreitary language of Altera.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-25-2005 08:48 :: Sparc :: Replies: 3 :: Views: 1334
a few years ago, i use ahdl to program altera's fpga. but now i use vhdl. vhdl is more powerful, agile and readable than ahdl.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-04-2005 12:20 :: ddt694 :: Replies: 3 :: Views: 885
This is a very asked question .Several times we have debated about it .
No need to start over and over ..
Do some search at EDA all is here
HDL is both verilog and vhdl well as others ahdl etc
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-26-2005 12:06 :: eltonjohn :: Replies: 14 :: Views: 1624
Also, ahdl may be replaced by vhdl-AMS.
Analog Circuit Design :: 01-06-2005 10:07 :: geconom :: Replies: 4 :: Views: 2377
Does anybody have a vhdl or ahdl sourcecode to generate an IEEE 488 controller like the 7210?
A friend of mine is looking for this for a long time, any hint where to get it (preferably for free) would be very nice ...
thanks and best regards
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-11-2003 11:36 :: C-Man :: Replies: 1 :: Views: 2750
This program can convert ahdl, ABEL to vhdl
Software Links :: 08-29-2003 03:45 :: serein :: Replies: 7 :: Views: 6011
I have tried such "mechanical" conversions, and the result is generally not pretty.
Abel is lower level (more hardware oriented) than vhdl, and the language structure is very diferent, too. Therefore the conversion result is quite unreadable. Altera has something called ahdl, which is much closer to Abel, and porting Abel HDL to ahdl (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-08-2003 17:58 :: ted :: Replies: 2 :: Views: 4233
You can use the xport utility.
Is there a Utility which converts ABEL or ahdl designs to Verilog or vhdl format
This is included as a utility in the xilinx tools and can
be found at %XILINX%/bin/nt/xport.exe.
It needs to be run via a DOS window.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-15-2003 09:55 :: gnomix :: Replies: 2 :: Views: 3700
XPORT can translate ahdl to vhdl.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-15-2003 09:50 :: shawndaking :: Replies: 0 :: Views: 1972