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10 Threads found on Ahdllib Using
Couple suggestions: 1. Check Environment (Setup/Environment/Switch View List). Must contain "veriloga" 2. Use resistor models from built in libraries: ahdllib (veriloga model); and analogLib (spice model). See if you are able to probe currents/voltages/dc operating points. If the result is still negative: check your library version with spectr
Hi everyone, I am using verilog-A to build up a behavior model of opamp for LDO. My opamp is a differntail input folded cascode and single output amp, and I am going to limit the output range of it between vdd-2Vov and 2Vov. I looked at the opamp example in the ahdllib, which is in the virtuoso library, and can't figure out the code in "soft output
For this purpose, you can use the simple amplifier in the ahdllib library (or base your own design on that).
If you have the analogLib: pvcvs2 or ahdllib multiplier or functional multiplier.
use rand_bit_stream from ahdllib
Hello . I am trying to get the DNL from 10 bit sar adc ? I am using , cadence library "ahdllib , dac_10bit_ideal " to convert the 10 bit ADC ramping output " D9:D0 to analog signal . Then using , " cadence library " ahdllib , dac_dnl_10bit " to get the DNL of the ADC ? It supposed to output a histogram file or someting . (...)
Hi! I am trying to measure the INL of an ADC using the adc_inl_8bit from the ahdllib. I have customised the verlioga code for the INL measure since my ADC is of 5 bit. When i am simulating in spectre i am getting an error where it states ("Internal error found in spectre during IC analysis, during transient analysis `tran'. Please run `getSpectr
If you are using Cadence, there is a cell called "rand_bit_stream" inside the library name "ahdllib". You can use that to generate random data. If you are not talking about Cadence, maybe the follow code might help you integer iseed; bit = abs($random(iseed)) & 1; hope this helps!
Put a DAC at the output from the ahdllib and record the sinuoidal signal. Sample it and find out what code it is on every sampling instant. Take the recorded data to matlab using printvs. and run the histo function on it. =========== I am suggesting this, since manipulating all the digital signals, converting them to a value and recording
In the ahdllib, there is an opamp that is verilog-A based. This already has built-in parameters for gain, input resistance etc.