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V(in, out) <+ 0.0; //for on state I(in, out) <+ 0.0; //for off state You also can describe smooth switch by tanh(). You can see many examples in "ahdllib" and "bmslib", if you have Cadence dfII.
Hi all, what is the design of SR flip flop for voltage mode boost converter i try this circuit and it doesn't work like ideal one from ahdllib on cadence { } :drevil: :thumbsup:
Hi, i have a problem with the op amp in the ahdllib in Cadence. I connected it as voltage follower with sinusoidal Vin+ (Amplitude 2.5V, f=10k), Vdd=5V. I set the following parameters for the opamp: gain=10000 frequ_unitygain=100M rin=10M vin_offset=0 ibias=0 (input current) slew_rate=10M rout=50 vsoft=4.9 iin_ma
Hi, In attachment ahdllib for IC5.
Hi, ahdllib -> rand_bit_stream or you can build your own random data source in Verilog-A
Hi, Has anybody used ideal opamp from cadence ahdllib. I am trying to simulate it with Vsupply_p=1.2V, Vsupply_n=0V and Vref=600mV in unity gain configuration. However, for a sine wave input, output is just a constant dc voltage. I tried to change different parameter values but it did not work.
Couple suggestions: 1. Check Environment (Setup/Environment/Switch View List). Must contain "veriloga" 2. Use resistor models from built in libraries: ahdllib (veriloga model); and analogLib (spice model). See if you are able to probe currents/voltages/dc operating points. If the result is still negative: check your library version with spectr
Hi everyone, I am using verilog-A to build up a behavior model of opamp for LDO. My opamp is a differntail input folded cascode and single output amp, and I am going to limit the output range of it between vdd-2Vov and 2Vov. I looked at the opamp example in the ahdllib, which is in the virtuoso library, and can't figure out the code in "soft output
OK, in "functional" lib there is "multiplier", and in "ahdllib" there are actually am_ and fm_ modulator and demodulator (and pcm_). At least this is what I have. These libs are Cadence-supplied.
I think there is something wrong in the circuits? the opamp is from cadence ahdllib,both of the gain and GBW are set to 69dB and 400M.the ac result is ok,but this fully differential opamp cant work in my loop? is anything wrong ?
Hi, I am a fresh in the ADC design. now i wanna test a 4b flash 52Mhz quantizer with this ahdl code in virtuso, plz give me some description of that, appreciate a lot.
The examples in ahdllib are so simple. They could not fit our needs.
For this purpose, you can use the simple amplifier in the ahdllib library (or base your own design on that).
If you have the analogLib: pvcvs2 or ahdllib multiplier or functional multiplier.
use rand_bit_stream from ahdllib
in the analogLib, No existing ideal comparator, you can find it in ahdllib. and you need add "veriloga" view in the switch view list to the environment.
Hello, when i use a ahdllib's componet in a schemtic i get an error, why?? How can we know if you don't tell us, when you get it, and what is its message? can't i use this library? Sure you can! When i go on the properties of ahdllib's componet, when close the window
Hello . I am trying to get the DNL from 10 bit sar adc ? I am using , cadence library "ahdllib , dac_10bit_ideal " to convert the 10 bit ADC ramping output " D9:D0 to analog signal . Then using , " cadence library " ahdllib , dac_dnl_10bit " to get the DNL of the ADC ? It supposed to output a histogram file or someting . But I dont see any file ?
Hi everybody.... Where can I find information about the component of the Cadence libraries ahdllib and analogLib. Thanks
Hello all, I have just designed a 8 bit ADC. I was wondering how can find out the INL/DNL of my ADC? I know that I could use the ideal 8 bit DAC that is in the ahdllib in Cadence. But I just don't know how to set the attributes in the ideal 8 bit DAC. Can anyone please tell me how to do that? Does that ideal 8 bit DAC work with hspiceD? I would
The library name is ahdllib. It is in the cadence data base. It is easy for you to find it. there are many verilog-A model for you
I want to use a square wave vco to run some test on my circuit, I found this "dig_vco" cell inside "ahdllib" but I can't make it work Can anyone teach me how to configure this component? I am ramping a voltage source from 0.7V to 1.4V (within 0s to 1u) Attached is the snapshot of how I connect my VCO & parameter values
There is a 'switch' component in ahdllib. It is written in VerilogA. You can try it.
Hi! I am trying to measure the INL of an ADC using the adc_inl_8bit from the ahdllib. I have customised the verlioga code for the INL measure since my ADC is of 5 bit. When i am simulating in spectre i am getting an error where it states ("Internal error found in spectre during IC analysis, during transient analysis `tran'. Please run `getSpectr
It is an OP model from ahdllib in Cadence. Why there is a "Vref" pin? And how to use it?
If you are using Cadence, there is a cell called "rand_bit_stream" inside the library name "ahdllib". You can use that to generate random data. If you are not talking about Cadence, maybe the follow code might help you integer iseed; bit = abs($random(iseed)) & 1; hope this helps!
hello everyone, I am trying to write a opamp model with verilog-A, there is a model from ahdllib, however, I want something diff in with diff out and now I am stucked to how to define the output stage with Common-mode voltage. Any suggestions? Regards,
u can find it in ahdllib. there is verilog-a model for VCO
I guess what you really need is a fully differential OTA behav model in Verilog-A. If that is the case, you can build it with the prototype in ahdllib and then exapnd it to include more non-ideal effects, such as finite bandwidth, output impedance, output swing, offset, etc. There is no need to really create a specific 'folded-cascode' OTA because
If you have Cadence EDA tools, the best starting point is to use Verilog-A behav. model included in 'ahdllib'. From there you can add extra features/non-idealities to that model and make your DAC model more realistic.
Hi I am simulating in Spectre the ideal 8bit DAC from the ahdllib. What seems strange is that from the DFT analysis the SFDR is about 60db. It is to small for the ideal case. Have you ever come up with this case? Thanks
Put a DAC at the output from the ahdllib and record the sinuoidal signal. Sample it and find out what code it is on every sampling instant. Take the recorded data to matlab using printvs. and run the histo function on it. =========== I am suggesting this, since manipulating all the digital signals, converting them to a value and recording
You have to press 'Q' for querying the a2d, I assume it is coming out of the ahdllib and then setup the parameters correctly. especially the reference voltage. With the pulse source, there are only two states and a very brief rise/fall time, but with a sin, the resolution of the converter will play a part.
In the ahdllib, there is an opamp that is verilog-A based. This already has built-in parameters for gain, input resistance etc.
You can use the Verilog A models to be configured as your ideal gates and flip flops. Then you can run them in IC 5.0....Please refer to the ahdllib directory in Cadence.
In the ahdllib in Cadence there are "ahdl" and "veriloga" views. The synthax is different. I am confused with the difference between them. "veriloga" should be a Verilog-A model. It seems that "ahdl" stands for SpectreHDL language - what is it? Which model is better to use?


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