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42 Threads found on Altium Net Name
sorry it's altium summer designer 09
the only way no assign a net name in altium is to place a net label. But you would have to do this for every net. You could generate a netlist in text format from your schematics and then use a text editor to globally change the names.
altium has options to let higher level net names take priority, let power port names take priority. It does not, unfortunately let you decide in what order these options take effect. Some Aussie programmer just went off and assumed on your behalf that if both are checked that you MUST have wanted net >> (...)
How do I put a net tie on Layers 2 of my 4 layers board. This is how I have it: Signal GND VCC Signal I want to tie all the different grounds on the GND (Layer 2) at a certain point and altium is not letting me put my net Tie on Layer 2. How do I do this?
Hello All As altium doesn't have a library entry fot the Holtek 12E (or family) what are you supposed to do when wanting to enter a circuit? I'm trying to use a generic DIL-18 entry (from PcbLib) to allow me to enter my circuit shematic so that I am able to autoroute with ground planes etc. - NO!! If a SPICE listing for these were available
You can't print the net labels that are shown on the pads in altium Designer except by using screen capture as you have done for the picture you posted. You can get a PDF with links to the nets by using SmartPDF. It creates an index that will zoom the PDF display to the object when you click on the net (...)
Hi I was working on altium Designer V6.5 but I updated it to 6.8 and then I saw that when highlighting nets with the panel at top right of screen other nets aren't colored and it is difficult to recognize top or bottom layer tracks. because they are all gray scale ant not colored. but I am not in single layer mode or monochromes or gray (...)
Hi all, I am back annotationg Ref Des from PCB to Schematic but the problem is that by doing this net names doesnot change with ref des they remain as per old (which result ion DRC errors and i have to unroute all the there any procedure with which I can change the only ref des. Thanks in Advance, Ricky
Hello, Please in a summer project ad i need help, the problem with altium is an ERROR that shows " Dulpicate net names Element " this appear when i used a BUS and the is a wire that come from this BUS, and the net name is A0 used in two différent sheet, please help me, thanks,
Hello, I have a problem under altium. I linked the TOTO signal of a component to GND and now on my PCB, all my GND have been named TOTO....:cry: Thank you for your help, Alex
So I've got this LED i'm trying to use in a design for a 7 segment display. The LED has 2 anode and 2 cathode pins. Thus far I have found a way to get the two pins on the same net in altium (Summer 09). However, if I don't connect both pins in the layout I get a DRC. Is there a way to prevent this? I would like to be able to connect to eit
What I have understand of ports in altium is that they are used for hierachicl connections to top sheet. If you do not want to use net label than you can to use off page connector(exact name I do not remember but it looks like "->>" and "<<-").
It will connect to "no net" pads as you are assigning a net name (as altium sees it), it is similar to assigning any other net name, as you have tried with GND, and if you leave the net name option empty it wont pour any copper. I think you want to put dead (...)
hello, I have a surface mount component (8-pin soic) in altium with a thermal pad in the middle, the thermal pad in the footprint has 4 thermal vias in it. I need to connect these to my ground plane, but I'm getting several errors, and it wont connect. I'm getting Clearance Constraint Errors from the via to the pad, and short circuit constrai
If you can post an image of relevant to you question, we would be able to understand you better then give you a sound advice. Can you do that for us? For the mean time, you can read about the basics of Hierarchical designs in altium using this link: Multi-Channel Design C
Hello everyone, I would like to seek advice on the proper way to doing back annotation with altium Designer. What is the proper way to update a schematic from PCB with net name changes?
Thanks Keith, actually i dont want the nets to have the same name....the whole point is to have two nets of different names shorted together at a particular point......its called a net tie in altium or a start point in cadstar...... so its "snap length" which provides the "stop on (...)
I have searched and am unable to find to a solution to my problem. I have created a part for one of Samtec's high density pin arrays (40x4). The schematic is created using four parts corresponding to each column of pins. Each pin designator of the parts maps to one footprint pin, i.e. 1-160. Upon placement of the footprint of the connector, the
Hi, I am going through the altium tutorial here on implementing an FPGA design (simple counter) in altium. I am having trouble with the "Wiring the Design" portion in that I cannot seem to connect U5 and U1 to the Q bus on U2, which drives some L
I am using altium DXP to design a PCB. When I build a SMT connector using PCB component wizard, the bottom layer is always there. How to delete this bottom layer? Any suggestions are appreciated.
hi. is it possible to define the net/component classes in the schematics level? if yes, how to do that? because if i import changes from sch, in the pcb, then it wants to remove all my net classes and component classes. i have to switch off these in the differences list, but if i miss it, then it makes big troubles on the PCB.
Hey, would someone know how to place PORT in eagle (like in altium, see the red ellipsis on the screenshot). Thanks !
I get a "Un-Routed net Constraint Violation": net 3V3 is broken into 4 sub-nets. How do i know what nodes are not connected to 3V3?
Hi I have some net names that I would like to rename. IOP1 IOP2 etc I want to rename them to IO1_P IO2_P Is there a quick way to do this? Cheers Jon
Hello, I'm working in a company as an Electronics Engineer at R&D department I want to use Microchip's MCP6V02 Spice model in altium Designer Summer 2009 program but i have a problem. When I try it in my project I get error called; Class Document Source Message Time Date No. Sheet1.SchDoc Compiler Component U1 MCP6V02
The directives mentioned by Anonymous_Ricky are just parameter placeholders. Once those exist on the schematic, net classes can be pushed from PCB back to SCH. The reality is though, most of the time this is not necessary in my experience. As for the absence of a "net class manager" - that's not strictly true. Technically net classes (...)
Hi guys, Can u describe the steps to make a new component in the library. I already made the footprint and the schematic of the component. Do I need to compile it when its finish? Kind regards, Jo Added after 2 hours 49 minutes: I made a new schematic component. But the pin names are shown out
The diff. net pair must be named with net label suffixes of _N and _P. Look for the AP0135 PDF in your altium help folder.
I have created a polygon pour in AD and connected it to my GND net. When I pour it it connects all of the power nets to the pour. It also doesnt seem to be using the correct clearance around the signal nets. I'm sure I have some setting wrong but dont know which one. Thanks Jon
I'm not aware of a way to place a bus directly on a component (you would normally break the bus out to the individual pins), but I think you can accomplish what you want with a Device Sheet: Using Device Sheets - English documentation - The altium Wiki
I haven't run into that problem but it looks like altium doesn't want duplicate net names on different subsheets. From Page 37 of the compiler error
Here's a link to some helpful tips: ? altium Designer Tips Johns Blog For questions 3 & 4, you click on an object (say, a component or trace), then right-click -> Find Similar Objects. If you want to select all components, set "Object Kind" to "Same", click OK and
Is it possible to synchronize two .pcblib files and find differences? I'll try to illustrate an example: Two libraries has same name QFN.pcblib (has 30 footprints) and another QFN.pcblib (has 35 footprints). Some footprints are the same (QFN32 in the first ant same in the second), but there are some components that exists only in first or onl
those two components are from altium library or you created them? check pin orientation. -- tantudaisu --
Hello. For one of the board i have to made at work i need to put on board for one component the possibility to use PDIP or soic package. So i create on footprint editor a footprint with the the two design and pads connected with line. The problem was, when i import the footprint on PCB all the footprint was in violation constraint (shortcircuit bet
One thing that got me recently is that you can't just have a yellow port named Test and a thick blue wire, and off that a singleton net Test1. You must also have a net label on the thick blue bus wire named Test. It's not realizing that Test1 and the port are related. Singleton net to (...)
I am using altium 10.391 (2011) and am still pretty new to it but am practicing with a small design. I was wondering, how do I view the net names of the wires on my schematic page? Like if I want to know the name of a specific wire how do I do this? I know they are named based on where they are connected but (...)
Hello all, I am creating a Pcb with altium Dxp for the first time. Simple issue: The default clearance rule on the board specifies 8mil. See here: 86034 This is fine for everything on the board except for some nets which will carry higher voltage, for which I would like to set the clearance to 16mil. I have created the
If you hold the Control key while clicking on one of the net connections, all of the portions of the board to which that net is connected will be highlighted, and the rest of the board will be masked. You can also use the PCB Panel. Go to the top of the panel, select nets, click on "All nets". Wait for (...)
hi do you know how can set net label in pad logic and i eco my schematic to layout design but unlike other software such as protel or altium designer it doesn't place the name of the terminal or pad and it's net i cannot find how to show this in layout can you help me thank
i m using altium . so from altium i hav expoted Orcad/PCB2 netlist from schematic. i changed the netlist as per allegro package. but couldnt load the netlist. what should i do?
which tool you use - - - Updated - - - do you use Protel DXP or Altuim I used altium designer 10