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13 Threads found on edaboard.com: Amba Ahb Bus Protocol
Hi, I am confused with concept of burst transfer type related to amba ahb protocol. (1) If I am using 32 bit data bus then can size of my transfer i.e HSIZE exceed 32 bit? (2)What does 8 beat burst mean and what is maximum transfer size of my data in a burst if my bus width is 32 bit? Please (...)
Hi, (1) How to determine number of bus cycle for read operation/write operation for amba ahb protocol. If I say bus cycle required for read /write is 4T states, then is it appropriate to say that for any amount of transfer on the bus the number of T states required is 4? (2) Does clock (...)
Hi, I am implementing arbiter module for amba ahb protocol for real time masters in verilog HDL. I want to know what value should I specify for HCLK signal. And what value should I consider for as my bus speed/bus bandwidth/bus rate? At least suggest me the source from where I can get this (...)
Hi; I am implementing arbiter module for amba ahb protocol in verilog HDL. For that I am considering real time masters having constraints in terms of deadline and service cycle. Now I am stuck at a point and want to know how the master convey this constraints to arbiter so that the arbiter will do the scheduling and grant the (...)
Hi anbuonlymevlsi, As nisshith said, for a 4 bit ALU there is no need of any pipeline mechanism. Here is an example where we can insert a pipeline mechanisms. Have you heard about the ARM's amba ahb protocol, in that protocol there is a pipeline mechanism. There is a shared Address bus for read and write (...)
Hello, I have a question about a master to slave transfer on an ahb-lite bus. Suppose, an ahb-lite master initiates a transfer to an ahb-lite slave. If the slave can respond at once, everything goes fine. But if it takes the slave many cycles to do the job the slave must issue an HREADY='0' for as long as it's (...)
I hope you get it in amba bus specification easily
Hi all, I have some difficulty by understanding the reason why only one master can own the bus system at the time even if another master do not want to access the same target which responds the first master request. which penalty shall the bus to face if it is suitable to deal with this option? Thanks Mido
PLS SEND THE VERILOG CODE
Hi Can any body tell my what is split and retry transaction in ahb and how master again get the access of bus. means how arbiter do the arbitration in this case? Regards, Tauqueer
Hi all..... this may be sill but.... Is CAN Compatible with amba-ahb.....? Thanks
Hello, I am working on an SOC with ARM. Project uses amba ahb bus. I have understood the ahb protocol. The testbench is written for complete SOC by writing code for ARM processor. I would like to know if there is any book on SOC design, verification, etc Aspire
as per the amba protocol NO .. but you can always modify it according to your needs. ya if u have multiple masters an arbiter is reqd and bridge complexity will increase. rgds