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i am doing a project on amba-ahb interface with the referance amba specification 2.0.can any body help me to get the source in uvm(slave side).
i am doing a project on amba-ahb interface with the referance amba specification 2.0.can any body help me to get the source in uvm.
Hi. As I know, We can make the bus matrix by using like NIC501 or something like tools. My question is that how can we verify the bus matrix? and what kinds of methodologies are existed to verify the bus what I made? Practically, I want to know that how to do this in Practically. Does any help this?
what is the major difference between verilog HDL and VHDL???? Which is best in designing the amba ahb, ASB,APB,AXI????? The biggest difference is VHDL's a strongly typed language and is significantly more verbose than Verilog. Either language will work well at implementing any if those bus protocols. Both lan
Hi, Most of the Design (SoC), the APB bus is used for register configuration. For bulk data transfer (eg: Video, EMAC) in amba we are using ahb or AXI. AXI is better than ahb.
There is a complete amba bus specification here: . Enjoy your design work!
I have read that amba ahb bus bandwidth (in bps) is 16 times clock frequency. Is it true? I read this in one of the ppt presentation downloaded from net. I want someone to confirm this. If this is true then if clock frequency is 25MHz then can I assume bus bandwidth to be 400Mbps for my amba (...)
Hi, I am confused with concept of burst transfer type related to amba ahb protocol. (1) If I am using 32 bit data bus then can size of my transfer i.e HSIZE exceed 32 bit? (2)What does 8 beat burst mean and what is maximum transfer size of my data in a burst if my bus width is 32 bit? Please explain me with an (...)
Hi, (1) How to determine number of bus cycle for read operation/write operation for amba ahb protocol. If I say bus cycle required for read /write is 4T states, then is it appropriate to say that for any amount of transfer on the bus the number of T states required is 4? (2) Does clock frequency is (...)
Hi, I am implementing arbiter module for amba ahb protocol for real time masters in verilog HDL. I want to know what value should I specify for HCLK signal. And what value should I consider for as my bus speed/bus bandwidth/bus rate? At least suggest me the source from where I can get this information. (...)
Hi; I am implementing arbiter module for amba ahb protocol in verilog HDL. For that I am considering real time masters having constraints in terms of deadline and service cycle. Now I am stuck at a point and want to know how the master convey this constraints to arbiter so that the arbiter will do the scheduling and grant the bus to one (...)
how do i find the data rate of the amba ahb , e.g if i have a clk of 200Mhz and use a data bus of 16bits. does it mean data rate = 200Mhz x 16bits .. how does burst play its role that's because i want to calculate FIFO length and i have 1mbps data going out at the other end - - - Updated - - -
hi guys, i have to do some calculations of how to handle the ahb bus bridge (connecting 1Ghz ARM and WLAN) , e.g i have to make a formula ( or excel sheet) for the wlan speed to bridge clock speed , e,g if i connect a 11Mbps wlan through a bridge to this ahb bus operated at 1Ghz( although it would also spare time for other (...)
i am doing a project on amba-ahb interface with the referance amba specification 2.0 from ARM. can any body help me to get the source in vhdl.
Hello everyone I have a question about amba ahb bus. I wanted to know if there are any similarities between the burst and split operations in amba ahb. I am aware of the differences but wonder if there are any similarities. Thanks in advance
Hi anbuonlymevlsi, As nisshith said, for a 4 bit ALU there is no need of any pipeline mechanism. Here is an example where we can insert a pipeline mechanisms. Have you heard about the ARM's amba ahb protocol, in that protocol there is a pipeline mechanism. There is a shared Address bus for read and write operation. So if we are performing a (...)
Hi all... Is anyone know how to calculate the through put of amba AXI or ahb buses... Means if i am transferring a 32 bit 16 Burst transfer through the AXI bus at 96MHz, then what will be the data through put of the transfer... Thanks in Advance....
Hi I have a question about opencores pci to wishbone bridge. In the test bench, the designers have set the pci clock period to 30ns (33 MHz) and similarly set the clock period of wishbone clock to 10ns (100 MHz) to test it. From this it makes sense because pci bus has a frequency of 33 MHz and wishbone bus has a frequency of 100 MHz. But i
Hi, Here's a tutorial presentation I had created for ahb bus training at my office. I've kinda put in only the relevant info need so that by the time you're through with it you will know at least most of the ahb bus details. Hope its useful! Thx
Hello, I have a question about a master to slave transfer on an ahb-lite bus. Suppose, an ahb-lite master initiates a transfer to an ahb-lite slave. If the slave can respond at once, everything goes fine. But if it takes the slave many cycles to do the job the slave must issue an HREADY='0' for as long as it's (...)
Hello people, I'm in the process of learning about ARM's ahb amba bus. My goal is to integrate existing VHDL designs on a single SOC's. I've read the amba 2.0 specs and there're quite a few things that aren't clear to me. First question: How many addresses does a single ahb slave have? The (...)
Hello everybody, i am new in Hardware design have a project in designing an AXI bus in VHDL and testbench in SystemC (Co-verification). I read some documentation and have understood how it works, now could some experienced persons tell me which are the steps i should follow, for example what are the different VHDL entities i will need (Channels,
I hope you get it in amba bus specification easily
Hi I have a naive question about amba bus protocols If there is ahb bus on one side (say left hand side) and there is APB bus on the other side, then you need a bridge. The question is do you need ahb2Apb bridge or Apb2ahb bridge or both In which case, i need only one (...)
Hi friends, I have been working very very hard for the past few days on the arbiter part of the amba ahb bus architecture. I am using a fixed priority algorithm for allocating grant to the bus master. I tried simulating the arbiter verilog code on modelsim with the testbench that I wrote. I was very disappointed. :cry: (...)
Hi all, I have some difficulty by understanding the reason why only one master can own the bus system at the time even if another master do not want to access the same target which responds the first master request. which penalty shall the bus to face if it is suitable to deal with this option? Thanks Mido
I am not very sure about amba , but in i2C one can access only one slave per master at a time. In amba ahb i believe the same case because unless one slave free the the data line the data can not be sent/receive at an instance. maybe you should understand amba bus to answer this question...
amba ahb can eventually support a maximum of 16 co processors maximum.... Since 4 lines are used to communicate with external devices and other lines are dedicated to interact with the internal peripherals..... only for that purpose amba architecture was restricted to ARM7 and later processors were developed with amba (...)
the amba clock could equal to the clock system.
Hi Guys I am familiar with amba ahb ,wishbone etc(On chip buses) buses and now for my project I am going to use PCI. Can you please give me comparison of both (PCI and amba) ie Can we use PCI as on chip bus if not whats reason +++ Thanks Tassadaq Hussain
Hi Friends, am working on amba ahb protocols , any one is there who is completed there ahb design ,i need to discuss my doubts and clarify it. Thanks and Regards, Kanimozhi.M
Hi Friends, I need amba ahb/AXI bus model in C/C++/SystemC. If someone is having, please mail me : udit.vlsi@gmail.com. Thanks in advance. Thanks & Regards, Udit Kumar
ARM uses amba as main bus. If you use amba you can find useful stuff at: This project demonstrates an easy way to create amba masters and slaves. It includes an ahb master, ahb slave, APB master and APB slave... ahb monitor:
PLS SEND THE VERILOG CODE
Because amba bus is a combination of 3 different bus. 1. ASB Advanced System bus. 2. APB Advanced Peripheral bus. 3. ahb Advanced High Performance bus.
here's the amba ahb spec, u can easily found it by google around. try read the document, it should be helpfull.
Hi Can any body tell my what is split and retry transaction in ahb and how master again get the access of bus. means how arbiter do the arbitration in this case? Regards, Tauqueer
amba.........what is this..........what does this do........ i would like to know these in really short notes............ thanks
Hi everyone...... could someone explain me in detail the following "The Advanced Microcontroller bus Architecture(amba)specification defines an ONCHIP Communications standard for designing high-performance embedded microcontrollers........." wht does ONCHIP Communications Standard refers to..... thanks
Hi all..... this may be sill but.... Is CAN Compatible with amba-ahb.....? Thanks
where do we configure the peripherals attached to an amba ahb bus............... like one way is to to it in the HDL code is there any other way out to identify the peripherals connected to a bus or provide the information to the CPU for a memory mapped system.............or if u can then provide some knowledge about memory (...)
Could someone give me a detail explain? I read the amba spec, but still cannot understand.
Hi I have a problem with Hready. When I try to access the registers of a slave on the ahb bus I get a bus error. after probing the ahb signals I notice that Hready comming out from this slave is always low. I could access other ahb slaves and APB slaves on the bus? What dose that (...)
Hello all, Currently iam working on ahb Master interface design. I have some doubt on retry and split. My burst length is 8. After sending the 5th beat , iam receving retry/split from the slave. If i get the bus grant again , i need to start the transfer from the begining or from the 5th beat. Regards Nivaz
Three distinct buses are defined within the amba specification: ? the Advanced High-performance bus (ahb) ? the Advanced System bus (ASB) ? the Advanced Peripheral bus (APB). The ahb acts as the high-performance system backbone bus. ahb (...)
Hello, I am working on an SOC with ARM. Project uses amba ahb bus. I have understood the ahb protocol. The testbench is written for complete SOC by writing code for ARM processor. I would like to know if there is any book on SOC design, verification, etc Aspire
I have doubt regarding SPLIT and RETRY. * Does the slave respond with SPLIT & RETRY for Data write i.e data from master to slave? * If a master wants to do locked transfer which crosses 1K address boundary, for sure arbiter will remove the grant when master reaches 1K boundary. Will the arbiter regrant the bus to the same master even with ot
i am doing a project on amba-ahb interface with the referance amba specification 2.0 from ARM.can any body help me to get the source in vhdl/verilog. Hi, If you want a ahb Master Verilog Model, i can provide it to you! My group has utilized to debug the whole system! Now, the hardware verification has reached an end. a
Hi, My boss gave me an issue to get information about amba bus Verifiaction tools subject. So I have a few question: 1. Does anybody use this kind of tools ? I mean for example : ACT by Synoposys or SolidPC by Saros. (I would like to test ahb and AXI bus version) 2. Maybe anybody knows the better tools ? (But they (...)
Dear All, I have a design that contains ARM processor and FPGA... inside the FPGA there is a single master amba bus connection with the ARM as the master of it... so I have an ARM wrapper to connect the ARM to the ahb bus.... The ARM and the FPGA are both mounted on the same board which contains crystal oscilator to (...)