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63 Threads found on edaboard.com: And Circuit Design Vhdl
D. Perry. vhdl (3rd Edition, Mc. Graw-Hill, ISBN 0-07-049436-3). Z. Navabi. vhdl (2nd Edition, Mc. Graw-Hill, ISBN 0-07-046479-0). V.A. Pedroni. circuit design with vhdl (MIT Press, ISBN 0-262-16224-5). i need soft copies of thes books
hi every body I'm new in FPGA. but I've worked on Altium pcb and schematic a lot. but not the FPGA design yet. I know that it's possible to simulate an FPGA design in Altium but still have some simple questions: Would it be possible to simulate an FPGA with peripheral circuits? I mean another parts like digital ICs or (...)
No issue after I added a fa.vhd file to the design. You do know this is a very large combinational circuit. Using Vivado it ends up with >60 levels of logic (LUTs) from a_in to y. Of course I didn't add any constraints to try and improve the timing. e.g. 105366 Regards
sir,for what purpose we combine xilinx(vhdl/veilog) with matlab for particular image processing project. this is for speed or accuracy ?
can anyone pls help me how to design a double tail comparator in vhdl using modelsim software......actually im feeling very difficult in designing a each and every transistor in that double tail comparator circuit....
Hi, Register-transfer-level (RTL) abstraction is used in hardware description languages (HDLs) like Verilog and vhdl to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. design at the RTL level is typical practice in modern (...)
Hi, I am looking to design a parallel squarer circuit using vhdl and try optimizing interconnections to see if it can be more efiicient. The design template Im looking to follow is based on this
I want to get back to circuit design and decided to practice some of the problems. I'm using vhdl for coding. The problem looked simple to me, but to my surprise I was not able to solve it. Please bear in mind that it is not a homework problem. I work full time and simply want to do more of (...)
For clarity, you should tell about the synthesis tool and imported libraries.
Hi! I have done my Masters in Embedded Digital Systems from University of Sussex, United Kingdom. Passed out Sep 2012. My skill set include: FPGA design with vhdl, RTL design, synthesis and implementation ( have done a project in it), PCB design, Signal processing in MATLAB and Image (...)
Hi abdullah, tnx ,but I want to design a circuit and then simulate by Hspice.
I'm new to vhdl shared variable I tried loops and even recursive functions Let me guess, you're a software programmer? the above quotes lead me to believe this, and also tell me you're probably doing it all wrong. Have you drawn the circuit you want for this design before you even wrote a single lette
Hi Dear all How can I calculate the maximum element of a NxN matrix? I know how to find it by matlab or C or even by using "for..loop" and "if" statements in vhdl but I am not sure that, Does this kind of coding synthesisable or not? ( I mean I didn't design a circuit for it before start to write the code). So what is your (...)
There's all sorts of avenues and some long-winded answers that could come off of your question... But personally I would say yes, aim to learn (in this order): (1) Digital circuit design (2) vhdl for digital circuit design and for testbenching (separate (...)
Logic gates (especially large scale) can be designed in vhdl (or Verilog) and then imported into Cadence for example. Cadence will allow you to simulate with these models. For transistor level design (e.g. one inverter), you can use Cadence and a control language (e.g. Eldo).
Not really that interesting, or that useful, and never a situation Ive ever seen anyone complain about. Afaik you cannot do it in any HDL (I dont think you can call half a function in C either!) If you think of the design using the simile of circuit components, how would you expect to connect half a chip on one board and (...)
I had installed FEL earlier. "Fedora Electronic Lab" targets mainly the Micro-Nano Electronic Engineering field. It introduces: * a collection of Perl modules to extend Verilog and vhdl support. * tools for Application-Specific Integrated circuit (ASIC) design Flow process. * extra standard cell libraries (...)
circuit design with vhdl by Volnei . Pedroni I have this book and at least my edition have a big problem. It uses the non-standard libraries std_logic_arith etc. There is no reason for a beginner to learn those libraries. First learn the numeric_std library, so it will become natural to you. It is (...)
first of all, you commented out the J and K inputs!
i have 3 questions 1-for the design of sequential circuit(mentioned at ch.8 in RTL book) it explain that the seq circuit is designed by (next_state logic , seq circuit and output logic). this design mean that the block is operate all time but only the output is (...)
Hi..... I want to design a TRANSMISSION LINE in vhdl-AMS in SMASH. Can anyone help me? I had tried it in hAMSter tool using partial differential equations of LC circuit and got result but i have to do a long coding in this tool and have some less facility. thank you in advance................
I'm currently trying to learn how to use TetraMAX to generate test patterns, but have come across a problem when using vhdl. I have a simple benchmark circuit implemented in both vhdl and Verilog. When I run the Verilog design, TetraMAX creates a list of 50 faults, but when I use the vhdl (...)
A vhdl core mean a circuit or an ip described in vhdl. Yes you can write and some design houses sell their cores as vhdl models. There are a lot of protection methods and tool vendors. -- Amr
You know this is a simple question that any student should know? IF you think about it or do a search on the web you will find something and LEARN something in that process.
RTL is Register Transfer Level. RTL is a way of describing the operation of a synchronous digital circuits. n RTL design, a circuit's behavior is defined in terms of the flow of signals (or transfer of data) between registers and operators. Register transfer level abstraction is used in vhdl (...)
hello all, i have posted the schematic of drilling mechanism can anyone explain whats the circuit. i mean the symbols... what is ls1 ls2 ls3 ans sc4 sc1 sc 2 sc3 and what is start and "in position" and what is A soln B soln at right side of circuit. . how to design this (...)
hi i want to use pass transistor to design 4 to 1 mux and use vhdl hat somebody help me? thanks
Hi, I need to design a circuit using 2 positive edge-triggered t flip flops w/synchronous active high reset and CE. The inputs that I am given are INPUT, CLR and CLK and the outputs are Q0, Q1 and RCO. Here's what I have for the code so far: entity sequential is Port ( INPUT : in
I can't finish my code, there's something I'm missing: Using vhdl, design a circuit which will produce 1. Q = INT(Y/X) and R = Remainder of Y/X 2. Let Y be a 8-bit unsigned, and X=4-bit unsigned. 3. Your design should have an error signal (active high) if X=0. This is my code: -- (...)
Use calculator and multiply the two signals if you are going to compare it with any other multiplier circuit or so. if not and you are going to use it as a part of circuit design then use Verilog/vhdl - AMS models if you can make one.
Dear all, I am using C@dence to do my circuit design. Now, I have digital control block and RF circuit. What simulator or method could I use in C@dence platform in order to simulate the mixed signal design? Thanks wccheng
Hello everybody, My project is design IC Controller for three-phase inverter using FPGA and vhdl coding. Now Im asked to design an interface circuit using optoisolator. I want to know the reason why I've to use optoisolator? and can I have sample of interface circuit (...)
I don't know if maxplus can do that. Quartus II surely can and can also import your Maxplus2 code, so switch to quartus II, import your project and convert it from there.
hi,, is it possible to design pll(VCO part) using cadence virtuoso tool and then extract a verilog code of the VCO design for a fpga implementation... i read in 1 paper the same way a vco design was done and then a vhdl code was extracted from some analog design tool for (...)
D. Perry. vhdl (3rd Edition, Mc. Graw-Hill, ISBN 0-07-049436-3). Z. Navabi. vhdl (2nd Edition, Mc. Graw-Hill, ISBN 0-07-046479-0). V.A. Pedroni. circuit design with vhdl (MIT Press, ISBN 0-262-16224-5). i need soft copies of thes books
Digital Logic and Microprocessor design using vhdl by ENoch
I think u are not asking about total correlation block. If u want only magnitude block calculation as u said "sqr and sqrt" ,u can use approximation circuit for ur magnitude block to reduce area. Don't forget to press help button.
i began digital design. i need some good digital design simulation software for simple designs for now ( like bcd to decimal decoder using 74138 and 7404 and 7421 ) i need your advices and cooments :D thanx
Simply FPGA is a programmable asic in which you can implement your logic circuit. To do that you should know one of hardware languages such as vhdl or verilog, and also you should be able to work with its related softwares and compilers such as modelsim for simulating, ISE or Quartus for implementing your design.
I have some vhdl which is just a PWM generator. I would like to add this vhdl in a A/D circuit in PSPICE and test it with some different value resistors and capacitors for a low-pass filter for the output... Basically to create a 1-bit DAC. But i have no idea how to do this at all. Okay sorry to burst (...)
Hi friends, I am searching for a job in FPGA/ASIC domain. My interest is basically in the field of VLSI design and wants to pursue my career in the same. I have good knowledge of Analog,Digital design, CMOS circuit design and Hardware Description Languages (Verilog and (...)
Learn an HDL such as Verilog or vhdl. design your circuit using that HDL. Choose a CPLD that's big enough to hold your design. Compile and synthesize your HDL using software from the CPLD manufacturer. Download the configuration file into the CPLD.
circuit design with vhdl Good book and easy to start Link : or Password: ebooksatkoobe
vhdl here although it is strongly typed, its constructs and features for high-level modeling are more that those of Verilog there are also many ways to model the same circuit also, specially those with large hierarchical structures also, the library concept is in vhdl only not in Verilog which gives flexibility to (...)
Yes. circuit design With vhdl is a good book. I prefer books with many examples which can help me to understand fundamental concepts and connect these concepts to real applications.
Hi, I want to know whether the book "Digital Systems design with vhdl and Synthesis" by KC Chang, is available as a softcopy. Also, i want the soft copies of best books for vhdl. Where can i find them? I tried using search option. But when i am trying to open the page thru URL, it is showing msg as the page is (...)
buy yourself an FPGA development board, play with it... refer to the various reference designs on the internet, try it out... since u are a fpga design engineer... u will master it after few years... :P anyway, read a few books like <vhdl Programming by Example 4th Ed - McGraw Hill> and <circuit (...)
welcome to the world of FPGAs. there are a number of books that you should download from here. one is the design Warrior's Guide to FPGAs by Maxfield. and you should download the Verilog HDL book by Samir Palintkar or if you want to start with vhdl, then circuit design with vhdl (MIT Press) (...)
I wonder if anyone has the 1. Instructor's Manual and 2. Source Code for the book circuit design with vhdl Volnei A. Pedroni which can be obtained from I will be glad if you could share it with me. I look forward to receiving these fil
It depends what is ur objective. If you want to do that in a FPGA, then write the vhdl code describing this behavior. If you want to build with discrete logic, u need to find the equation of each output. Anyhow, here the design approach I would use: 1) Write the state machine There are 2 inputs and u need to think the different (...)