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Hi guys! When i copy the layout of the triple well mosfet nfet33tw from the pdk (ibm 130nm) as it is and ran lvs on this single device without any modification or connections, the calibre is unable to recognize the device. Am i missing anything here? Thanks
Hi Everyone, I am struggling with using the Floorplanning tools in Layout XL to automatically place my IO cells. I have created a very simple schematic and layout cell in which I have instantiated 4 IOs - VDD, VSS, DVDD, and DVSS. The cells have been provided by ARM (...)
I was planning on upgrading my old laptop , from a pentium mmx to a pentium II, I have even bought the pentium II processor for it, But this is a weird issue for this Laptop, and i have no idea why ibm would do this, this laptop could come with a pentium mmx or a pentium II , this is where the issue, is (...)
I see nobody responding so I'll suggest that while you're waiting, you find a copy of the design kit docs and find the mask levels descriptions and groundrules that pertain to this layer. That ought to be what anybody who uses the process, would be regurgitating on your behalf.
Hi all i want ask about how I have access to design kits from TSMC, BSIM,ibm, and STM (65nm, 90nm, 0.13um, 0.18um)the aging model file.
Found another problem, my project uses functions deg2rad, angle, dB(S) in Qucs In QucsStudio deg2rad and angle gives "undefined/unknown function" error, while dB(S) seems give incorrect results.
We now have two problems that are related to temperature. Firstly, according to the BSIM4's model, we should have linear equation between threshold voltage and temperature, while when we simulate the NMOS, it shows totally linear, but in PMOS it shows some non-linearity. I wonder is this temperature non-linearity is caused by which (...)
Hi everyone, I am new on this forum and relatively new on analog design. I finished layout design of my low-voltage current mirror (100:1). I used 2D common centroid for better matching. After extraction spectre gave me Vth=335mV (346mV in schematic) for my unity MOSFET TN3. Everything else is same. What is mechanism behind this (...)
I tried to find the flatband voltage of the technology I use in the documentation of the technology (ibm 130nm) but it seems that this information is not provided -- is there a way to get the neceassary information somewhere (spice files)?
Hello, We have a design requirement for a Power PC based ASIC. Due to our existing relations with ASIC foundries, we can't directly license it from ibm/Global foundaries. Could you please suggest who can provide soft cores for PPC405 and its surrounding sub systems ( like PLB , OPB, EPB etc components) I have (...)
This link has a file with both the scan codes and ASCII values in hex for the keys on an ibm PC
Do you need to do that? Some foundries insist to do it in their CAD group, not trusting the dumb customer. See if any of the libraries (like the one with the pads in it) has a "scribe" or "die seal" PCell? No way would any foundry want you to free-hand it, there's a standard they want to (...)
Why don't you grep around in the PDK until you find these keywords, and then make sure the files they are found in, are in the include-chain?
Hi everyone, I am using ibm 130nm cmrf8sf PDK. I made a simple inverter and performed DRC, LVS, PEX with Calibre. The DRC and LVS work well, but there is a PEX error shown as follows: "error: Could not find pin mapping for terminal sub of cell (cmrf8sf devicepad symbol). (...)
hello, i'm new with analog design with this pack of ibm and i have a trouble that i can't solve. I'm doing a simple inverter with Mentor Graphics in this technology and in the schematic i put the subc for the NMOS, but i don't have a contact for the substrate of the PMOS, (...)
Has anyone used the process of LFOUNDRY in Germany ? How good is this company and is it stable ?
Hello, I've designed a digital core with ARM front end standard cell and an analog circuit in cadence Virtuoso in ibm 130nm. I wanted to do the mixed mode simulations in virtuoso. However, the ARM front end standard (...)
Hi, I am doing a layout of a simple common-centroid differential pair with multipliers and fingers using ibm 130nm cmrf8sf. DRC runs fine. But i get malformed device error: *ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device. Any ideas on how to solve this? Thanks.
You should characterize your devices before using them. Run the id vs vds curves for a bunch of different W and L. Find out how lambda varies.
Hi All I am familiar that MIM cap can be placed on SUB or NW. In ibm 0.18 they give a third option for the backplate, which is BB layer. Does anybody know what is this BB layer used for and any pros and cons? Thanks!
Hello, I am using cadence dc analysis. From print-> dc operating point. I get such a result, from which I even can't find 'vdsat' and 'region'. Any one knows which one is the saturated vds parameter(perhaps vdss) , and how to add 'region' in the display list. The reason is because (...)
Hello everyone First i have to provide this information: 1- i have instaled the latest version of Intel MPI and platform MPI of ibm. 2- i have to use one of them through Ansys HFSS 15 x64 which is a EM-software in a GigE network. 3- HFSS dont have any problem with discrit processes (for ex. 15 paralel process in (...)
Hi every one, I want to design a peak detector in my AGC circuit which be compared with reference voltage and produce the control voltage of VGA.the peak detector should be linear with input magnitude I couldn't find any reasonable circuit to satisfy my idea. could you please help me... with best regards matin
VDD! and GND! are the power and ground pins. Seems UPPER and lower case letters will be distinguished: 107783
1.2K pullup load and 10uA tail current means a 120mV signal swing, stop-to-stop. That is not much. and 1.2K times a tenth of a picofarad would account for your 100pS-range risetime. If you want to drive any wireload at all, you will want to lower the load resistor value (...)
Hi, I'm currently completing my first layout, and getting errors on all my pins. When I run LVS I am getting an error on each saying "Unbound Pin". I have simply placed the pins that were automatically generated in layout XL (when I generated the layout from schematic) within the appropriate metal layer. When I purposefully place (...)
Hi, I am facing the same issue with extraction using Calibre and ibm130nm. Is there a way to fix it? Any help is greatly appreciated. Thanks!!
hello, if your printer follow EPSON ESC sequence ..example of use and document for standard ESC commandes void MHardcopy() { int yt,x,y,t,k; int my; int Dx; byte Hi,Lo; byte pr; StateLP(); if (etatLP==1) { my=596; (...)
Generally the PDK already includes the rules for Calibre DRC and LVS, and instructions on how to run using its setup and file names. If you are asking how to modify the LVS settings, the easiest way is Calibre Interactive - LVS. To invoke (...)
I am going through MOSIS and I find two different spice models (BSIM4) for 90nm (hopefully for two different specialized processes). and these have very differe
layout and schematic screenshot please.
Hi everyone What is the types of storage used in ibm company and what is the against of it for EMC company ?? What is the storage types for ibm company ??
Hello there, In ibm CMOS7RF 0.18um PDK, we need to put a "subc" in the schematic and put a "sxcut" layer in layout in order to pass the LVS. But in the digital standard library, the schematic views of the standard cell (...)
Strongly depends on the capacitance of associated output drivers and the ESD protection. I'd recommend to calculate with 10pF (w.c.), 5pF (typ.), and 1pF (best case).
hello I intend to use PTM models of 32nm for LNA design. I have access to ibm 130nm techfiles only. Please correct me if I am wrong "I understand that for designing LNA, I must have inductors and capacitors of the same 32nm technology" (...)
Look for an alternate PDK mos primitive that isn't "digital" or "rf" - these will tend to be fixed length in the interests of modeling edgy performance. There ought however to be an "analog" or "i/o" transistor type with parameterized L and not-as-good high speed modeling. You'd think.
Don't think it's a problem of the number of pins, and in any case PSUB concerns GND, not VDD. Perhaps this thread might help. It concerns an ibm process, however, so their subc should correspond to your PSUB.
An nwell resistor should (of course) sit in an nwell. Try and connect the 3rd terminal to the nwell tap, and the latter one to VDD (by metal1).
I'm using ARM IP's SRAM memory compiler for ibm 130nm. It is only characterized for nominal voltage and some worst case corners. I'd like to scale VDD significantly since I only need a fraction of its specified performance at full voltage. I do have netlists and full layout (...)
Where can I find some resources with examples or tutorials that include RFIC laout examples to get started with ibm BiCMOS process using the Cadence design tools? My only experience has been with the schematic and circuit simulation. Thanks!
Guess you know you can get these rules files only by signing an NDA. You could also try and get the ibm 130nm PDK from the University of Texas at Dallas.
Hi, Friends: I'm doing a project with lot of on-chip SRAMs. and we want to transfer to ibm MRAM process. I want to know: the foundary manufacture cost difference between TSMC 90nm process and ibm MRAM process at 90nm. Such as the mask cost (...)
Hi all, I am a fairly new user using calibre tool for DRC error check. I have not finalized my design and want to perform DRC check on the blocks. Suppose an inverter.. I saw from earlier threads that there is a way to avoid chip edge related error by choosing the cell switch on. Can someone please elaborate on this? Where can I find the (...)
Hello, I have done quite a few boards using Orcad Schematic Capture and Orcad PCB Layout for ibm over a 10 year period. I have also worked with board houses to have the boards fabricated. I have also built up many boards myself. I am looking for remote design work or local work in the NC area. Please email me or PM me if you (...)
Hello, I am with problems to run Assura and DRC and LVS verifications. The Design kit that is being used is the ibm8rf-DM 130n. Before to start the design some configurations to setup the DK were done ( ). To test Assura (...)
and produce an audio signal ready to be analyzed by audio DSP techniques on the PC? What is the dynamic range of your PC's audio input?
Hi i have designed CML D latch using tanner 250nm tools inbuilt libraries. To proceed for a frequency divider(/3 & /2) using this latch, i need to use ibm so what will be the length and width to fix or how to find length and width generally for technology file selection. (...)
I have lots of electronic tubes from my father and uncle, some of them are very rare and expensive today, but I dont have will to struggle with these. We should accept technology improvements and to move on. I have first (...)
Hi all, I import a GDSII file in ibm 7RF technology and while streaming in I specified the LayerMap file (cmrf7sf.layermap) but while I try to do Calibre DRC it shows me the following error message: ibmPdkrunCalibre("DRC") Starting DRC on top cell in window:3... Unable to find valid layer mapping (...)
Hi, I am designing a circuit that uses an isolated P-well in ibm 130 nm. To create the isolated Pwell, I used a PI layer and a N-well layer surrounding PI. Using a PI guard ring, each of the contacts(p+ contact for isolated p-well, n+ contact for n-well and p+ contact for (...)

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