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460 Threads found on edaboard.com: And Nor
Can I use the following to find out the internal source resistance of the signal generator? I use a DC voltage source driving the signal generantor and 10K ohm resistor in series. Base on the current and voltage drop across the 10K ohm then I can find out how much the source resistance of the signal
Hi i have a parallel 16bit nor flash device implemented in a project unfortunately it is getting obsolete. I want to replace it with a similar device. I don't know much information about the code currently running on the board. While comparing the nearest part i could find, i understand that the page size for each is o JS28F128M29EWHF
I am synthesizing a cholesky decomposition algorithm using verilog and synopsys DC. I've also written a customized cell library, which contains the following cell: and OR XOR IV Nand nor Xnor DFF MUX It was sufficient for me to compile functions like Division and Sqrt.
Hello, As we are following 50Ohm impedance in single ended signals and 100Ohm impedance differential signals in routing. My question is in routing differential like Clock+ and Clock- we follow 100Ohm differential impedance. Is it necessary to follow 50Ohm for individual signals? Means we need to follow 50Ohm for Clock+ and 50Ohm for (...)
hi everyone, can you help me? i write this code, a pulse with period 300ms. then it delay 200ms. but when i measure, width pulse change, i got 0.001ms and 0.0001ns // VerilogA for baitap, ngovaox1, veriloga `include "constants.vams" `include "disciplines.vams" module ngovaox1(plus2,minus); output plus2, minus; electrical
Hi, The following circuit to delay a clock signal appears on a few forum discussions (can't find them now after re-searching, so unable to post the links): 136303 It works in a simulator, with a little tweaking, but didn't work on a breadboard at 2Hz, 3, 16, 32, 64, etc., up to 16.7kHz, and changing passive components
Hi, I'm using orcad capture CIS for schematic design, when i move or drag components or part name it shows warning due to that i'm not able to arrange the components properly. But i can able to move by cut and paste. Kindly give a suggestion to solve the issue by any settings. h
I can able to design Full adder and Full Subtractor using 12 nor gates. But I want to realize Full adder and Full subtractor by using Minimum number of nor gates i.e 9 nor gates. Please explain this Realization
You are driving CART1_B and CART2_B by the instance LC_CAL and the process, you commented out the assignments in the reset branch but left the assignments in later branches.
LCD Display is Working Well . When I POWER OFF the microcontroller and LCD DISPLAY also OFF , When I tried to power ON AFTER 3 Seconds means MICROCONTROLLER and LCD WORKING WELL, but when I POWER ON THE DEVICE suddenly after 1 seconds or below or repeatedly , the LCD DISPLAY SCRAMBLES. afterwards I will POWER OFF the device and I Tried to (...)
Hi I got cadence IC616 and MMSIM13 from and installed it successfully and also applyed the patch successfully but it does not have license.dat file neither in IC616/share/license nor in MMSIM13/share/license I request you pls share the license file or email me
We were doing a school project, attempting to create binary data storage. In the process of putting the circuit together, we discovered that moving closer or farther from the circuit affects the brightness of the LED. When we disconnected the button from the nor integrated circuit, the circuit got extremely hot and burnt out. We also recreated this
I want to know in CAN and LIN which one full duplex and half duplex
Hello there. I have one question that buggs me. Why for some ICs, you need to connect the A/B logic gate inputs to the ground (-) through a rezistor for the output to come out right, and for some others you can just plug the (+) rail into the input and you get the right output? Thanks.
I am trying to design a simple loop of communication system between pc and FPGA virtex 5, for this purpose I interfaced a BRAM with uart module, I am using VHDL as the hardware description language, the memory used is a 16 byte simple dual port BRAM ram with a width of 8-bits; is supposed to read 16 bytes of data from a terminal software and then s
Hello, This datasheet is extremely slow to respond to scroll up and down commands, do you know why?
I need a latch to work as follows 1) two inputs, one output 2) upon a short logical high on input_1, output goes high and stays high Any other logic highs will make the output high 3) upon a short logical high on input_2, output goes low. Any other logic highs keep low I am ok with simple logic gates but I
There isn't any model for such circuits for neither ADS nor any.Its' characteristics are defined and you take it, use it.
Hi. I have a 12V PSU which I want to reduce to 4V 2A PSU. I have used a NPN power transistor (BD137) plus a 270Ω resistor and a 5V zener to make a regulator which gives me a 4.4V output which is still too high. Is it a good idea for me to just put a silicon rectifier of some sort in series with the regulator output to give me a further 0.6V
1. Difference between qualitative and quantitive analysis? If we want to perform these for any electronics circuit What i know is in qualitative, observe data is not measured and in quantitive analysis observed data is measured. 2. Difference between small signal and large signal analysis (example- for MOS)? What i know is small (...)
Hello there i have a problem with p spice and i dont know what to do with it since no actual error emerges. I am attaching a self explanatory immage, any help would be greatly apreciated130918
The ASIC synthesis tools like Cadence RTL Compiler will report static and dynamic power consumed in your design in the power reports. How does the tool calculate the dynamic power even without the switching information??
Hi, I would like to build the clock tree with Nand/nor gates. As we know these gates are universal gates, so we can build BUF/INV logic with these gates. If anyone of you have idea about this concept, please let me know. I don't bother about the performance, just I want to build the clock tree. I am trying to build with EDA tools present in m
hi bigdoggurru and aussie susan, i found out the problem, the problem was in the hardware the voltage in R/W pin of LCD was 1 V (neither 0 logic nor 1 logic)eventhough it was connected to ground through a resistor, now i connected that pin to ground stright and the voltage becomes zero (...)
Have someone ever used the LT3650? I have designed a circuit charging a 18650 battery. It works ok but the IC gets very hot (50C) at 12V input and over 65C at 28V. The IC has about 20mm? of copper on the bottom side and about 10mm? on the top side. Charging current is set to 1.5A. IC should have thermal shutdown but is this heating (...)
Hi, Anyone knows how to build a or/and/nor gate with VCVS in Hspice commond line( Hspice code)? The syntax is : Multi-Input Gates Exxx n+ n- gatetype(k) in1+ in1- ... ink+ ink- + x1,y1 ... x100,y100 But can anyone give me an example of two input OR gate? Y=A OR B. I d
Hello every one I have a project with PIC18F97J60 because of the ethernet communication capability in it, but I didn't found it in ISIS proteus and in microC for PIC also how can I add it to them, thank you.
I do not believe that you can sweep a component value with the AC Analysis in LTSpice Read about .STEP command
I was working on my project with logic, sequential and combinational ICs. and, wanted to test the 74LS10 3-input Nand gate and it wasn't working!! All other ICs are working, nor, 2-input Nand, counter, 555 timer. I've other 74LS10, if they all not working then I'd combine 2-input (...)
Hello, I need to interface a shared SRAM on Zynq FPGA . I saw in ug 585 manual and found that there are dedicated parallel SRAM/nor flash pins in the PS for SRAM interface. Alongside with this SRAM, I need to interface a QSPI nor flash. The problem is that few pins of the MIO are overlapping between the parallel SRAM and (...)
There is a postulate which says that there no exists magnetic field, nor electric field, but both walk together, which means that one generate other and vice-versa. I admit that never thought about this question, but without googling anything, in a brainstorm I would dare to say that those ?free electrons? exists and perhaps should be (...)
Hi, either me or you has to read the datasheet. I prefer that you read it. ;-) From your first post i assume VCC = 5V. Usually there are shortcuts. (open the datasheet as pdf, go to the "electrical operating specifications" section.) Do a search on: V_OL = Voltage output low V_OH = Voltage output high I_OL = output sink current I_OH = output sou
That has to be the most complicated and convoluted keypad code ever written. Make life easy for yourself, put the rows on adjacent pins and the columns on adjacent pins, then use the shift operators to scan the keys. Brian.
Why would anybody want to simulate an LED that has three different LEDs in it? A school kid? Simply buy one that has an English datasheet and make a circuit for its spec's. Look at its ranges of forward voltages for its three LEDs. If all three colors are lighted (lit?) then observe its maximum heating rating.
Initially I would be tempted to define the maximum operating frequency by the critical path, as being the propagation time of each one of the three nor gates, added to the propagation time of the and gate. However, as there is a symmetry in the circuit, in theory one side should balance the delay of the other, but I believe that the maximum frequ
You would just need a toggle Flip Flop, a one shot and two active low switches with Relay coil common to V+. Single push button goes to one shot which debounces push button and drives FF Clock input in /2 mode or toggle mode ( D=Qbar) Q and one shot = Gate drive 1 Qnot nor one shot = Gate drive 2 FETs would be N (...)
Q1-3: The circuit doesn't correspond to a clean toplogy, it has two feedback pathes and is neither clearly CB nor CE. Don't expect simple answers. Q4: Quiescent current is related to transmitter range. C945 has however a wide range of current gain, so actually achieved transistor current can be quite different. Suggest to try yourself by varying t
while design a nor3A ie a 3 input nor with A input inverted. we have two ways build a two stage nor3A OR build a 3 stage and3BC(apply demorgans to nor3A ) so while computing the delays i found that 3 stage design was faster. so i got a question here is that how is it faster? and what (...)
while design a nor3A ie a 3 input nor with A input inverted. we have two ways build a two stage nor3A OR build a 3 stage and3BC(apply demorgans to nor3A ) so while computing the delays i found that 3 stage design was faster. so i got a question here is that how is it faster? and what (...)
Hi, we can neither check your hardware nor check your code, as long as you don´t post it. So I´ve googled and found a lot of "how to use GY80" guidelines. Did you read them? Please provide more information. Klaus
Put a 3V bulb or a white LED or an appropriate resistor between the 15 volt power supply and the relay coil. The COM pin probably has the better thermal conductivity to the relay coil.
you do not tell us how long the interconnecting transmission line is, nor how much amplitude ripple you can live with over a bandwidth. If they are really close, just hook one to the other. If they are far apart, you could add a series resistor at the mixer, and run 75 ohm line. if it is narrowband, you could just (...)
Not knowing your technology nor your DRC rules, I 'd assume: You have N_WELLs WITH DIFFERENT POTENTIAL in your layout. Seems - in your technology - that N-Wells have to be marked (e.g.) by a DNW_LV_MARK marking layer. But there must be different DNW_LV_MARK marking layer polygons for N_WELLs WITH DIFFERENT POTENTIAL. and these have
you don't say it is video or stills nor if it color or B/W nor resolution BUT if you need to do 1) and especially 3) as well you definitely can NOT use a wee micro-controller, you need a full-blown PC.
Hi guys, 1. I'm simulating 8 bit mips processor from CMOS VLSI DESIGN: 4th Edition. This is results that I obtained for Astro and VCS using Synopsys. I've no problem with Astro but for VCS simulation, at the first instruction, the result is ok but when it proceeds to second instruction, there is something which I not quite understand. Why the me
* If LiPo has I*t= 5.5Ah then energy storage is V* I*t = 25.9V*5.5Ah = 142Wh > x3600= 511,200 W-s= Joules By comparison your 9V primary battery is only 9V *0.6Ah *3600s/h =19,440 Joules Thus your LiPo ( ignoring charger type inefficiency ) will take 511,200/19,440=26 times longer charge time with 26x more energy st
Hi, I need some help. I have an HP8565A and I have no Frequency readout neither on the CRT nor on the LED readout. The problem started a few months ago when the LED readout started to flicker and display intermittent lighting of the segments. Now it just displays 0.0000 I checked the 10V reference and is within (...)
See the 74HC14 datsheet circuit. Essentially the inverters of the basic FF are replaced by Nand and nor gates.
I do not hold solder in my teeth nor with my toes. instead I fasten down the item I am soldering and hold the solder in one hand and the soldering iron in the other hand, or I fasten down the solder and hold the item to be soldered in one hand and the (...)
Your photo-diode is not a current nor a voltage source because it is reverse biased. Then light on it causes it to leak and become a resistance. Then it conducts some of its bias to the opamp input. A photo diode without bias is a tiny solar cell that does generate a voltage and a current.