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78 Threads found on edaboard.com: Assura Rcx
rcx was replaced by QRC. Before start the virtuoso set up variable export QRC_ENABLE_EXTRACTION=t With this variable You should see in assura menu the QRC extraction and it should works.
QRC is the replacement for assura rcx. It's based on the same technology, but has merged in the Fire & Ice cell-level extractor, uses common technology data, and QRC is the maintained and developed tool; assura rcx only lives on in legacy support mode. You need the LVS results, and additional data files produced from a (...)
If I remember correctly, assura extract the parasitic resistors and capacitors (like traces) and not the component values itself!
Hi msdarvishi, My TSMC kit does not support assura, only Calibre. DRC is strightforward : "runset" is not compulsory. In the kit installation directory, you should have a "Calibre" directory, with "drc", "lvs" and "rcx" subdirectories. Just load Calibre/drc/calibre.drc rule file for default DRC. After sucessfull DRC, you will able to save your con
Maybe I posted it before in the wrong section... Hi everybody, I'm trying to simulate the effects of my layout routing from the pads to the core of a mixed-signal ASIC. My idea was to hierarchical extract the whole layout and then simulate the connection parasitics with the subcells at schematic/functional level to make the process faster.
Dear all, A few months ago I started working with the TSMC 65nm (CRN65LP v1.7a) PDK provided by Europractice services. At present I'm testing the full design-flow (from the schematic level to the post-layout simulations) through some basic exercises. Does anyone know if the entire physical verification (DRC+LVS+rcx) is supported with Calibre
Hi, I am using assura rcx to carry out parasitic extraction of an inverter layout. Cadence icfb version I am using is IC5141USR1. The tool is extracting the layout successfully, but the extracted view shows NMOS and PMOS symbols in place of metal layers. Parasitics (resistors and capacitors) symbols are present in the extracted view, but it
@AMITH, In your rcx run window, you can find the run details the run details tab, you can find run directory and both sch_cap_ground as well as lay_cap_ground would be created by assura. If you cant find, you can create it by yourself. Thanks, Siva hi,siva actually I have faced the same problem that
Hi, I want to do parasitic extraction of an inverter design using assura rcx.Its a UMC180nm project. DRC and LVS are clean for this design. assura is version 3.1.6 on Linux. It can be serious bottleneck for the project undertaken. Getting following failure log upon running. (...)
Dear all, I wonder if the tsmc 65nm kits are compatible with assura DRC. Compatibility with assura LVS and assura rcx seems ensured, but I cannot made DRC work... In the assura directory of the kit, there is no drc.rul or similar one, whereas the "training" included in the PDK clearly mention the DRC (...)
Hi, I am using assura to extract layout (pdk: tsmc35). In the layout, I have a transistor with width of 19.5u and finger of 10, the total width is 195u. But in the av_extracted view, I check the property of that transistor, and find its size is w=19.5u and finger=1, m=1. Then i did post-layout simulation with this extracted view, that transistor do
Hi there, I need to incorporate a few custom designed transmission lines and inductors in to a TSMC 65nm tapeout. I found a document from another TSMC pdk about using assura ?blackboxcell option to do LVS and rcx. The basic procedure is that you copy n2port element into the PDK lib and name it as a new cell (for example n2port_d1). Then copy sy
Hello, I am just wondering.. what are the general settings for rcx for extraction the layout so that the simulated results will be very accurate. I mean some use RC decoupled and some use RC coupled. Max fracture length infinite or 1? (for best accuracy) I am not talking specifically about any particular accuracy. I mean was in general what
Hi all, I want to perform post layout simulation of sram cell in cadence 6.1.4. I have completed drc n lvs steps successfully with assura.But i can't extract gives error that "no directory found". I have attached screenshots of settings for directory please help me if anybody can solve this problem...Thanks in advance...[A
Hi all, When I do some extraction of my layout, I found a strange thing, some big rfmos are extracted while the other small rfmos not. In my HCELL file, this type rfmosfet is included. The version of assura is 4.1_USR2, while the IC is 6.1.5. Hope someone can help me. I don't want those RF devices to be extracted. Thanks for your help.
If this is assura, then you first need a clean LVS, then you run rcx, then you prepare the av_analog_extracted view, then create the config view for your simulation testbench; open it, start analog environment and select that view for the inverters and then proceed with simulating.
I am working on cadence 514 using assura 317 I am clean my design upto DRC zero and LVS match.But when I am run rcx it shows me creat blank av_extracted view.Because of that I am unable to run post layout simulation.Here I have also attached my rcx log file
I have a mixed signal design with cells connected to VCC and GND and logic gates with global pins (VCC! and GND!). In the layout VCC is connected to VCC! and GND is connected to GND!. I run the LVS using the joinNets switch for the schematic: joinNets( root "GND!" "GND" ) joinNets( root "VCC!" "VCC" ) The LVS is clean. I run the rcx (only C
hi, I can not see the av_extrated view in assura 317. I am using cadence 514 for schematic and by using SDL I am generate the layout which passses from zero DRC and LVS match. but when I was try to run rcx it is failed. and one av_extrated file is generate which is blank. Thanx
Hi Friends, How can you prevent double counting of parasitics in assura rcx? Thanks
Hi all, I have done rcx using assura and get the extracted file. Then how to use hspice to do the post-simulation? What are the steps? (I used hspice to do the front-simulation.) Thanks in advance.
This looks older post - but not having right solution: Transistor level rcx, the input data source is LVS db. This is used to backannotate. If you are trying to create av_extracted view - run LVS with DFII schematic & Layout not CDL & GDS. For CDL GDS flow, create SPICE, Spectre, xDSPF, xSPEF netlist only, as an output from rcx. Check if you are
It is not a problem, assura is just extracting your layout: when you have 4 fingers, you have 3 drains and 2 sources (or 2 drains and 3 sources), alternating. The capacitance is going to be different for every finger. I am surprised that fingers 1-3 and 2-4 match, I would have expected 1-4 and 2-3 but of course it depends on your layout.
Hey! I've designed an LNA in Cadence (TSMC 0.35um CMOS technology). After successfully running DRC and LVS, when I tried to run rcx on my layout design, it gave the following errors: 'Can't access compare.rul' 'error loading master control file rcx.trial2.rsf' (my cell view name is trial 2) 'error in loadstring' I read over some forums that you nee
Anybody knew how run assura rcx, using Cadence 6.1.3? In the Substrate insert I need to indicate SNA Tech Dir. Where can I get it? Is the SNA Tech Dir related to Cadence or Design Kits? Thanks in advance.
... any literature on assura rcx, I will appreciate. Don't know if this will be helpful?
hello i'm facing this issue when i run the rcx extraction tool in assura. *ERROR* No library model for device "short ivpcell substrateLib". *WARNING* dbOpenCellViewByType: Failed to open cellView (short ivpcell) from lib (substrateLib) in 'r' mode because cellview does not exist. *ERROR* No library model for device "TIE symbol substrateLib
assura (tm) Physical Verification Version av3.1:Production:dfII5.1.41 Release 3.1.6 Copyright (c) Cadence Design Systems. All rights reserved. @(#)$CDS: assura version av3.1:Production:dfII5.1.41 07/21/2006 04:00 (tux21ee) $ sub-version 3.1.6, integ signature 2006-06-06-1703t run on from /cad/Cadence/AS
Hi I am using a PDK and used caps and inductors from the design kit. When I run rcx to generate an RC av_extracted view the simulator fails to extract the PDK caps and inductors. I do not get any errors ie extraction succeeds, so I am not to sure where the problem is. any help is appreciated. Thanks!
Hi, I have to do LVS in assura before performing rcx extraction. However I do not have a schematic view, but the design netlist in spice (with include files path mentioned in it). Will it work if I mention this in the assura-> Run LVS window instead of the schematic view? I am getting so many problems regarding the netlist am giving. (...)
Can anyone explain to me why i get this type of warning when i run the assura rcx? the follwing is the warning i get: Constructing the rcx run script Could not open file /projects/cllee/technoloogy/silterra/silterraC13_1_9_02apr2008/assura_silterraC13_tech/lvs/rcxspiceINIT for reading *WARNING* Bad (...)
i did rcx extraction in assura, i have extrated cap. and res. in extracted view but i m not able to get netlist file in which all the cap and resistor are defined..... i need this type of file------ Netlist .GLOBAL AVDD AGND * .SUBCKT sch_trig IN OUT * * * caps2d version: 9 * * * TRANSISTOR CARDS * * MN1 net050 OUT AVDD AGND nch L=0
Refer here: . You probably need assura3.2 now, refer to the release notes for the assura kit. In assura3.2 the assura pulldown menu will have Run QRC
by "assura extraction" I assume you're using rcx. The kit no longer supports rcx, use Cadence QRC. You can find the supported tools here (IC613 is also supported although its not listed):
What version of IC are u using? I'm using IC5141 and EXT71 doesn't have its own menu, it replaces assura rcx in the assura menu. The menu still says rcx, but you need set QRC_ENABLE_EXTRACTION="t" in your startup script.
Hello, I am having trouble running assura rcx. I am currently using Cadence Virtuoso 6.1.3 with IBM PDK cmos10lpe (65nm). I ran assura LVS on a simple inverter cell and it has no probem passing LVS check (I ran DRC on the same inverter with Synopsys Hercules because the IBM PDK that I am using does not provide a rule set for (...)
Hello everyone! when I do post-simulation with assura extracted-view after the lvs and rcx step, I find an odd problem. As is showed in the picture a rf_mim cap is directly connected to the gate of a MOS transistor. But their DC voltage are different. And it seems the rf signal of the two points have no relationship. Besides, I found that DC
Hi, everybody! Our circuit is operating beyond 10GHz, so we must consider all possible parasitics and make full use of EDA tools. We met a problem when we used assura rcx-HF(av32) to enable substrate extraction for TSMC 0.18um RF/MM CMOS technology(v1.5d). In the final step, appears ‘SNA Tech Dir’, but we don’t know what it
I did two assura rcx extractions with "coupling" and "de-coupling" extraction. The post-layout simulation gives pretty different result. The "de-coupling" one works fine, but not the "coupling" one. So which extraction is more accurate? Thanks.
hi,guys These days I am doing a layout of a cascode amp,I set up vdd and gnd as inputoutput pins and label them in the layout.After I run a rcx to extract the RC parasitics,backannotate in the schematic and find that, the pcapacitors are displayed without the presistor, it showed "r=NA". But in the av_extracted view, I can see presistors by enl
assura rcx is still supported by IC5.141.We use it daily...nop..
Hi, all. I use icfb 5.1.41, assura 3.1.6 and UMC 0,18. The DRC and LVS for my circuit is clean. When I run assura rcx, it says: assura rcx run failed! The log file says: *Warning* avrcx: The LVS run used ?rulesFile, which overrides the technology directory operation. You must now (...)
I am using assura within IBM cms9flp design kits. 1. There is no problem with DRC and LVS, but the extracted view generated by DRC only have all the pins in the view, and no component at all! If it passed the LVS, I believe the extraction should be correct. So is this the display problem or something else? 2. If I use rcx I can get the extra
which are better assura or DRACULA or DIVA or CALIBRE or HERCULUS? Is there using DRACULA in companies?
For my layout, I have passed the DRC and LVS checking using assura. As I do the extraction in RC or R only extraction mode, it gives out the error and stated: *ERROR* FAILED ASSERTION at ?reconnect?: rcx net 1722 cannot be mapped to LVS net If I use C only extraction mode, it could do the extraction. Could you tell me the solving
Hi all, I am using assura rcx for parasitic extractions. In the menu of rcx, there are extraction modes like: extract RC, R only, C only, RLC, RLCK. I know how to extract RC parasitics, but I don't know how to extract RLC, RLCK. Does anyone know how to do this. There are several setting for doing RLC/RLCK extractions and I don't (...)
After renew the license, I run the assura rcx with error. (DRC and LVS are alright) But it is only happened in sparc Solaris machine, it is alright in x86 Linux machine. I use same layout to do the test. Both Linux and Solaris use IC5141 and assura3.1.7. Please help! rcx Error message (...)
assura Parasitic Extraction Lecture Manual. Version 3.1.2
there are three kind of options decoupled, coupled and decoupled to substrated in assura rcx tools. but, I can't understand exactly. could you explain the different among that and how to use that? when do i have to use coupled or decoupled or decoupled to substrated?
Hi, I'm having parasitic exstraction with assura 3.12 and I got the following error: *ERROR* no model library for device "y ivpcell" *ERROR* no model library for device "x ivpcell" what are device y and x?? I haven't it on my layout.... please help me :-(