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96 Threads found on edaboard.com: Assura Rcx
I'm trying to generate a netlist from a layout view using assura rcx. My question is: Does assura rcx also use the schematic view to extract parameters from layout? Thanks
assura rcx has worked before but now gives the error for any cell: *Error* append: argument #2 should be a list -"rcx Nets" If anyone knows how to fix this problem please let me know, any help would be greatly appreciated. Thank you.
With my assura rcx and UMC version, it seems that parasitic capacitances are extracted twice. The extracted view shows the corresponding ivpcell view for the library component (that already includes the parasitic elements) and another ivpcell parasitic capacitance, that should not appear. I have problems, at least, with pads and mim capactiors...
The assura rcx can not run correctly, after LVS is clean. The error message is 'sh: /ru_assura_lvs/design/rcx.sh: bad interpreter: No such file or directory *WARNING* Bad reture status from rcx run. 0x7e ' who can help me ? I use IC5033, assura3.14, TSMC PDK. Thanks!!!
Hi, For my design, The DRC and LVS for the circuit is clean. Now, when assura rcx is run, the tool gives assura rcx run failed. It says @(#)$CDS: assura version av3.1:Production:dfII5.0.0 01/09/2004 14:40 (sjpvlin1) $ sub-version 3.1.2, integ signature 2003-11-21-0052bl run on (...)
When assura rcx you can create netlist of spectre or hspice. If you create a view of "av_extracted" you can following eng_Semi said in hierarchy editor to select any views of any cells.
Hi, I use the Cadence tool assura rcx. How can I extract inductances from a piece of layout without having a schematic. I mean I only have a shape (i.e. long path) and want to know its inductance. Regards, Tom
Hi! I have some problem with the parasitic extraction, using assura rcx. I'm trying to select the minimum value of capacitance that the tool have to set during the extraction. I can set the minimum value (in femtoFarad) and a percentage(I don't know to what it's referred). I have tryed many times with different values, but after the extraction
After renew the license, I run the assura rcx with error. (DRC and LVS are alright) But it is only happened in sparc Solaris machine, it is alright in x86 Linux machine. I use same layout to do the test. Both Linux and Solaris use IC5141 and assura3.1.7. Please help! rcx Error message (...)
Hi all, I am using assura rcx for parasitic extractions. In the menu of rcx, there are extraction modes like: extract RC, R only, C only, RLC, RLCK. I know how to extract RC parasitics, but I don't know how to extract RLC, RLCK. Does anyone know how to do this. There are several setting for doing RLC/RLCK extractions and I don't (...)
Hi, all. I use icfb 5.1.41, assura 3.1.6 and UMC 0,18. The DRC and LVS for my circuit is clean. When I run assura rcx, it says: assura rcx run failed! The log file says: *Warning* avrcx: The LVS run used ?rulesFile, which overrides the technology directory operation. You must now (...)
Hi, everybody! Our circuit is operating beyond 10GHz, so we must consider all possible parasitics and make full use of EDA tools. We met a problem when we used assura rcx-HF(av32) to enable substrate extraction for TSMC 0.18um RF/MM CMOS technology(v1.5d). In the final step, appears ‘SNA Tech Dir’, but we don’t know what it
Hello, I am having trouble running assura rcx. I am currently using Cadence Virtuoso 6.1.3 with IBM PDK cmos10lpe (65nm). I ran assura LVS on a simple inverter cell and it has no probem passing LVS check (I ran DRC on the same inverter with Synopsys Hercules because the IBM PDK that I am using does not provide a rule set for (...)
Can anyone explain to me why i get this type of warning when i run the assura rcx? the follwing is the warning i get: Constructing the rcx run script Could not open file /projects/cllee/technoloogy/silterra/silterraC13_1_9_02apr2008/assura_silterraC13_tech/lvs/rcxspiceINIT for reading *WARNING* Bad (...)
Anybody knew how run assura rcx, using Cadence 6.1.3? In the Substrate insert I need to indicate SNA Tech Dir. Where can I get it? Is the SNA Tech Dir related to Cadence or Design Kits? Thanks in advance.
Hi all, When I do some extraction of my layout, I found a strange thing, some big rfmos are extracted while the other small rfmos not. In my HCELL file, this type rfmosfet is included. The version of assura is 4.1_USR2, while the IC is 6.1.5. Hope someone can help me. I don't want those RF devices to be extracted. Thanks for your help.
Hi, I want to do parasitic extraction of an inverter design using assura rcx.Its a UMC180nm project. DRC and LVS are clean for this design. assura is version 3.1.6 on Linux. It can be serious bottleneck for the project undertaken. Getting following failure log upon running. (...)
Hi, I am using assura rcx to carry out parasitic extraction of an inverter layout. Cadence icfb version I am using is IC5141USR1. The tool is extracting the layout successfully, but the extracted view shows NMOS and PMOS symbols in place of metal layers. Parasitics (resistors and capacitors) symbols are present in the extracted view, but it
Hi! I have installed IC5033 and assura 3.1 on Fedora Core 2. Unfortunatelly I cant start assura rcx! When i try to start assura rcx from Virtuoso, a folowing error is reported: "*Error* isDir: argument #1 should be either a string or a symbol (type template = "Sg") - nil"? Please help! Thanks, (...)
Hello! I have installed IC5033 and assura 3.1 on Fedora Core 2. And I have done this on few other mashines also (same configuration). I was hoping that Multimachine possibility in rcx will work, but unfortunatly i was wrong! It only ping the other machine and that's it. On the internet and in Cadnece documentation i can't find any tutorial o
Hi, I have passed LVS, but when I am going to run rcx it cannot be launched & shows the following message in CIW : *Error* append: argument #2 should be a list - "rcx Nets" What is the problem? Sometimes I can launch it but sometimes cannot. Thx!
:cry: Once I got a clean LVS, I ran rcx but I got an error. #==========================================================# # Run pax16 to generate capfile #==========================================================# pax16 -V -scf sip.cmd -filterfile maxnetfile -dC \ mt1_cpoly_mimcap_mimcap_CAP_927.cap -M_perim_off -c \ /local3/consult2/X
Hi all, I have no knowledge about assura, and StarrcxT. I'm looking for some good materials/docs/websites for those to help me understand how to implement them in my project. Please, have some inputs/feedbacks. Many thanks! A.T
hi, im using assura rcx to do layout extraction, i wonder what the "MinC" in the filtering tab means? and how can i set the value of MinC and the value of the %? and what does the value of % mean? thanks newbie
hi, Does anyone has the rcx scripts for 65nm of tsmc? and can you share it with me? thanks
Hi, I'm having parasitic exstraction with assura 3.12 and I got the following error: *ERROR* no model library for device "y ivpcell" *ERROR* no model library for device "x ivpcell" what are device y and x?? I haven't it on my layout.... please help me :-(
there are three kind of options decoupled, coupled and decoupled to substrated in assura rcx tools. but, I can't understand exactly. could you explain the different among that and how to use that?
there are three kind of options decoupled, coupled and decoupled to substrated in assura rcx tools. but, I can't understand exactly. could you explain the different among that and how to use that? when do i have to use coupled or decoupled or decoupled to substrated?
For my layout, I have passed the DRC and LVS checking using assura. As I do the extraction in RC or R only extraction mode, it gives out the error and stated: *ERROR* FAILED ASSERTION at ?reconnect?: rcx net 1722 cannot be mapped to LVS net If I use C only extraction mode, it could do the extraction. Could you tell me the solving
hi,guys These days I am doing a layout of a cascode amp,I set up vdd and gnd as inputoutput pins and label them in the layout.After I run a rcx to extract the RC parasitics,backannotate in the schematic and find that, the pcapacitors are displayed without the presistor, it showed "r=NA". But in the av_extracted view, I can see presistors by enl
This looks older post - but not having right solution: Transistor level rcx, the input data source is LVS db. This is used to backannotate. If you are trying to create av_extracted view - run LVS with DFII schematic & Layout not CDL & GDS. For CDL GDS flow, create SPICE, Spectre, xDSPF, xSPEF netlist only, as an output from rcx. Check if you are
Hi I am using a PDK and used caps and inductors from the design kit. When I run rcx to generate an RC av_extracted view the simulator fails to extract the PDK caps and inductors. I do not get any errors ie extraction succeeds, so I am not to sure where the problem is. any help is appreciated. Thanks!
... any literature on assura rcx, I will appreciate. Don't know if this will be helpful?
Hey! I've designed an LNA in Cadence (TSMC 0.35um CMOS technology). After successfully running DRC and LVS, when I tried to run rcx on my layout design, it gave the following errors: 'Can't access compare.rul' 'error loading master control file rcx.trial2.rsf' (my cell view name is trial 2) 'error in loadstring' I read over some forums that you nee
It is not a problem, assura is just extracting your layout: when you have 4 fingers, you have 3 drains and 2 sources (or 2 drains and 3 sources), alternating. The capacitance is going to be different for every finger. I am surprised that fingers 1-3 and 2-4 match, I would have expected 1-4 and 2-3 but of course it depends on your layout.
@AMITH, In your rcx run window, you can find the run details the run details tab, you can find run directory and both sch_cap_ground as well as lay_cap_ground would be created by assura. If you cant find, you can create it by yourself. Thanks, Siva hi,siva actually I have faced the same problem that
I have a mixed signal design with cells connected to VCC and GND and logic gates with global pins (VCC! and GND!). In the layout VCC is connected to VCC! and GND is connected to GND!. I run the LVS using the joinNets switch for the schematic: joinNets( root "GND!" "GND" ) joinNets( root "VCC!" "VCC" ) The LVS is clean. I run the rcx (only C
Hi all, I want to perform post layout simulation of sram cell in cadence 6.1.4. I have completed drc n lvs steps successfully with assura.But i can't extract gives error that "no directory found". I have attached screenshots of settings for directory please help me if anybody can solve this problem...Thanks in advance...[A
Hello, I am just wondering.. what are the general settings for rcx for extraction the layout so that the simulated results will be very accurate. I mean some use RC decoupled and some use RC coupled. Max fracture length infinite or 1? (for best accuracy) I am not talking specifically about any particular accuracy. I mean was in general what
Dear all, I wonder if the tsmc 65nm kits are compatible with assura DRC. Compatibility with assura LVS and assura rcx seems ensured, but I cannot made DRC work... In the assura directory of the kit, there is no drc.rul or similar one, whereas the "training" included in the PDK clearly mention the DRC (...)
There is also assura rcx, successor of Vampire. Hierarchical, good for large designs. If you want to do parasitic extraction on the call based design, you can use also Hyperextract (2.5D) - Cadence, or Fire&Ice Cadence (former simplex).
Dear all, I have seen the manual of the Assua Physical Verification User Guide. However, I am still not clear what is the different between the coupled and decoupled parasitic caps. extraction. Could anyone explain it in detail? Thanks for your helping. Best Regards, wccheng
The DRC and LVS operate normarlly in assura, but when start rcx, the problem in cds.log assura TCX run: loading Technology data, stand by... \e *Error* putprop: first arg must be either symbol, list, defstruct or user type - nil \e *Error* putprop: first arg must be either symbol, list, defstruct or user type - (...)
Hi I need to know how to obtain a list with all net names of a design in Cadence Virtuoso because I want to do a rcx-Extraction of selected nets with assura. Thanks
How to modify the accuracy in the extractor of StarrcxT? Like the function of "filter" in assura rcx. As if we set minimum cap to 0.1fF, the software will skip all the parasitic cap which are smaller than 0.1fF. I had looked up in the sold0412, but nothing was found to be related. Is it possible that the StarrcxT (...)
Hello, I am generating an hspice netlist using ADE from the av_extracted view (obtained from assura rcx). The problem is that the netlist is missing the gnd and the vdd nodes and instead has numbers for the nodes. Because of this I get no path to ground errors while doing an hspice simulation. Does anyone have any ideas on how to retain the node
Hello, I am generating an hspice netlist using ADE from the av_extracted view (obtained from assura rcx). The problem is that the netlist is missing the gnd and the vdd nodes and instead has numbers for the nodes. Because of this I get no path to ground errors while doing an hspice simulation. Does anyone have any ideas on how to retain the node
I had the same problem with suse 9.1. i included the PATH $assuraHOME/tools/assura/bin and the DRC problem was solved. I had also a problem with rcx because assura was trying to find /bin/ksh. I solved the problem creating a link "ln -s bash ksh" in /bin. Bye :D
Hi Besides star-rcxt and fire&ice(though I never heard of it), there are many RC extration tools, i.e., diva, assura-rcx, Xcalibre etc. regards, jordan76
Hi, I have some questions regarding assura LVS/rcx. 1) How to debug assura LVS? To debug DIVA extraction, I used to use saveDerived and view the layer in the extracted view. But assura there is no extracted view, so how to go about debugging? 2) Can I run LVS after rcx? This is to check if the (...)