120 Threads found on edaboard.com: Assura Rcx
I'm trying to generate a netlist from a layout view using assura rcx. My question is: Does assura rcx also use the schematic view to extract parameters from layout?
Thanks
Analog IC Design and Layout :: 23.08.2004 14:16 :: pantic :: Replies: 1 :: Views: 1079
assura rcx has worked before but now gives the error for any cell:
*Error* append: argument #2 should be a list -"rcx Nets"
If anyone knows how to fix this problem please let me know, any help would be greatly appreciated. Thank you.
Analog IC Design and Layout :: 04.03.2005 17:07 :: kramer :: Replies: 0 :: Views: 638
With my assura rcx and UMC version, it seems that parasitic capacitances are extracted twice. The extracted view shows the corresponding ivpcell view for the library component (that already includes the parasitic elements) and another ivpcell parasitic capacitance, that should not appear. I have problems, at least, with pads and mim capactiors...
Software Problems, Hints and Reviews :: 18.04.2005 16:49 :: hsolar :: Replies: 0 :: Views: 650
The assura rcx can not run correctly, after LVS is clean.
The error message is
'sh: /ru_assura_lvs/design/rcx.sh: bad interpreter: No such file or directory
*WARNING* Bad reture status from rcx run. 0x7e '
who can help me ?
I use IC5033, assura3.14, TSMC PDK.
Thanks!!!
Analog IC Design and Layout :: 05.07.2005 11:14 :: Question :: Replies: 2 :: Views: 971
Hi,
For my design,
The DRC and LVS for the circuit is clean.
Now, when assura rcx is run, the tool gives assura rcx run failed. It says
@(#)$CDS: assura version av3.1:Production:dfII5.0.0 01/09/2004 14:40 (sjpvlin1) $
sub-version 3.1.2, integ signature 2003-11-21-0052bl
run on (...)
Linux Software :: 10.04.2006 10:42 :: carrot :: Replies: 5 :: Views: 2257
When assura rcx you can create netlist of spectre or hspice.
If you create a view of "av_extracted" you can following eng_Semi said in hierarchy editor to select any views of any cells.
Software Problems, Hints and Reviews :: 23.06.2006 10:10 :: jizhongren :: Replies: 2 :: Views: 778
Hi,
I use the Cadence tool assura rcx. How can I extract inductances from a piece of layout without having a schematic. I mean I only have a shape (i.e. long path) and want to know its inductance.
Regards,
Tom
Analog IC Design and Layout :: 03.06.2007 22:04 :: Thomas Mann :: Replies: 3 :: Views: 1342
Hi!
I have some problem with the parasitic extraction, using assura rcx.
I'm trying to select the minimum value of capacitance that the tool have to set during the extraction.
I can set the minimum value (in femtoFarad) and a percentage(I don't know to what it's referred).
I have tryed many times with different values, but after the extraction
ASIC Design Methodologies and Tools (Digital) :: 06.06.2007 12:00 :: GertDalPozzo :: Replies: 0 :: Views: 957
After renew the license, I run the assura rcx with error. (DRC and LVS are alright) But it is only happened in sparc Solaris machine, it is alright in x86 Linux machine. I use same layout to do the test. Both Linux and Solaris use IC5141 and assura3.1.7. Please help!
rcx Error message (...)
Analog IC Design and Layout :: 16.04.2008 09:25 :: lahaha :: Replies: 0 :: Views: 658
Hi all,
I am using assura rcx for parasitic extractions. In the menu of rcx, there are extraction modes like: extract RC, R only, C only, RLC, RLCK.
I know how to extract RC parasitics, but I don't know how to extract RLC, RLCK.
Does anyone know how to do this. There are several setting for doing RLC/RLCK extractions and I don't (...)
Analog IC Design and Layout :: 17.04.2008 10:25 :: DoYouLinux :: Replies: 2 :: Views: 966
Hi, all.
I use icfb 5.1.41, assura 3.1.6 and UMC 0,18.
The DRC and LVS for my circuit is clean.
When I run assura rcx, it says: assura rcx run failed!
The log file says:
*Warning* avrcx: The LVS run used ?rulesFile, which overrides the technology directory operation. You must now (...)
Analog IC Design and Layout :: 24.06.2008 18:15 :: dmitry_pr :: Replies: 5 :: Views: 2014
Good afternoon:
I have met a problem in the process of running assura rcx extraction. that is shown in the following. Could you help me to solve it?Thanks!
assura (tm) Physical Verification Version av3.1:Production:dfII5.1.41
Release 3.1.5
Copyright (c) Cadence Design Systems. All rights reserved.
@(#)$CDS: (...)
Analog IC Design and Layout :: 20.11.2008 08:36 :: shhaha :: Replies: 6 :: Views: 2979
Hi, everybody!
Our circuit is operating beyond 10GHz, so we must consider all possible parasitics and make full use of EDA tools. We met a problem when we used assura rcx-HF(av32) to enable substrate extraction for TSMC 0.18um RF/MM CMOS technology(v1.5d). In the final step, appears ‘SNA Tech Dir’, but we don’t know what it
Analog IC Design and Layout :: 22.05.2009 02:29 :: chenpufeng :: Replies: 0 :: Views: 700
Hello, I am having trouble running assura rcx. I am currently using Cadence Virtuoso 6.1.3 with IBM PDK cmos10lpe (65nm). I ran assura LVS on a simple inverter cell and it has no probem passing LVS check (I ran DRC on the same inverter with Synopsys Hercules because the IBM PDK that I am using does not provide a rule set for (...)
Analog Circuit Design :: 12.06.2009 21:39 :: pokemonstation :: Replies: 5 :: Views: 6435
Can anyone explain to me why i get this type of warning when i run the assura rcx?
the follwing is the warning i get:
Constructing the rcx run script
Could not open file /projects/cllee/technoloogy/silterra/silterraC13_1_9_02apr2008/assura_silterraC13_tech/lvs/rcxspiceINIT for reading
*WARNING* Bad (...)
Analog IC Design and Layout :: 05.04.2010 18:46 :: wing0 :: Replies: 1 :: Views: 1418
Anybody knew how run assura rcx, using Cadence 6.1.3? In the Substrate insert I need to indicate SNA Tech Dir. Where can I get it? Is the SNA Tech Dir related to Cadence or Design Kits?
Thanks in advance.
Analog IC Design and Layout :: 14.07.2010 15:26 :: ShN :: Replies: 0 :: Views: 580
Need more clarity on the question. RFMOS "device" extraction should be happening at the LVS extraction stage - what does that has any relation with rcx?
If this is LVS problem - which LVS tool Which technology? layout of "big" and "small" rfmos may help, overall more details will help.
Analog IC Design and Layout :: 22.11.2011 23:19 :: sat :: Replies: 2 :: Views: 373
Hi,
I want to do parasitic extraction of an inverter design using assura rcx.Its a UMC180nm project. DRC and LVS are clean for this design. assura is version 3.1.6 on Linux. It can be serious bottleneck for the project undertaken.
Getting following failure log upon running. (...)
Analog IC Design and Layout :: 05.10.2012 12:32 :: anannya :: Replies: 3 :: Views: 249
Hi,
I am using assura rcx to carry out parasitic extraction of an inverter layout. Cadence icfb version I am using is IC5141USR1. The tool is extracting the layout successfully, but the extracted view shows NMOS and PMOS symbols in place of metal layers. Parasitics (resistors and capacitors) symbols are present in the extracted view, but it
Analog IC Design and Layout :: 16.11.2012 11:23 :: anannya :: Replies: 3 :: Views: 212
Hi!
I have installed IC5033 and assura 3.1 on Fedora Core 2. Unfortunatelly I cant start assura rcx! When i try to start assura rcx from Virtuoso, a folowing error is reported:
"*Error* isDir: argument #1 should be either a string or a symbol (type template = "Sg") - nil"?
Please help!
Thanks, (...)
Linux Software :: 23.06.2004 17:15 :: vlado :: Replies: 6 :: Views: 2863
Hello!
I have installed IC5033 and assura 3.1 on Fedora Core 2. And I have done this on few other mashines also (same configuration). I was hoping that Multimachine possibility in rcx will work, but unfortunatly i was wrong!
It only ping the other machine and that's it.
On the internet and in Cadnece documentation i can't find any tutorial o
Linux Software :: 14.07.2004 13:26 :: vlado :: Replies: 0 :: Views: 635
Hi,
I have passed LVS, but when I am going to run rcx it cannot be launched & shows the following message in CIW :
*Error* append: argument #2 should be a list - "rcx Nets"
What is the problem?
Sometimes I can launch it but sometimes cannot.
Thx!
Analog IC Design and Layout :: 01.09.2004 13:20 :: dragonwell :: Replies: 0 :: Views: 707
:cry:
Once I got a clean LVS, I ran rcx but I got an error.
#==========================================================#
# Run pax16 to generate capfile
#==========================================================#
pax16 -V -scf sip.cmd -filterfile maxnetfile -dC \
mt1_cpoly_mimcap_mimcap_CAP_927.cap -M_perim_off -c \
/local3/consult2/X
Software Problems, Hints and Reviews :: 15.12.2005 00:07 :: kdavid94588 :: Replies: 0 :: Views: 1011
Hi all,
I have no knowledge about assura, and StarrcxT. I'm looking for some good materials/docs/websites for those to help me understand how to implement them in my project.
Please, have some inputs/feedbacks.
Many thanks!
A.T
Analog IC Design and Layout :: 07.03.2006 18:20 :: asktech :: Replies: 3 :: Views: 570
Hi,
EDA tools generally manipulate using the data from .lib which delays are from spice simulations.
Lets say in your libary u calculated the delays for 100ff and 300ff ,if the tool see the load of the cell is 200ff ,it manipulates using some alogorithms using the values of 100ff and 300ff to get the delays of 200ff LOAD.
You can get
ASIC Design Methodologies and Tools (Digital) :: 09.05.2006 14:47 :: arimilli_r :: Replies: 6 :: Views: 1148
hi,
im using assura rcx to do layout extraction, i wonder what the "MinC" in the filtering tab means? and how can i set the value of MinC and the value of the %? and what does the value of % mean?
thanks
newbie
Analog IC Design and Layout :: 05.08.2006 00:49 :: newbie_1 :: Replies: 6 :: Views: 648
hi,
Does anyone has the rcx scripts for 65nm of tsmc? and can you share it with me？
thanks
Analog IC Design and Layout :: 15.12.2006 20:14 :: newbie_1 :: Replies: 1 :: Views: 557
Hi, I'm having parasitic exstraction with assura 3.12 and I got the following error:
*ERROR* no model library for device "y ivpcell"
*ERROR* no model library for device "x ivpcell"
what are device y and x?? I haven't it on my layout....
please help me :-(
Software Problems, Hints and Reviews :: 29.02.2008 16:05 :: vinzetto :: Replies: 0 :: Views: 816
assura Parasitic Extraction Lecture Manual. Version 3.1.2
Analog Circuit Design :: 26.02.2009 10:17 :: pit1000 :: Replies: 3 :: Views: 964
there are three kind of options decoupled, coupled and decoupled to substrated in assura rcx tools. but, I can't understand exactly. could you explain the different among that and how to use that? when do i have to use coupled or decoupled or decoupled to substrated?
Analog IC Design and Layout :: 05.03.2008 01:04 :: yikwon1 :: Replies: 0 :: Views: 305
For my layout, I have passed the DRC and LVS checking using assura. As I do the extraction in RC or R only extraction mode, it gives out the error and stated:
*ERROR* FAILED ASSERTION at ?reconnect?: rcx net 1722 cannot be mapped to LVS net
If I use C only extraction mode, it could do the extraction. Could you tell me the solving
Analog IC Design and Layout :: 19.04.2008 11:10 :: wccheng :: Replies: 4 :: Views: 760
Which is the best tool for verification,userfriendly for layout
a)assura.
b)Calibre.
c)Diva
vote for ur best verfication tool.
Analog IC Design and Layout :: 28.04.2008 11:56 :: sridhar540 :: Replies: 23 :: Views: 1800
hi,guys
These days I am doing a layout of a cascode amp,I set up vdd and gnd as inputoutput pins and label them in the layout.After I run a rcx to extract the RC parasitics,backannotate in the schematic and find that, the pcapacitors are displayed without the presistor, it showed "r=NA". But in the av_extracted view, I can see presistors by enl
Analog IC Design and Layout :: 12.11.2008 13:43 :: mightyocean :: Replies: 9 :: Views: 1586
Hi,
I am working on a chip design which needs to be submitted to IBM in a short while. I have had some challenges with the design kit. I am currently the only user of this technology, so there are some basic issues involved.
I am trying to extract parasitics from my layout. DRC and LVS run properly and I do not get any major errors. However,
Analog IC Design and Layout :: 31.12.2009 01:37 :: BB2009 :: Replies: 3 :: Views: 1965
Hello all,
I am trying to extract the layout of an inverter in IBM cms9flp, with assura 3.1.7, Cadence IC6.1.2. But I do not see any option for assura QRC/rcx in the IBM_PDK pull down menu of the Layout Editor Window, like assura DRC/LVS. I found 'assura -> Run rcx' which is another pull (...)
Analog IC Design and Layout :: 26.01.2010 16:04 :: shahriar22nd :: Replies: 7 :: Views: 1911
Hi
I am using a PDK and used caps and inductors from the design kit. When I run rcx to generate an RC av_extracted view the simulator fails to extract the PDK caps and inductors. I do not get any errors ie extraction succeeds, so I am not to sure where the problem is.
any help is appreciated.
Thanks!
Analog IC Design and Layout :: 23.04.2010 01:22 :: EEsj :: Replies: 1 :: Views: 545
... any literature on assura rcx, I will appreciate.
Don't know if this will be helpful?
Analog IC Design and Layout :: 09.07.2010 15:19 :: erikl :: Replies: 3 :: Views: 1328
Hey! I've designed an LNA in Cadence (TSMC 0.35um CMOS technology). After successfully running DRC and LVS, when I tried to run rcx on my layout design, it gave the following errors: 'Can't access compare.rul' 'error loading master control file rcx.trial2.rsf' (my cell view name is trial 2) 'error in loadstring' I read over some forums that you nee
Analog IC Design and Layout :: 22.08.2010 16:48 :: EngrFZ :: Replies: 0 :: Views: 469
It is not a problem, assura is just extracting your layout: when you have 4 fingers, you have 3 drains and 2 sources (or 2 drains and 3 sources), alternating. The capacitance is going to be different for every finger.
I am surprised that fingers 1-3 and 2-4 match, I would have expected 1-4 and 2-3 but of course it depends on your layout.
Analog IC Design and Layout :: 15.11.2010 18:13 :: JoannesPaulus :: Replies: 5 :: Views: 344
Hi,
I wanna extract C only for my block. I have done rc extraction for a couple of blocks. but this time, assura is quitting with a strange error
=================================
cat < sch_cap_ground
VSS
ENDCAT
sch2lay -a -r /design/sysext/dt02/users/sivaram.popuri+dt02+dt02z+4/ver/lvs/integ_blk_siva/integ_blk_siva.gnx -rd /desig
Analog IC Design and Layout :: 07.04.2011 14:28 :: psrkforuvlsi :: Replies: 5 :: Views: 636
I have a mixed signal design with cells connected to VCC and GND and logic gates with global pins (VCC! and GND!). In the layout VCC is connected to VCC! and GND is connected to GND!. I run the LVS using the joinNets switch for the schematic:
joinNets( root "GND!" "GND" )
joinNets( root "VCC!" "VCC" )
The LVS is clean. I run the rcx (only C
Analog IC Design and Layout :: 22.06.2011 12:25 :: Pobyms :: Replies: 0 :: Views: 306
The answers to your questions can be found in the manuals that assura QRC provides along with it's for the errors you encounter nobody will help you get rid of them unless you provide a comprehensive description or screenshot of them ;-)
Analog IC Design and Layout :: 02.08.2011 15:09 :: jimito13 :: Replies: 3 :: Views: 1003
Hi all, I want to perform post layout simulation of sram cell in cadence 6.1.4. I have completed drc n lvs steps successfully with assura.But i can't extract gives error that "no directory found". I have attached screenshots of settings for directory please help me if anybody can solve this problem...Thanks in advance...[A
Analog IC Design and Layout :: 02.03.2012 08:02 :: kpkp :: Replies: 0 :: Views: 346
Hello,
I am just wondering.. what are the general settings for rcx for extraction the layout so that the simulated results will be very accurate.
I mean some use RC decoupled and some use RC coupled.
Max fracture length infinite or 1? (for best accuracy)
I am not talking specifically about any particular accuracy.
I mean was in general what
Analog Circuit Design :: 05.04.2012 14:38 :: priaz :: Replies: 0 :: Views: 245
Now i have to contact MOSIS for this issue.
In order to demonstrate this I'd suggest to build an extra circuit, e.g. an inverter with M0 & M25 and run assura and LVS. So the problem can be more clearly presented (and you get a better chance for their soon reaction).
If, however, these 2 transistors would get
Analog IC Design and Layout :: 15.05.2012 13:04 :: erikl :: Replies: 11 :: Views: 382
Dear all,
I wonder if the tsmc 65nm kits are compatible with assura DRC.
Compatibility with assura LVS and assura rcx seems ensured, but I cannot made DRC work...
In the assura directory of the kit, there is no drc.rul or similar one, whereas the "training" included in the PDK clearly mention the DRC (...)
Analog IC Design and Layout :: 11.09.2012 17:05 :: gag2000 :: Replies: 1 :: Views: 280
There is also assura rcx, successor of Vampire. Hierarchical, good
for large designs.
If you want to do parasitic extraction on the call based design,
you can use also Hyperextract (2.5D) - Cadence, or Fire&Ice Cadence
(former simplex).
ASIC Design Methodologies and Tools (Digital) :: 31.07.2002 22:27 :: moorhuhn :: Replies: 9 :: Views: 3023
But in every case, technolgy file should you permit to do extraction that is very difficult.
You mean that foundry does not provide a "full features" technology file? Or that RX assura full license is quite expensive?
Another (probably stupid) question: In my rdfe installation the ads standard library is directl
RF, Microwave, Antennas and Optics :: 18.12.2005 10:11 :: wasm :: Replies: 14 :: Views: 2829
Dear all,
I have seen the manual of the Assua Physical Verification User Guide. However, I am still not clear what is the different between the coupled and decoupled parasitic caps. extraction. Could anyone explain it in detail? Thanks for your helping.
Best Regards,
wccheng
Analog IC Design and Layout :: 08.09.2004 11:33 :: wccheng :: Replies: 2 :: Views: 3162
DIVA interactive DRC, LVS, ERC ...
assura : Batch mode DRC, LVS, ERC
DIVA for small block verification
assura for big block or whole chip verification
assura is more expensive, of course
Yeah, exactly.
But I want to know which one better for assura & Calibre, even Hercules.
thanks.
Analog IC Design and Layout :: 08.10.2004 04:19 :: z81203 :: Replies: 10 :: Views: 2720
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