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1000 Threads found on edaboard.com: Astro Place And Route
astro
Hi place and route Tools download 1. -> t tnx
Hello, I am trying to run my testbench to do a simulation check after Xilinx has done place and route for the design. When it brings modelsim up and tries to simulate it gives errors such as: # ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver". # No such file or directory. (errno (...)
I need technology library for amplify asic to run place and route.where i can find something for this tool? I have tried something but it doesn't work.what do you use?
I tried to do manual place and route but it seems like it only let me do place but not route. I can manually place the logic blocks but I could not manually route the signal from one block to another. THis is the free download version. Maybe the full version will let you.
Since ISE does not seem to support the Spartan (I), and yet Leonardo does, how does one place and route without having what ever old version of foundation that is required? jelydonut
I am taking VLSI place and route course. and using cadence silicon ensemble EDA tool. Anyone can tell me where can i find some useful documents, class notes, books to learn the concepts about P&R. Also SE's notes? The instructor doesn't give us any useful and systmatic notes to study.
how to do auto place and route by using cadence to implement gate array instead of standard cell. Thanks. Added after 9 minutes: any tutorial file or doc? thanks.
hello, where can i get the details about the difference in full custom flow and place and route flow. thanks in advance. Prasad
Hello, I was wondering what factors contribute to inaccuracies between the timing as reported by Synopsys and actual timing after place and route? What can I do in general to fix these inaccuracies?
can we place and route using standard cells of gates in cadence Virtuoso?????/ thanks in advance, Prasad
Hi Guys I am using ISE7.1i for my design. While doing place and route i get a particular warning which i am not able to understand. Can anyone please explain wht it means and why it is comming. WARNING:Par:276 - The signal MB(197)_IBUF has no load I get this warning for all the io pins what i have for (...)
Hello! I have minimal experience with Xilinx and now I have to do a project with itXilinx. For this I use Xilinx 8.1i. Which are the settings for best result in synthezis, place and route?
HI , There are two options available for netlist generation viz. hierarchy and flatten approach. What impact does it have in place and route.
Hi Is it possible to do Clock tree synthesis "CTS" for vertix-4 FPGA using Xilinx ISE ? and if possible How to do it? How to estimate the required buffring for a clock after place and route? Salam Hossam Alzomor
i am an analog designer , but i have to do some digital layout , i already have the standard cell (schematics and layout) but i have to do the place and route , but this will be done manually, so i was hoping that anyone would provide some tips or hints on the right way to do the P&R to save area as much as (...)
Hi all, In the Physical Synthesis in PKS tool, i was able to synthesis my code and get the schematic and even the initial floorplan. Once the initial floorplan is over ,i am trying to add the power nets to the netlist using the command 'set_power_stripe_spec' , but it is giving error "power specs not valid , it will be ignored"... Can (...)
What is checkerboard pattern in place and route??:?:
Hello, i got a gds file, and need to conduct place and route in cadence how do i go about doing place and route? i had stream in the gds file, what happenes after here? how do i create the symbol, and other things? thanks
Can any one tell me about the lef diagram of inverter?
Hi after doing place and route will it reduce my dut's frequency, if so why? please correct me if i am wrong.
Hi all, When I synthesize my VHDL model XST synthesis reports says that the design can run at some 215Mhz, and when simulate the behavioral model (at 100 Mhz) every thing is fine. But when I try to simulate the post place and route model with the same test bench at 100 Mhz it not working at all. But it works fine if I (...)
Dear all, Can anybody tell me what is the significance of Manual "place and route" in Xilinx tools ( i Use xilinx9.1) and how to do it in DETAIL! Is manual process really useful considering the Good place and route algorithms embedded in vendor`s tools. i may be (...)
Dear all, Can anybody tell me what is the significance of Manual "place and route" in Xilinx tools ( i Use xilinx9.1) and how to do it in DETAIL! Is manual process really useful considering the Good place and route algorithms embedded in vendor`s tools. i may be wrong, so (...)
the software for gate array place and route ? gate ensemble? astroGA? anyone know ? thank u
Hi all Can any one give me the docs which explains very basic fundamentals on place and route(specially on routing, about metal layers and all ). I am unable to get the docs on fundamentals concepts Thanks
Hi, Friends, I am new to this area and I have a question for you. If I will receive a full place and route (after routing and all the procedures) design : 1) How do I know which layers any macro in my design used? 2) If I would ask this question before the place (...)
Hello all, I have been implementing a design on a Xilinx FPGA for a few weeks. Since the rtl is huge it takes arnd 5hrs for synthesis and place and route to complete(1hr+4hr). Everytime there is a small change in the RTL, the whole process needs to be redone and it consumes a lot of time. Is (...)
Introduction to place and route Design in VLSIs By Patrick Lee can any one send me free link to download this book? Thanks
I'm a newbie. Please help! I've finished the verilog coding for a chip consisting of several big blocks. SOC encounter offers partition approach of place and route. The doc says there are top-down or bottom-up approaches. It seems to be easier for me to go bottom-up approach. My question is: When I work on each block, do I need to (...)
Hi All, Can any body provide me some docs about place and route. I need them. Regards
hi friend i m using syniplify pro for the synthesis of my project 2009C but i can't find xilinx place and route in this any one plz give me link for the xilinx place and route Thanks
Hello there, In the place and route stage, I have to fill in the metal 1 spacing and metal 2 spacing. However I don't know how to deduce these values. I'm looking at its LEF file, but don't know at what I should be looking for. Can anyone please shed some light please ?
I am working on analysing the effect of various place and route schemes on the capacitance of a circuit. So,please let me know the different place and route schemes used in Cadence Encounter in the order of optimality it provides
i'm somewhat new to fpgas and digital design. i'm using ISE Webpack 11.1 to learn about all of that. after i design something i simply follow a series of steps a tutorial "told" me to do, so that the design could be put onto the fgpa. however i don't know why i'm doing it. out of the steps i take i only understand what synthesis is (this step gener
Hi I'm doing a full custom IC design for digital system using Cadence tools. I'm now in the process of doing DRC for my layout and after this LVS. Is it the nest step is doing place and route? and I have no tool that can automated place and route. Can (...)
Hi buddies, let me try to briefly summarize what I do before illustrating the problem. I have a design with 16 sub-blocks. 1) the design is partitioned and 16 partitions are saved 2) I work block by block doing place and route 3) when all the blocks are placed&routed I reopen the main (...)
Hi Can Anyone explain me in detail, how router works in different tool which is used for place and route(P&R) designs. and what are the most common algorithms used for routing(global and final) nets in design .
Dear all, I have a simple logic circuit which is instance from standard cell. The number of standard cell is around 100. As I know the Virtuoso XL provide a simple software to do place and route. I have searched one link (DIMOS01 Design Tutorial - placement and (...)
Dear All, We are doing a project on FPGA and we have finished design synthesis ,and did the the behavioral modeling ,moreover we need links and books about advanced topics like post synthesizes simulation, mapping, Design constraints, static Timing analysis and place and (...)
Dear all, I am now to have the Timing analysis for my design along with place and route using Xilinx ISE. Since I am learning I have few problems in understanding few things. 1- What input Jitter time should I place for my clock. How can I know what jitter time my clock has...? 2- Also can I save (...)
Well prolem is what is mentioned. In my code i read 32bit data from a file, and store them in a ram of 8 bits datas (and 4 more times indexes.) In behavioral it works perfectly. But in place and route my ram stays always in 00000000. The result it the same either if i implement my own ram or create one (...)
Hi all , I am doing place and route on flat full chip for the first time.Please provide any material on this . Previously I have worked on partitioned blocks.But with full chip , there many new things to consider ( PADS etc.). I would like to know what must be done/not done at chip would be helpful if any study documents is provided.
hi I want to make KL- algorithm related tool, which will helps to solve place and route problem like wire delay... I want to place GUI in form of CLB o/p. without applying and after applying algorithm
help me please my project in VHDL code use the Fixed point package by David Bishop and i use the spartan3E board and when make post place and route simulation the below error occur: ERROR:HDLCompiler:1316 - "G:/project/VHDL/final_with_PAR-simulation/netgen/par/main_timesim.vhd" Line 28014: Index value (...)
help me please in my design this error appear in place and route step tha target device is spartan 3e and the ise is ise14.1 error: place:120 - There were not enough sites to place all selected components. Some of these failures can be circumvented by using an alternate algorithm (...)
Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be (...)
I have a small design which includes a macro RAM block and am trying to perform the place and route in IC Compiler. Is there any particular guidelines that I need to follow. I create a floorplan and then fix the RAM macro which seems to be required before doing the placement. When I (...)
Hi everyone, I am doing the layout of a chip, whose main part is a network of 100 identical modules (just like a memory). I have the layout of the module and I put the pins carefully so that the 100 instances can be put next to each other. The communication between neighboring instances are realized by abutment without routing. But all the inst
I'm currently developing a cpu with ooo execution. I was wandering how would place and route tools arrange the data bits in the reservation stations. Will it be 1)a0a1a2... b0b1b2... or 2) a0b0a1b1a2b2... ?