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37 Threads found on Astro Place And Route
What's the difference between timing-driven and non-timing-driven P&R in astro?
I am learn astro , i just read manual of astro,i want to learn the idea of backend not just backend tools, can you intro a book to me, thanks.
When we after place and route by astro, we generate a netlist file, and the netlist file have some assign command, such as : assign cpu_rst_n = rst_n how to remove such assign command ,please help me.
How to place dual height cells in Synopsys astro ?
I am just a beginner in astro. Please can anyone guide me how to get the netlist for the design and then load it in astro tool for place and route.
actually IC Compiler is more and more expensive than DC. it include physical compiler,Jupiter,astro. combine with DC to form rtl-to-gdsII flow.
Is there a way of reporting the area per block/module in astro? The place and route summary does not provide this information. TIA
Dear guys, I am using the astro place and route tool. I need your help to complete the scan chain optimization process. Before the placement process I delete the chains, and that?s ok. But before the optimizations of the chains I need to run this command (...)
Hi friends, What is the cell view and frame view of a design and what is the difference between them? How can we create cell view or frame view for a design in astro and in SOC Encounter? Please help. Thanks, Sowmya
Hi, I need to generate a two level hierarchical design (chip + block) in astro. After place and route is complete for the low level block, I need to generate a timing (TIM) view by creating CLF. After setting up the timing I generate the CLF using 'astTimingModel'. However, I noticed that the input delays are missing (...)
hi,all Apollo II is now astro. and have many new features. Se is out of date. and who can share training material or tutorial about astro? Thanks. "astro Recommended Methodology", the slides from SNUG 2004 tutorial.
Anyone have experience on the performance comparation of timing closure, physical implementation flow: 1, JupiterXT floor plan + physical compiler placement + astro route 2, netlist -> Jupiter floor plan + astro timing driven plance and route 3, netlist -> SOC encounter floor plan, (...)
Magma is place and route tool, heah to head compete again Synopsys astro It's not only P&R tool, also have RTL synthesis, floorplan, physical synthesis, STA parts, it holds all tools that do RTL2GDS flow. equl synopsys DC+PhySyn+Jupiter+astro+PT
No, Mentor doesn't have tools doing place and route. Only Synopsys and Cadence do. Apollo, astro, Silicon Ensemble etc ...
i think u can go to can use an edif netlist and do standard cell place and route or u can also use the block place and route feature.u can also use cadence soc which does p &r or synopsys astro to do p and r (...)
asic flow : RTL simulation ---> RTL synthesis ---> P&R tools: RTL simulation : cadence's NC-sim or synopsys' VCS etc RTL synthesis : synopsys' DC P&R: candence's SE or avanti's apollo or astro etc others: CTS , Prime Time etc
hi tahar, the steps 6,10,11,12,13 are needed only in ASIC flow. You cant learn them with Altera FPGA and Quartus tools. You need process library and very expensive EDA tools for this purpose. eg: Synopys Design compiler,Physical compiler, astro, StarRC.. Proabaly ur university has a license to these tools .. check them out... the (...)
1. place (Either in astro or Physical compiler) 2. CTS 3. route
if you have access to comercial tools such as synopsys, you can use synopsys design compiler to synthesize your equation into netlist and then read it into synopsys astro layout tool and do a quich place and route. For simple designs you don't need to worry about clocks and (...)
what is soc encounter please, I would like to benefit from the discussion thanks Salma:D It's a Cadence tool for place and route Synopsys has Apollo, astro Magma has Blast Fusion
ya.. he is right.. mostly PKS is used for logical optimization and inserting constraints.. we dont use place and route mostly.. Encounter is better tool for placement and routing. it is equally compared with astro..
Hi all, My team will achieve a analog divider using analog method through cadence simulation. My question is who know the flow from schematic to achieve auto P&R? That is to say, schematic designer will give me a schematic, how can i achieve the layout using APR tool like astro or Encounter from schematic? For the schematic is much huge, using c
astro is easier to learn, and astro has close relation with DC, that's helpful for timing problem solution. Hi, can anybody please tell me which place and route tool is easier to learn in short time period..(magma blastfusion or soc encounter)
1. MAGMA...... 2. astro...... 3. SOC ENCOUNTER.....
Earlier Synopsys had astro as their PNR tool, but now they've launched IC Compiler for their 65nm process & beyond ICC uses Zroute as its router engine which is a multi-threaded router, belive me life in 45nm is not easy & ICC have shown very good routing results as compared to their earlier router, it gives (...)
In STA say in PT we use Back-annotated SDF where in in P & R Tool we extract the SDF once detail route is completed. So.. analysing the RC Delay and process variation effects are more accurate in PT as compared to astro or Blast Fusion etc.. Hope this helps.....
Hi, I'm working on place and route of a design in Synopsys IC Compiler. I have gate netlist from DC Compiler and I'm getting the following error while running "read_verilog" in ICC. ***** Verilog HDL translation completed! ***** Elapsed = 0:00:00, CPU = 0:00:00 Hierarchy Preservation is turned ON The (...)
I used encounter to do place and route, then I get the timing files and .spf and .spef files of the layout information. But I prefer to have .rspf (reduced standard parasitic format) file because I need to know the pi model of every node. How to get it? I checked rcOut. It doesn't (...)
Dear all, I am using Synopsis astro to place & route my netlist (with scan chain). Since my scan chain order should be remained for some optimization reasons, I could not let astro to change my scan chain order. However, the total wire length will be awful. I have tried "Trace Scan Chain" & "Optomize Scan (...)
Transition Fixing Question: What commands are available to fix maximum transition violations in astro? Answer: The following are some commands that can be used to fix maximum transition violations in astro. Transition fixing can be concurrent with fixing setup, hold, capactiance (...)
Hi, Do you have astro log file ? The information isn't enough. Best Regards, Chyau
You read-in the file you created using auECOByChangeFile. To get the full syntax of this command in Apollo or astro type help auECOByChangeFile.
Dear all, I have only 1 clock(period is 50ns) in a test case,when I running CTS in astro,the tool will report a massage of "Overlap Removal Engine Terminated", and the insertion delay of clock is quite large-- ~11ns, skew is 0.2ns, but timing is OK after question are: 1>What does the massage mean? the place area is not enough for CTS o
Hi,guys I have got confused with how to assign metal layers and how to auto place & route in the physical design tool astro. is there any flow should be followed for doing physical design in astro, Could you give some details or link? thanks in advance roy:|
Apollo is now called astro, and SE is also good.
hi, I am beginer of layout. As I know, the basic layout is draw each transistor by youself.But now,we have some EDA tools such SE/astro,this tools can auto P&R.