22 Threads found on edaboard.com: Aucdl
In aucdl netlist generation, I want to generate the netlist shown below
XI1 net16 gnd! / rnpoly2 rl=20 rw=2
.SUBCKT rnpoly2 MINUS PLUS rl=2 rw=2
RR0 PLUS MINUS 190*rl/(rw-6.2e-3) $ $W=rw $L=rl
But the generated CDL out file (File->Export->CDL) is
XI1 net16 gnd! / rnpoly2 M=1
.SUBCKT rnpoly2 MINUS PLUS rl=2 rw=2
RR0 PLUS MIN
ASIC Design Methodologies and Tools (Digital) :: 15.12.2010 02:57 :: paulux :: Replies: 0 :: Views: 1050
Do you want to convert netlist for Hspice or generate Hspice netlist from Cadence enviroment. If second you can use aucdl. You can adust CDF parameters for Hspice syntax.
Analog Circuit Design :: 29.03.2004 08:47 :: Fom :: Replies: 4 :: Views: 5707
please use CDF to edit the aucdl view of the cap and add parameters of width and length
Software Problems, Hints and Reviews :: 26.03.2006 07:07 :: vibren.chao :: Replies: 2 :: Views: 1617
When I use "hspice" to simulate my inverter,it can pass!
Then I use "awaves" to see my input/output waves, the output wave is zero!
What's wrong with my netlist?
This is my netlist.
* aucdl Netlist:
* Library Name: Inverter
* Top Cell Name: inv
* View Na
Analog IC Design and Layout :: 15.09.2005 10:12 :: shaq :: Replies: 6 :: Views: 1077
pls use CDF to edit the aucdl view of inv and nand3 and add the params needed
ASIC Design Methodologies and Tools (Digital) :: 26.03.2006 05:42 :: vibren.chao :: Replies: 2 :: Views: 1520
Because the simulation information in the CDF of cellview res doesn't define L and W.
Open the CDF form, fill in the form with the library name and cell name of res, and change "Effictive" to "Base"
Open the "Simulation Information" section, and select the aucdl simulator. Add l and l to the instance Parameter field.
Analog Circuit Design :: 08.11.2006 23:48 :: Hughes :: Replies: 2 :: Views: 1925
you need to have the hspice version of the resistors in the cdl ...if not you can create one and extract with the resistor available with you.
what do u mean by having the hspice version of the resistors in the cdl?
is it due to the properties if the view of aucdl of rppolywo? if so, what can i do?
Analog Circuit Design :: 08.12.2006 13:32 :: newbie_1 :: Replies: 2 :: Views: 2344
The prolem is finding a way to export CDL netlist contains parameters defined by myself of specified model.
Take resistor for example. By deafult, a resistor in a CDL netlist have a form below:
R1 VDD VSS 1K RP
It means a resistor connect to VDD and VSS has a 1K ohms value and model name is RP.
Now I need 2 additional parameters
Software Problems, Hints and Reviews :: 03.09.2007 02:49 :: starrinesss :: Replies: 1 :: Views: 1687
but actually, there is a view named aucdl in analoglib for every vsource, such as vdc, vsin ..so, that's the config of cadence?
Software Problems, Hints and Reviews :: 11.10.2007 08:45 :: starrinesss :: Replies: 6 :: Views: 1403
I used to cdl extraction, I want to modify some paramneter and model name, Bu ti cannot.
In the net, I can find some way to modify aucdl. But This is not work for me.
In my case, I have only 4 view component in the one cell, cdl, lvs, symbol, verilog.
"cdl" is the key to extract cdl netlist. But I don't know how to modify it.
when I ope
Analog Circuit Design :: 12.11.2007 19:09 :: 020170 :: Replies: 2 :: Views: 1275
How did you make your mosfet Cdl export?? Did You get problems like error: Netlister: unable to descend into any of the views defined in the view list :' aucdl schematic'??
Analog IC Design and Layout :: 25.02.2008 18:23 :: calliste :: Replies: 1 :: Views: 988
in cadeance enviroment, in cell view, there are differenct view available.
spectre view, verilog, calibre, aucdl
what are the difference between the views and what are they used for.
i only know spectre is used for analog simulation
verilog for digital
what is calibre and aucdl used for?
Analog IC Design and Layout :: 22.01.2008 03:27 :: surreyian :: Replies: 2 :: Views: 1038
You should define these parameters in inverter's CDF, and list the parameters in the simulator information section for aucdl.
Analog IC Design and Layout :: 26.03.2008 10:01 :: Hughes :: Replies: 2 :: Views: 715
I am trying to run lvs on a schematic with an instance of a block which does not have schematic view. It has layout+symbol views. However, the schematic is in a .cdl file. Looks like cadence cannot generate the schematic netlist because :
"Missing or incorrecto master.tag in library CUSTOM_STANDARD_CELLS cell INVX1 view aucdl schematic"
ASIC Design Methodologies and Tools (Digital) :: 22.11.2009 03:41 :: mhaghaed :: Replies: 1 :: Views: 1238
Usually where do people find the documentations to understand those parameters in, say, a aucdl spice netlist?
Anyone know what "nf=" in a MOS instance in the netlist mean?
In Calibre LVS, I have a MD(pfet) of w=2u and nf=1 from layout, but a MD(pfet) of W=8u and nf=pfolds from the schematics (pfolds = 4); this make me guess that "nf=" someho
ASIC Design Methodologies and Tools (Digital) :: 10.07.2010 11:36 :: zhipeng :: Replies: 3 :: Views: 1735
I'm late but couple remarks anyway:
As said above the problem could be in the pin order of subckt definition/call.
- if you are using Cadence schematic view to the netlist extraction for Calibre you should be so careful with the subcircuits CDF properties like pin order. Try to check if this property is the same in the CDF and symbol. Otherwise i
Analog IC Design and Layout :: 14.03.2011 18:28 :: sdedov :: Replies: 9 :: Views: 1399
first of all make sure that this is not an actual error that escaped the previous version of the rules, if the layout pcell is actually a match for the schematic symbol then verify which netlist (layout or source) is not correct.
If it is the source, then change the CDF of the aucdl simulator, which is used by Calibre for LVS netlistin
Analog IC Design and Layout :: 24.06.2011 01:34 :: dgnani :: Replies: 7 :: Views: 1423
(1) If I have device with multiplicity > 1, I have to generate CDL netlist and use LVS CDL mode. If I use VLDB mode, there will be error indicating multiplicity problems.
Yes this is in effect unfortunately,i encountered such a problem with IBM cms9flp last avoid CDL netlisting and respective type of LVS
just use the bus n
Analog IC Design and Layout :: 12.10.2011 04:42 :: jimito13 :: Replies: 8 :: Views: 844
1. Make sure you are using the updated rules and PDK
2. Sounds like - this resistor got extracted as a generic device - maybe instead of extractRES, extractDevice is used - else, got transformed to a generidDevice by other techniques , in case there is an already available bind.rul [maybe they
Analog IC Design and Layout :: 22.11.2011 18:02 :: sat :: Replies: 1 :: Views: 617
I need to incorporate a few custom designed transmission lines and inductors in to a TSMC 65nm tapeout. I found a document from another TSMC pdk about using Assura ?blackboxcell option to do LVS and RCX. The basic procedure is that you copy n2port element into the PDK lib and name it as a new cell (for example n2port_d1). Then copy sy
Analog IC Design and Layout :: 01.05.2012 19:04 :: snaildr :: Replies: 1 :: Views: 458
I am trying to extract a cdl netlist from CIW of a schematic of a mixed-mode circuit, i.e. containing both analog cells ("schematic" views) and standard cells ("cmos_sch" views).
the netlist extraction fails, because in my switch view list only "schematic" views are listed, so when the extractor arrives to the symbol of one of the st
Electronic Elementary Questions :: 16.12.2012 16:31 :: mailinutile2 :: Replies: 0 :: Views: 472
First of all, thank you.
I can ensure all three things.
When I add NMOS transistor n18e2r,some warnings appear:
*warning* ddMapGetFileViewType: You are trying to run a CDB executable on an OA library file "symbol.oa".The file is in library "smic18ee" in cell "n18e2r" in view "aucdl". You must run an OA executable to use that library file
Analog IC Design and Layout :: 24.01.2013 20:35 :: huihuicn :: Replies: 3 :: Views: 312