10 Threads found on edaboard.com: Aucdl
I found this in the Calibre Interactive manual; as you are using aucdl, perhaps it will help:
"When using aucdl views, si once again reads the si.env file, but also checks the .simrc file to see what variables are set. If the variables cdlSimViewList or cdlSimStopList are set, they overwrite what you specified in the si.env file. If they are the sa
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-16-2016 16:31 :: slizak :: Replies: 7 :: Views: 423
What is the difference between aucdl, aulvs and create cdl settings in PVS - LVS(schematic input section) tool.
Please explain if any idea..........
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-25-2015 01:47 :: bhanuk :: Replies: 1 :: Views: 408
In aucdl netlist generation, I want to generate the netlist shown below
XI1 net16 gnd! / rnpoly2 rl=20 rw=2
.SUBCKT rnpoly2 MINUS PLUS rl=2 rw=2
RR0 PLUS MINUS 190*rl/(rw-6.2e-3) $ $W=rw $L=rl
But the generated CDL out file (File->Export->CDL) is
XI1 net16 gnd! / rnpoly2 M=1
.SUBCKT rnpoly2 MINUS PLUS rl=2 rw=2
RR0 PLUS MIN
ASIC Design Methodologies and Tools (Digital) :: 12-15-2010 02:57 :: paulux :: Replies: 0 :: Views: 1580
Usually where do people find the documentations to understand those parameters in, say, a aucdl spice netlist?
Anyone know what "nf=" in a MOS instance in the netlist mean?
In Calibre LVS, I have a MD(pfet) of w=2u and nf=1 from layout, but a MD(pfet) of W=8u and nf=pfolds from the schematics (pfolds = 4); this make me guess that "nf=" someho
ASIC Design Methodologies and Tools (Digital) :: 07-10-2010 11:36 :: zhipeng :: Replies: 3 :: Views: 2508
You should define these parameters in inverter's CDF, and list the parameters in the simulator information section for aucdl.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-26-2008 10:01 :: Hughes :: Replies: 2 :: Views: 973
in cadeance enviroment, in cell view, there are differenct view available.
spectre view, verilog, calibre, aucdl
what are the difference between the views and what are they used for.
i only know spectre is used for analog simulation
verilog for digital
what is calibre and aucdl used for?
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-22-2008 03:27 :: surreyian :: Replies: 2 :: Views: 1344
How did you make your mosfet Cdl export?? Did You get problems like error: Netlister: unable to descend into any of the views defined in the view list :' aucdl schematic'??
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-25-2008 18:23 :: calliste :: Replies: 1 :: Views: 1267
I used to cdl extraction, I want to modify some paramneter and model name, Bu ti cannot.
In the net, I can find some way to modify aucdl. But This is not work for me.
In my case, I have only 4 view component in the one cell, cdl, lvs, symbol, verilog.
"cdl" is the key to extract cdl netlist. But I don't know how to modify it.
when I ope
Analog Circuit Design :: 11-12-2007 19:09 :: 020170 :: Replies: 2 :: Views: 1599
but actually, there is a view named aucdl in analoglib for every vsource, such as vdc, vsin ..so, that's the config of cadence?
Software Problems, Hints and Reviews :: 10-11-2007 08:45 :: starrinesss :: Replies: 6 :: Views: 1749
Because the simulation information in the CDF of cellview res doesn't define L and W.
Open the CDF form, fill in the form with the library name and cell name of res, and change "Effictive" to "Base"
Open the "Simulation Information" section, and select the aucdl simulator. Add l and l to the instance Parameter field.
Analog Circuit Design :: 11-08-2006 23:48 :: Hughes :: Replies: 2 :: Views: 2319