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27 Threads found on Avinash
but after simulation it shows warning : NF is infinite"Very natural result. I think noisetemp=-273.15 = 0K, and it does not add noise to input portCorrect. so thatswhy i am not getting proper result.Simply you can not understa
can you please tell me about ET analysisEnvelope Analysis, that is, time variable Harmonic Balanced Analysis.
If somebody have documentation then please help me Here's an (old) LNA RF workshop instruction by Cādence: 126956 If you've got a Cādence account or license, I'm sure you can upload the associated views and models.
Hello, I have made a PCB design and generated .drd files, How to import these files to AWR Microwave Office ? Regards, avinash
thanks avinash.kashyap your posted cheap mobile charger schematics based on power transistor 13001 (NPN) has pulled me here while searching on net for the circuit diagram of a nokia charger model AC-3 ( approximately same as your attachment) What I am doing from this chrager is I am trying to drive three high brightness white LE
avinash, Well tap: contact ponits which are heavily doped : A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent latchup. D-Cap: This cells are usefull to reduce voltage peaks tie cells: available in verilog netlist which are nothing but cells with one of their ports fixed at 1(VDD) or 0(gnd) and f
Hi avinash, Wire spreading is one of the most effective solutions to reduce bridging fault, hence reduce yield loss. It relates to a new physical design t/c that is able to increase the spacing between metal wires in the layout effectively and efficiently without violating any design rules. Also helps in reducing the dummy metal fill It is d
Hi, Could anybody please provide me material on Slotlines and Finlines, or any good ppts on these topics with neat figures and explanations ? Regards, avinash
hi every body, i m back after a long time. Now i ve a doubt in implementing this block into a practical circuit for implementation. Can any body work out this for Regards, avinash.S.
Hi Friends, What is the meaning of Reluctance literally and technically? Regards, avinash.S.
Hi Friends, What is the relaationship between the BH curve and the curve between Induced EMF and Field current. Regards, avinash.S.
Hi Friends, Please tell me about the MULTICHIP MODULE. Regards, avinash.S.
Hi Friend, Please refer Regards, avinash.S.
Hi Friend, Refer "Digital Design" by "Morris Mano" Prentice Hall of India Publications. Regards, avinash.S.
Hi Friend, So that the magnetic field in the air does not get weak. Regards, avinash.S.
Hi Friend, Refer to 1) Electronic Communication Systems Fundamentals through Advance By Wayne Tomasi. 2) Advanced Electronic Communication Systems By Wayne Tomasi. Regards, avinash.S.
Hi Friend, Submit your resumes to the following sites Regards, avinash.S.
Hi Friend, With this info we could not help you. Please say the application in which you are going to use it. and say at what load it is going to work. Regards, avinash.S.
try ti use iy may be
avinash bhai, just sweep the common mode input and check ur gain. the range of CM which is meeting ur gain spec is ur CMIR. PS: i think u shd be polite with assembly. he was trying to help u. avoid using the words "u r wrong". u can use better words to put ur arguments..
Hi puyeng, As avinash said, the +ve i/p is fixed at analog ground. In this case, it should be the common mode voltage which should make the input transistors stay in saturation. Hope it helps you^_^ regards, jordan76
suppose my opamp has open loop gain of 100dB and UGB of 5MHz.if i use this opamp as an unity gain amplifier,what would be the bandwidth of signal it can handle?and how? thanks in advance. The bandwidth will be equal to the UGB in a configuration as follower or buffer, this in the condition that your feedback factor is one
from gregorian i read that for SC circuits the UGB(w0) of opamp should be greater than 1/Tsh. w0 > 15/Tsh Tsh is the charging discharging time of load. Tsh=1/(2f),where f is clock frequency. now my question is if my clock is 1Mhz,w0 comes to be it not sounding strange. please help it depends on ur spec. o
how to simulate for output resistance of opamp through spice. Just connect an AC voltage source to the output and measure the current in that source. The resistance is V/I in any analysis AC or DC or Tran. You can sweep that source and check the resistance for diferent output voltages. Bastos
dear bastos, if i have unity gain opamp.what should be its settling time in respect of UGB(open loop). moreover how do you get the factor of 0.35 in your equation. thanks for reply in advance. For the case of unity gain F-3dB = GBW. The 0.35 is taken from Paul Gray book which corresponds to the time it takes to go f
how the gain,ugb and phase margin can be calculated of fully differential help Here is the solution to your question! and if I have helped you could you please kindly click the "helped me" button and help m
i think before razavi book you should go through allen and hollberg. Added after 4 minutes: before going in circuit analysis,you must know few basic things thoughroly.current mirrors,bandgap,opamp,current source and sinks etc which you may get from allen and hollberg All these