1000 Threads found on edaboard.com: Back Drilling
what is back drilling and why is it preffered.
PCB Routing Schematic Layout software and Simulation :: 04-03-2008 01:21 :: v_kumar :: Replies: 6 :: Views: 8269
I think did an article on pcb drilling machine a while back
go to and do a search on pcb cnc or some such
PCB Routing Schematic Layout software and Simulation :: 06-26-2003 00:12 :: bluecube :: Replies: 5 :: Views: 3511
in principle it will oscillate. From end to end and back.
but variations in the gravity field (Earth is not a singular point as in exercises!) will affect this result.
PS: Are you interested in creating a hole in the Earth. Please let us so we can try get transported somewhere else. :wink:
Mathematics and Physics :: 10-20-2004 05:50 :: the_penetrator :: Replies: 6 :: Views: 1218
Could any one please help me.i want to know before start the cad what are the rules we have to follow for back plane board. If any one having details about the back plane board documents please share here... :)
PCB Routing Schematic Layout software and Simulation :: 12-06-2010 07:39 :: geekay :: Replies: 5 :: Views: 1332
Do somebody how to read back the code programed in a motorola 68HC705 microcontroller??
Thanks in advance.
Professional Hardware and Electronics Design :: 07-02-2002 12:10 :: penrico :: Replies: 2 :: Views: 2476
Home of the t*nbo drill
Hobby Circuits and Small Projects Problems :: 01-08-2003 17:36 :: MITSUKO :: Replies: 7 :: Views: 7668
APC back UPS 250i_400i_600i
APC back UPS BK300MI,BK500MI
Professional Hardware and Electronics Design :: 12-14-2003 10:01 :: mbyka :: Replies: 1 :: Views: 5047
Please help me build one drilling PCB machine use microcontroller ( ex : AT8951 ) include schematic and software.
My email : email@example.com
Many thanks !
Microcontrollers :: 06-22-2003 03:15 :: Trinh The Long :: Replies: 1 :: Views: 2340
APC back UPS 250i_400i_600i
APC back UPS BK300MI BK500MI
APC UPS 500
Stylus COLOR 600 640 660
and please use ''search'' in board because this linkk in here
Service Manuals, Requests, Repair Tips :: 01-04-2004 04:47 :: mbyka :: Replies: 1 :: Views: 4980
I constructed this machine 1 year ago. Please take a look xx with tt)
This web page is designed to present my graduation thesis; printed circuit board drilling machine which was done for Hacettepe University, Electrical and Electronics Engineering Depart
PCB Routing Schematic Layout software and Simulation :: 06-05-2004 07:28 :: electro :: Replies: 0 :: Views: 1422
I need some detailed help & matlab source code on Filter back projection.
Would you pls share it?
Digital Signal Processing :: 06-29-2004 03:43 :: siosavin :: Replies: 1 :: Views: 1230
I heard a bout snap-back in analog design but do not know exactly what it's about?
and how to treat it . Thank you very much.
Analog Circuit Design :: 07-05-2004 19:10 :: tomfam :: Replies: 1 :: Views: 1052
Hi to all,
I have just finished my design in Layout and back annotated it to capture by creating a swap file from layout after renaming components.
But I have a big problem now, all components in capture have wrong value! and part reference.
How can I solve this problem ?
Please help me.
PCB Routing Schematic Layout software and Simulation :: 09-21-2004 02:25 :: BasePointer :: Replies: 3 :: Views: 1970
this is not the trivail task at all. Having the results of a single back-to-back case is not conclusive enough - you can't get ANY info on S parameters of single balun, as Fatulent already wrote.
I can't remember exactly where, but I came accross a method comprising of having diffrent line length between the two baluns in (...)
Electromagnetic Design and Simulation :: 09-26-2004 04:47 :: flyhigh :: Replies: 8 :: Views: 2719
I am simulating a p@tch antenna in CST MWS - 5. All the results are fine.However I am unable to see the back lobe levels. In the back side it is giving a zero field !! . I have included open + add space for zmin boundary condition.Any ideas as to how I can do the back lobe calculation ?
Thanks for your time.
Electromagnetic Design and Simulation :: 09-25-2004 11:40 :: svarun :: Replies: 1 :: Views: 1803
can anybody suggest me some sites for video webcast on back end ic design?
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-06-2004 07:00 :: supra924 :: Replies: 0 :: Views: 737
The functional simulation is OK, but ERROR info appeared during back-end simulating, such as:
Time: 13043 ps Iteration: 0 Instance: /vfifft_tf/UUT/\mifft/irom3/B5\
# ** Error: d:/Xilinx/verilog/src/simprims/X_RAMB16_S18.v(507): $setup( negedge ADDR &&& EN:12932 ps, posedge CLK:13043 ps, 350 ps );
# Time: 13043 ps Iteration: 0 Insta
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-11-2004 21:36 :: shuchong :: Replies: 2 :: Views: 735
:lol: .....I am currently doing the serial communication between my hyperterminal and my PICDEM 2 PLUS board in mplab icd2,so just wonder how can i send the "ok" to my hyperterminal from my board?i tried this code
putrsUSART((rom char*)"ok"); or, if you for putrsUSART((rom char *)"ok\r");
ie. Send T
THen the proble
PC Programming and Interfacing :: 10-12-2004 03:57 :: ooicheesan :: Replies: 0 :: Views: 1042
I want to know how many formats of CNC drilling are awailable.
PCB Routing Schematic Layout software and Simulation :: 10-20-2004 01:55 :: manishyamdagni :: Replies: 1 :: Views: 907
Yes, back_end design just includes P&R.
The synthesis is included in front_end design. It gives netlist ot back_end engineers.
ASIC Design Methodologies and Tools (Digital) :: 11-23-2004 00:41 :: horzonbluz :: Replies: 6 :: Views: 931
It is so easy to do that any reputable company will have fall back if the error rate is too high on a connection.
RF, Microwave, Antennas and Optics :: 01-08-2005 21:44 :: flatulent :: Replies: 1 :: Views: 1120
Is there a precise definition of where RF front end section ends and where back end starts?
I need to write to some stuff in a report and don't seem to find this piece of info in literature.
RF, Microwave, Antennas and Optics :: 01-19-2005 20:05 :: GeekWizard :: Replies: 4 :: Views: 1921
Some time back on this Forum there was a tutorial of Inermediate Xilinx users
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-24-2005 19:41 :: sarath51 :: Replies: 1 :: Views: 669
I tried the tool back Annotate in Orcad but cannot back annotate from Allegro. Anyone knows this?
PCB Routing Schematic Layout software and Simulation :: 02-06-2005 03:21 :: s500 :: Replies: 2 :: Views: 2773
in IC DESIGN
front end means design(RTL/Schematic,
back end means APR/LAYOUT
Electronic Elementary Questions :: 03-01-2005 07:06 :: mediatek :: Replies: 6 :: Views: 1795
Does anybody have a reference that give some guideline & and rule of thumb for back-end design?
ASIC Design Methodologies and Tools (Digital) :: 02-26-2005 01:12 :: omid219 :: Replies: 1 :: Views: 643
I back annoted my architecture for xilinx virtex device using modelsim and i simulated the flattened hdl and sdf file.The output matched the initial simulation but im getting my output only after nearly 50 clocks.Why is that so?Is that an error?if so what should be done?
ASIC Design Methodologies and Tools (Digital) :: 04-03-2005 12:58 :: dynamicdude :: Replies: 1 :: Views: 886
now i only have the hex code for the 8051 and how can i convert it back to its source code (op-code) ???
Microcontrollers :: 04-23-2005 01:19 :: syteh82 :: Replies: 5 :: Views: 4029
It is the first time I use Eagle 4.14 and I am trying to cut PCBs (printed circuit boards) I had no problems generating the trace (HPGL) files but when I want to generate the drilling file I have no idea how to do it. I am running an .upl file that Eagle has called: "Mill-outlines" and it has the provision to make the dr
PCB Routing Schematic Layout software and Simulation :: 05-15-2005 13:35 :: on7tim7 :: Replies: 0 :: Views: 570
can anybody pls suggest me good,basic books for VLSI back -end design.
ASIC Design Methodologies and Tools (Digital) :: 05-23-2005 05:34 :: balu304 :: Replies: 8 :: Views: 2351
who have it
A. Amerasckera, M-C. Chang, C. Duvvury and S.
Ramaswamy, ?Modeling MOS Snapback and Parasitic Bipolar
Action for Circuit-Level-ESD and High-Current simulations?, in
Proc 34th IRPS, pp. 318-326, 1996.
Analog Circuit Design :: 04-24-2006 04:33 :: andy2000a :: Replies: 4 :: Views: 7419
How to read back a 9536 cpld if it is readback protected?Is there any way to read jed file from it?
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-14-2005 06:56 :: dsj :: Replies: 0 :: Views: 853
how to avoid back slash "\" in dc
ASIC Design Methodologies and Tools (Digital) :: 07-03-2005 03:30 :: roger :: Replies: 2 :: Views: 994
Let's first set this straight.
DC = RTL to Gates mapper (w optimization etc) + STA engine
PT = STA (powerful)
When you back-annotate SDF/SPEF to PT and still fail timing that means you have to re-synthesize. That is when DC comes into pic, NOT PT. You use the layout data to accurately model the net delays (WLM) and call it
ASIC Design Methodologies and Tools (Digital) :: 08-03-2005 01:07 :: eda_ak :: Replies: 2 :: Views: 830
When etching back a trace, what are the reasons to do Under etch (lower trace smaller than upper trace), Over etch (upper trace smaller than lower trace)
and Correct etch (lower trace and upper trace are of equal width) ?
Other Design :: 07-27-2005 06:14 :: amjad :: Replies: 0 :: Views: 1091
Could u tell me, what kind of topology is suitable in back light deisgn of cell phone using while LED driver ?
there are a lot of advistments of IC vendor for this, some vendor said that their PWM solution provide lower noise inject to the batter source, but some vendor insist there solution (PFM) is much efficiency then PWM (but the
Professional Hardware and Electronics Design :: 08-09-2005 07:22 :: Btrend :: Replies: 1 :: Views: 1416
I'm from china.I have done a back-end IC design and front-end digital design for one year.Now i want to find a job in china.Any company can provide to me a chance!Thanx in Advance!
EDA Jobs :: 08-17-2005 00:58 :: feel_on_on :: Replies: 0 :: Views: 798
Why make AC from DC and then back again? Why not just build a new front end for the PCs original PSU? What happens in the PSU is that the AC is rectified and chopped up again to drive the pulse transformer. Rewinding the transformer for 12V will save the unnecessary step and work much more efficient.
Analog Circuit Design :: 09-04-2005 17:49 :: Ante :: Replies: 9 :: Views: 1845
I could not remember how to spell but the pronouciation is like "leaf"
a format from the back-end process.
Who know that is it?
Added after 2 minutes:
It is used in back annotated information.... not "LEF"
ASIC Design Methodologies and Tools (Digital) :: 10-25-2005 23:46 :: luancao :: Replies: 0 :: Views: 466
I'm designing 12b 80M pipeline ad
and there are lots of problems........
I want a question about B.E. a/d.
i use 1.5bit resolution per stage.
and B.E. ad is 2bit flash a/d
And Can i use 3bit flash or 4bit flash AD in back-end???
If so, what's the drawback??
and if i made a 4bit pipeline,(1stage(1.5bit) + 3bit flash)
Analog Circuit Design :: 10-29-2005 18:15 :: ljy4468 :: Replies: 5 :: Views: 951
Two days back when I put ON my PC a flash occurred at the back of the CPU near the power it the fuse that has burned or anyother???
If it is with fuse can any one specify what type of fuse to be taken?
Im using AMD processor.
Service Manuals, Requests, Repair Tips :: 12-19-2005 00:14 :: mithra :: Replies: 0 :: Views: 574
I cannot back annotate from Layout.
I swaped in layout 2 gates from 2 different components of the same type.
When I try to back annotate, I receive the message:
External pin swap (U2.7 and U1.7) not supported.
The same message for other 2 pins of gate.
So, I can't annotate to capture the gate's swapping from 2 different c
PCB Routing Schematic Layout software and Simulation :: 12-19-2005 12:21 :: pavel47 :: Replies: 1 :: Views: 1271
I am conducting a small experiment on my sine wave as my desired voltage is approximately 5V but the output voltage is roughly about 6 Volts so I would like to learn how to control the output voltage back to 5 Voltage via microcontroller. Unfortunately I have no knowledge of implementing control system
Any help would be indeed appreicated
Electronic Elementary Questions :: 01-27-2006 13:04 :: Maverickmax :: Replies: 3 :: Views: 683
Is it possible to translate a bitstream (for fpga programming) back to VHDL code?
thanks for advance
This is for a research project... can you give me your opinion?
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-09-2006 10:27 :: mobile-it :: Replies: 1 :: Views: 659
hai every one,
i want know the effective design method for flyback transformer and the design conciderations.
thanks & regards
Professional Hardware and Electronics Design :: 03-25-2006 05:30 :: get2kamal :: Replies: 3 :: Views: 1465
The level of back off depends on the crest factor of the modulated signal.
Eg: pi/4Dqpsk modulation has a crest factor of 3.3dB (crest factor means peak to average value of the modulated signal envelope). CDMA signal has a crest factor of about 10dB.
So if you use a RF power amplifier for CDMA you have to operate at a power 10 dB less than its m
RF, Microwave, Antennas and Optics :: 06-27-2006 09:20 :: egemini :: Replies: 7 :: Views: 6321
If I have enough area for my chip,what is the pros and cons of back-to-back vs. NOT back-to-back standard cell placement?
Thanks in advance!
ASIC Design Methodologies and Tools (Digital) :: 04-03-2006 22:06 :: eexuke :: Replies: 8 :: Views: 1276
Has anyone managed to build a home CNC drilling Machine?
Any building plants to share?
I have read most of the cnc machine posts in the forum and found nothing interesting or easy to follow.
Please share ..
Hobby Circuits and Small Projects Problems :: 04-09-2006 16:53 :: JJFORTY :: Replies: 8 :: Views: 4836
I had a doubt while studying inverters & converters in Power Electronics. In most of the circuits, (semiconverter, full-wave bridge converter, midpoint converter) the load is assumed to be a RLE load (i.e resistance R, inductance L, & a battery E). Now, it is said that the battery E may be the generated counter EMF of a dc motor.
Electronic Elementary Questions :: 04-14-2006 22:02 :: elexhobby :: Replies: 2 :: Views: 1726
I was trying to do pros and cons of Front end ASIC design vs back end.
Can you please help me in deciding which job should I choose?
Can you tell me which one has more scope in the long run?
Which one is less likely to get outsourced to countries like India and China?
How about verification is it equally prone to outsource?
EDA Jobs :: 05-07-2006 09:41 :: kgeorge123 :: Replies: 3 :: Views: 2349