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51 Threads found on edaboard.com: Bandgap Regulator
Hello all, Could you tell me how I can increase the voltage of bandgap. Right now, the voltage operation Vin is from 2.2V to 4V. If I wanna increase voltage to 12V, how I do that ? Please show me the way to do it. Thank you so much. In the below, I attached some img about my bandgap136112
Hello everyone, I have a problem with my regulator for my bandgap circuit. The schematic is attached below. I add some PMOS diodes ( Drain shorted to Gate) in series with the R3 resistor to reduce the amount of resistance I need to put on the R3 resistor. In my testbench, I use a ideal current source as reference current produced by (...)
zeners are not efficient nor stable compared to bandgap reference diodes used in all LDO's (LM317 type and many others) Zeners must draw more than the worst case load to ensure when loaded there is still enough current to get past the knee in the zener. Then when no load, that current * voltage can lead to thermal problems for high power. So
Had you performed a reserarch ? There are a lot of informations avaliable : +++
Hello, Attached is a picture of an LDO schematic seen in the IEEE paper: A 1.21V, 100mA, 0.1uF - 10uF output capacitor LDO voltage regulator for SOC applications. The vref is a bandgap voltage (1.2V) and the resistors R1 and R2 are adjusted to deliver the desired output voltage (2.5V). The VDD = 3V The output PMOS pass device (Mpass) is made l
1) You can't. Precision bandgap references are almost always trimmed for accuracy. 2) I don't think there is any reason, other than it being a nice rounded numbers that industry partners thought was good for standardization of ADC/DAC references and regulator feedback margins. 3) Vbg = Vbe + k * delta(Vbe) will always give you around 1.2V. Low volt
Hi All, could please someone recommend me a book or a document with a compilation of basic analog building blocks in CMOS, like for example: power on reset undervoltage detection voltage regulator 0scillator bias generator bandgap etc what I am looking for is not a theory book but a compilation of different topologies, if possible
Besides Error amplifier, you need to design current bias, bandgap, OTP, current limiter.
There are two tricks for low noise voltage regulators: 1) choose one that allows you to put an external capacitor across the bandgap reference, such as LM723, NCP623, etc 2) Have enough input shunt capacitors (and maybe input series inductance or small resistance) to form a lowpass filter for any input noise above 10 KHz (where most regulat
In a power IC the bandgap and any cascoding is unlikely to be significant in the end, area-wise. It's the power devices' area. The current for a reference and housekeeping analog should not need much device width. Stacked MOS diodes and a resistor make a good enough shunt regulator, a pass follower (high voltage capable) makes a series
How to setup in laboratory to test PSRR of a voltage regulator / bandgap circuit
Hi, I want this paper, could you help me if you have? Thanks for your kindly help in advance 1. A Low Noise CMOS Low Dropout regulator with an Area-Efficient bandgap Reference SUMMARY In a low dropout (LDO) linear regulator whose reference voltage is supplied by a bandgap reference, double stacked diodes increase (...)
Since the input power is fundamentally limited I would go with a shunt regulator, right after the rectifiers. A very low power bandgap and shunt transistor. Or even just a simple FET stack (say, 3*VT) maybe with a high ratio current mirror at the bottom so you have usable drain headroom. Question is, how good and process-repeatable does
i think i need a pre-regulator circuit . tks Right. As most bandgap ICs are rather low power devices, a simple resistor - zener diode combination should do. BTW: Such questions (nothing common with Analog IC Design & Layout) should better be asked in this forum .
I have use bandgap output as the reference of the regulator. When the regulator is sinking larege current, there will be voltage drop at power net. This affect the output of bandgap, then large variation is seen from the regulator output. How can I make the bandgap output stable? PS: (...)
first you can generater the internal VDD by regulator and the bandgap can be use VDD for power supply
In conventional bandgap topologies the minimum voltage is VBE+a*VT+VDSAT It is the series path of the parasitic PNP, a kT multiplier and a PMOS regulator current output. In a non-curvature compensated band the absolute temperature coefficients of VBE and a*VT should cancel dVBE/dT~-2mV/K dVT/dT=+(1/300)*26mV so a solves to abou
Maybe your input voltage range is wide. One for voltage pre-regulator, the other for the compare value of core circuit. Typical no need the 3rd bandgap for temperature protection. BTW, OTP maybe over-temperature protection?
hi~hr_rezaee If Vref is fixed like bandgap ref. and then Driving Tr. in Opamp use pass tr. as PMOS. is it possible?
hi all! if the bandgap output, i buffer it with a opamp before connect to other circuit as reference voltage, is it fine? accuracy?
hello, everybody can somebody have the paper named "Supply noise insensitive bandgap regulator using capacitive chargepump DC-DC converter"? if possible, please send it to me. my email address is oldwulf@gmail.com anyway, thanks to all friends. Supply noise insensitive bandgap regulator using capacitive chargepump (...)
Can I use a voltage regulator before a bandgap to further inprove PSRR? In this case, it create a loops between bandgap and voltage regulator, where bandgap supply reference voltage to regulator. Anyone have experience in this? Regards.
You may use auxiliary linear regulator for bandgap voltage reference.
Try to design internal a low voltage regulator for bandgap circuit. It will improve line regulation.
Now I use high voltage process, Vds can reaches 30V, Vgs can't exceed 5V, then my previous method using high voltage bandgap, OP, and power mos to generates inner votlage 5V is impossible, can anyone give me some instruction or suggestion of generating inner voltage 5V, thanks!
Hi Everybody, I think I have to make it straight for everybody. I have designed Opamp, bandgap, regulator, Rectifier and ? with HSPICE and also checked the simulation with Spectre, and silicon results. As you may know, BSIM models are the most accurate models exist for MOS transistors. These models are for HSPICE. As matter of fact, HSPICE is
The output should not change with the input for an ideal regulator -- that is why it is called a 'regulator' anyway. The limited line regulation can come from different sources: bandgap voltage (or reference voltage) line regulation, error amplifier finite DC gain (but NOT the offset), etc. You may need to check it more thoroughly with (...)
what is the best books/papers on bandgap voltage reference? please give me some advices, thanks.
For any DC-DC converter, there is a feedback loop to sense the output voltage and apply either more or less input voltage in order to regulate to the desired output. Usually just an op-amp comparing an internal reference voltage (bandgap voltage) to a feedback pin (FB). A linear regulator uses a pass device operating in the linear region - it a
CMOS shunt regulator with bandgap reference for automotive environment IEE Proceedings - Circuits, Devices and Systems -- June 1994 -- Volume 141, Issue 3, p. 157-161 thanks
bandgap generate output that is independent of temperature. It is very important in analog design as a reference voltage. For example, in voltage regulator design, common mode feedback , you need a reference voltage constant across temperature.
Increase your startup helper current injection and switch it off after the bandgap reach near its full voltage.
I think you can try unit gain bufeer , But the unit gain buffer need to drive low load (It is depand on your circuit) . The input is 1.25v form bandgap circuit . I think it is better .
What is the difference between a voltage bandgap and a voltage regulator ???
Yes, use R load to test load regulation of bandgap. Just the same way as regulator load regulation test. The value of R load depends on the current available for sinking/sourcing without affecting the accuracy of the output voltage.
What's the meaning of "4 bias voltages"? Do you mean four independent voltages? if it is, you can just use regulator or bandgap.
You can consider the low voltage bandgap: "a CMOS bandgap reference circuit with sub-1v operation"
low quiescent current LDO regulator how low current ?? 1ua or 0.1ua ?? we can easy design OPA or bandgap work on < 10ua .. if you want let you LDO work on < 1ua , maybe bandgap have some problem . for small current and Vbg keep 1.2v you need large "resistor" in chip .
A. Internal high voltage management: a. Charge pump: positive and negative b. regulator c. Bias generator (voltage bias: bandgap reference, tyipcal; current bias: current mirror) d. Voltage boost (for read operation) e. Current limitter (avoiding latch-up) B. HV switches -- for well-bias control and WL voltage switch C. Sensing pat
hello every one, i need to design a low noise LDO linear regulator whose noise is lower than 20?Vrms(10~100KHz). i have adopted a low-pass filter to filter the noise of bandgap voltage, and i eager to know how to reduce the amplifier noise. how shoule i do and especially, what structure can i choose. thanks in advance!
Specs for design: CMOS tech forced to use bandgap and a ballast to build up the simple regulator input 5V+/-20% output 2.5V +/=1% current <2mA Ro < 0.05 Ω Robg < 1 Ω temperature coeff kT < 500 ppm / °C Any design doc or school project report will be very helpful. thx for share!
When I simulate a convential bandgap voltage reference circuit by using Hspice, transient analysis is need or not? why? I already had a dc sweep analysis. thank you.
I guess this is happening during chip power up. When the VCC is ramping up, internal regulator is not enabled. So the VCC will be connected to the bandgap. After that, you want to hot switch the bandgap from VCC to your regulated voltage source. Big "back to back switch" can help you to do the switching. It can eliminate the forward (...)
hello all: i am designing a vco, the structure is regulator(bandgap+op), V-I converter and CCO, but i found that even with noiseless power supply, the jitter of the vco is much more worse than design the vco without regulator(only v-i converter and cco). i am really confused. wo should i think about the phenomena. thanks (...)
I can offer the following idea: a high input voltage low dropout regulator with output voltage about 1.6 ... 1.8 V and low input voltage bandgap. What technology you will use? 0.6u, 0.25u, 0.18u or others?
some LDO asic only work on < 10ua .. how to design it ? regulator need OPA + bandgap .. if bandgap total working current < 1u , cmos process design use BJT model (parasic device) can be use under such small current ( maybe BJT current < 100na ) ?? I don't think FAB have good spice model for BJT device ..
use bandgap and OP to make a regulator, then you can get a stable, low noise voltage supply. you can get high PSSR double voltage supply is not a good choice i think
1. direct use HiV mos + BJT but as I know some process BJT model have problem is HV 2. use 2 step regulator 40v -> ~12 then use 12v device make bandgap is easy than 40V cmos 40V CMOS L is very large ... for good Line regulation need Long L what process in your design   UMC/TSMS/VIS or other ??
Gurus, I need to design a voltage dectector circuit and the supply voltage range is 1.6v~6.0v.But I have no bandgap reference voltage as my reference, can anyone give a hint or some reference sources? One more thing to add: suppose the voltage range is roughly divided into three parts: 1.6v~2.5v,2.5v~3.8v,3.8v~6.0v by two threshold,
Hi How about your LDO speci ?? I ever design a LDO use bandgap + OPA buffer and driver "large Pmos " , becuase Pmos is large and R_on samll V_drop < 1v .. but this chip current < 1A