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61 Threads found on edaboard.com: Bandgap Startup
Hi Guys, I have a concern on the bandgap start up circuit design. I understand the need of a start up circuit in the bandgap design. But I'm not very sure, or need your feedback on the simulation outcome that Im observing. With the startup circuit added, the bandgap core output voltage is able to settle around 150us when (...)
This is your fundamental "box" for designing startup circuits. The startup current needs to be large enough to boot the loop in the worst case, and it needs to be low enough to not bother the loop setpoint in the "best" case. PVT can make this a thread-the-needle exercise especially if you want to stay simple (like diode-steered resistor pullup)
I would suspect that the Schmitt threshold is too close, but on the wrong side of, the bandgap output voltage and yet the startup circuit cannot be removed without the bandgap core collapsing. The startup looks too simple to me. Start with breaking that feedback loop and see where the startup can be removed (...)
Hi All, I have two subcircuit for a bandgap reference circuit design. One is PTAT and one is CTAT. When I originally designed, I put these two subcircuit seperately in different cellviews and both of them are working well. The power supply of both circuits are the same. But when I copied and placed them in the same cellview, and just make their
Hi all, I am designing a bandgap reference circuit, which i have tested using Cadence Spectre. The circuit works well and converges to the designed operating point without a startup circuit, which wont be the case, when fabricated. The problem now is, if i design a startup circuit, i dont know how to test its working, as the circuit without (...)
The problem with all capacitive-based startup circuits is that it's not robust. You may have to simulate not only slow startups, but also brownout conditions. It may give a lot of headache if you have very strict criteria on your bandgap startup.
Hi Guys: I am working on a bandgap circuit for a internal regulator in a DC-DC converter. The core circuit is a simple BROKAW bandgap circuit and i need a startup circuit for it.The problem is the input voltage is from 5~23 and the high voltage MOSFET my process provide have a max Gate-Source voltage(Vgs) of 5,while the max (...)
Hi Friends I am designing a bandgap reference circuit in .18um process shown in figgure. my objective is to get a stable output voltage with least temco as possible when i simulated my bandgap i got 1.125v as the voltage which has least temp co but usually 1.25v is the desired bandgap voltage if i set my output voltage to 1.25v my temp co (...)
Some bandgap structure will have three operating points.
Will the bandgap ref work well if I add 2 cap and 2 res in the circuit? startup without any problem? stability for work?
Hi all, Could someone help me with the startup problem in my bandgap circuit? I have startup problem for lower temperatures .i.e if i simulate ckt for weak -40. I get output waveform as attached .. Thanks in advance rampat
hi all, i wanna do some research about the startup circuit of bandgap, please help me 1:how to analysis the numbers of the stable operating points of the circuit. as far as i know, some bandgap circuits have 2 stable operating points, some circuits have 3 stable operating points. I wanna know are there some methods to count the number
Hi All, I have a bandgap reference circuit, which works fine in simulation. (Both DC temperature sweep and transient sweep give satisfactory results.) As this is my first fabrication, I am a bit concerned about the start-up and also the stability of the circuits. startup the startup circuit I used is the one based on capacitor. (...)
hi. id like to know the causes of output fluctuations of a bandgap with startup circuit..and how to solve this problem. what are the things to consider when designing startup circuit for a bandgap?like do i need long channel device or minimum length. how to design W/L for a startup circuit? is there a (...)
Hi For 1.5V supply I would not use the classical bandgap approach The classical approach will show some serious problems in the low-temp/slow corners, especially during startup ... Look out for some papers about low voltage bandgaps. The basic idea there is, that you add a ptat and an iptat current. THis current is injected into a (...)
please show your bandgap schemtic
Hello, Designing a sub volt (Banba Type) bandgap. I am having problem that my low frequency PSRR is say -40dB and then the PSRR rises to -29dB at say 10MHz and then again starts reducing. Need to improve this peaking in PSRR curve. Please help on this. My understanding is: 1) DC PSRR is governed by the loop gain and the Resistor devider ratio
Hi this bandgap the startup circuit works fine untill I apply an offset (vos) to the opamp. With a positive offset, all it's ok but witha negative one the loop becomes open! Why does it happen? Any suggestion to avoid this bad behavior, please? TIA, CBs
Hello bharatsmile, Limitations of this startup that I can think of: 1. it is always on because when vdd is up, the diode connected nmos is going to have a vgs across it. The pmos connected to V- will have a high Vgs across it. 2. the bandgap voltage is going to have an error term because the startup pmos transistor has current that (...)
hi, would you pls suggest a startup circuit for Conventional BGR,which consumes less current(in nA) and improves the response of the bandgap? Thanks
hi does self biased BGR requires a startup? THanks
Hi.. can any one tell me the simualtion setup for finding out the stability of the BGR? Pls find the schematic i used.... Thanks
Hi there, I am a analog behavioral modeling engineer. I am developing analog power supply behavioral model now. I will develope "bandgap reference model" by using AMS language. During the development i wish to verify the following charasteristic: 1. start-up characteristic: Vout vs Vin 2. load characteristic: Vout vs Iload 3.temperature ch
1.what is your initial seting for your circuit or why you do that? Becuase you have an inable pin? 2. The mean state is a stable state and in this state the VBGR will not start ever without start-up circuit. I designed bandgap voltage reference and startup circuit for it. I have read topics about BGVR and startup. I verify start
A simple test, simple to automate, is that your circuit should be enter the normal mode from any node voltage combinations. If you have 9 nodes you have possible 512 states where either VDD or 0 is used as initial state. Some of the state lead to high currents or some very short time responses. But there are possible states where is takes very l
hi i attch the bandgap circuit. Do we need start up circuit for this bandgap and why? thanks
hi guys., how to troubleshoot start-up issue in bandgap. any relevant document or journal will help full.thank in advance.
you can search and get many resources about bandgap references here.
Hi all I've a question about bandgap reference circuit. In attached figure, left side is bandgap core & right side circuit is my question.... I heard that right side circuit prevent saturation when start-up. But I don't know further. Anyone can help me?
is there any way that i can check functionality of my bandgap circuit in SPICE simulation without using start up ckt. And is start up ckt always required for bandgap functioning???? also suggest some good start up circuits fro bandgap references????
Input noise is useless, because it is get from output noise devided by transfer gain from power to output. From your simulation, the gain (of psrr) is 60u200m=1/3000 or -70dB. For bandgap, we only need to care output noise.
OK give me also a try: 1. Use a bandgap VBDG=1.2V 2. At chip startup sample the ratio of VDD/2 to VBDG by using a opamp and a ladder network. 3. Use a comparator which compares the scaled VBDG with VDD/2 4. Use binary search to fix the scale factor 5. Finish the initial calibration. So the scale factor multiplies the VBDG to V
hi,all I have a doubt about trimming of bandgap reference which is showed in attached schematic.The R2 and R3 should be trimmed at the same time or only to trim R2 is enough. For trimming convenience, i tried to combine the M1&M2, but the perfermances were difficult to tradeoff nice. By the way, the opamp's bias current was cont
Lets see.... The startup generate initial bias current ~(VDD-Vth,p-Vth,n)^2 seems ok! But the reg opamp of the kT-generator see the impedance of the inital startup bias generator. So use ideal buffer with some real output impedance to isolate the effect. I suggest that oscillation if happen because of the impedance vanish for zero ohm and ini
Thanks all the friends to reply to my question. The problem i stated above have been resolved.I added a capcitor between power supply line and the output of opamp, in this way, the voltage at two pmos transistor's gate will not be so sharp, additionally, i reduced the total capacitance at the opamp's output node to alleviate it's bu
I found the start up circuit for a bandgap is difficult to work well at different Vcc supply. For example, 2.7v and 3.6V. When the Vcc is high, the start up circuit can not shut up completely and when the Vcc is low, the startup circuit can not bias the bandgap core circuit to a wanted level. How to handle this problem when the Vcc (...)
Transient analysis is enough to simulate a bandgap circuit.
Have you built a start up circuit in your bandgap circuits?
Please help me to improve the start up time of bandgap.. If anybody of u have the start up circuit which is very fast, please upload here.. bandgap circuit is the normal cascoded PMOS and cascoded NMOS circuit..
The architecture of amplifier is from Op-amps and startup circuits for CMOS bandgap references with near 1-V supply Boni, A.; Solid-State Circuits, IEEE Journal of Volume 37, Issue 10, Oct. 2002 Page(s):1339 - 1343 Digital Object Identifier 10.1109/JSSC.2002.803055 Summary: The design of bandgap-based voltage references in (...)
Do you know any book or ref to design the startup circuit for bandgap both in cmos and bicmos process. Please advise. thanks
hi, i'm design a bandgap voltage and simulate it with hspice. how can i simulate and validate my bandgap design correct or not without using startup circuit? is it using .tran xx xx uis and .ic v(x)=xx to initialize some node to the specific voltage? thanks.
Try this link: and goto Start-up Circuitry section .. Regards, IanP
I need startup circuit for bangap voltage reference and value for R1 and R2. VDDA=5V
Can any one propose fast setling time, low noise CMOS bandgap configuration. Now we have such a problem, clock of the ADC couses glitches in the power supply. And this disturbs behaviour of our bandgap. The bandgap is made with large area components in order to insure low noise. But these large components, increase setling time of the (...)
There are few such materials about startup circuits for bandgap in IEEE. Where can I find relative materials? Thank you there is one start up circuit in the chaper of bandgap in Razavi's book
To sunking, It is for bipolar version bandgap. Is there any similiar circuits for CMOS bandgap ?
if the circuit is self-biased it contains a zero solution. let's say your circuit uses an amplifier or level shift stage. if this current is set by the bandgap then the bandgap has to be running for that current to exist. also, that current must exist to allow the bandgap to run. this would be one instance of a zero solution.. no current (...)
in my opinion, it can not filter the high frequency noise from the power supply, and it can delay the outputs ,but do the outputs really need the delay? or there are some other functions this capacitor can perform? thank you very much:)
How to identify the startup loop and bandgap loop ?