45 Threads found on edaboard.com: Barrel Shifter
hi
simple code for barrel shifter is given in VHDL primer J. Bhaskar book but it is in VHDL . I think its logic can easily be converted to Verilog code
bye
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.06.2005 16:11 :: shreshtha :: Replies: 6 :: Views: 16566
Hi, everybody
I want to design a barrel shifer in our design, but I don't how to discribe it using verilog language, or it is only can be generated in the synthetize statge?
thanks for any reply!!
clive chen
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.07.2005 09:55 :: clivechen :: Replies: 6 :: Views: 3692
Hi, everybody!
If we want to implemented the MAC instruction, Why do we need the barrel shifer to accellerate its speed?
thanks for any reply
clive chen
Digital Signal Processing :: 05.07.2005 11:52 :: clivechen :: Replies: 3 :: Views: 624
hi i want to design barrel shifter using combinational logic
can any body help me 4 that
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.08.2006 09:18 :: dipen_dudhat :: Replies: 3 :: Views: 1950
i have to design a barrel shifter and a logarithmic shifter of the 4-by-4 shifter and have to compare them in terms of area, delay, and power. how to determine the area of the shifter?? which shifter give the lower delay and power??
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.04.2007 06:46 :: vivian248 :: Replies: 0 :: Views: 366
vhdl code for barrel shifter,4 bit divider and,4 bit serial adder
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.10.2007 11:54 :: seemagoyal44 :: Replies: 0 :: Views: 3335
hello !!
please help me in solving the following question :
Design a 8 bit barrel shifter has 3 bit input control signal .
CTRL Output
000 shift left 1
001 shift left 2
010 shift left 3
011 shift left 4
Electronic Elementary Questions :: 13.04.2010 12:30 :: graciousparul :: Replies: 1 :: Views: 2638
hi
Plz help me to construct a 16x1 Mux barrel shifter code in verilog.
The given data is that we want to move the output data
Shift left
Shift Right
Rotate Left
Rotate Right
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.03.2011 09:56 :: ss_engg :: Replies: 15 :: Views: 1860
Design a barrel shifter for 16 bit words in VHDL. This barrel shifter is capable of
logical shifting input toward left and right direction. Two different architecture
designs of the same barrel shifter must be implemented and tested with the
testbench you also need to develop. One (...)
Electronic Elementary Questions :: 13.03.2011 03:15 :: Anand Bhattar :: Replies: 1 :: Views: 1590
Hi,
I would need to design a 15-bit barrel shifter; I mean a barrel shifter having 15 inputs, 15 outputs, rotating according to 4 control bits.
I need the real architecture, described in terms of logic gates, not the verilogA.
Usually barrel shifter have a number of inputs which is a (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.04.2011 09:26 :: fra2k10 :: Replies: 4 :: Views: 924
hi i want to design a 8 bit barrel shifter and i want to do some hand calculation such as power ,delay, noise margin.after that i should draw a schematic and do simulation.then draw layout for that.finally i must extract the circuit and do a post layout simulation for that.but i have problems. what must i see in the first simulation and how i can
Software Problems, Hints and Reviews :: 28.01.2012 08:01 :: atefehn :: Replies: 1 :: Views: 683
hello everybody.
i read a paper about the ldpc decoder the block diagram of decoder ,it uses two stage barrel sifter .i cant find why it uses two stage.can anybody tell me?
the papaer is attached.and the barrel shifter is in the figure 8 in page 1453
by reguard.
Digital communication :: 14.02.2012 16:23 :: electronical :: Replies: 0 :: Views: 323
I am realizing a N-bit barrel shifter.
Here it is my component:
entity barrel_shifter is
Generic ( N : integer := 4);
Port ( data_in : in STD_LOGIC_VECTOR (N-1 downto 0);
shift : in STD_LOGIC_VECTOR (integer(ceil(log2(real(N))))-1 downto 0); -- log2 of N => number of inputs for the shift (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.12.2012 23:52 :: HyperText :: Replies: 2 :: Views: 148
I'm assuming your code is trying to shift a 32-bit word left 32 bits into a 64-bit word, right?
A barrel shifter is a PHYSICAL realization IMPLIED by your VHDL code.
ASIC Design Methodologies and Tools (Digital) :: 01.01.2013 02:13 :: barry :: Replies: 2 :: Views: 215
hi everyone,
i am trying to design an 8 bit barrel shifter by use of tanner tools.
i dont know where to start .....
plz tell me the basic building block and what are the important parts to design?
Electronic Elementary Questions :: 05.03.2013 18:58 :: prabhatranjan :: Replies: 0 :: Views: 90
RTL coding.. or any other efficient 32bit shifter to perform left and right shifting ???
Hi Santosh ,
What is your target platform , FPGA , ASIC or just Verilog Simulation .
Do you have timing constraints that you have to do this in one clock cycle .
barrel Shiftier is a combinational circ
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.03.2013 14:30 :: gasingh :: Replies: 4 :: Views: 262
Design overview
After putting some thought into the design of a barrel shifter it is clear that some sort of multiplexer circuitry is required to select how the input bits route to the output bits. A naive method of implementing a barrel shifter would be to use N (where N is the number of input bits) parallel N-to-1 (...)
Digital communication :: 19.03.2013 07:20 :: sandipm14 :: Replies: 2 :: Views: 142
barrel shifters are transmission gate arrays rather than a series of registers (otherwise known as combinational shifters). It is modified from a crossbar switch layout requiring (n-bit x n-bit) gates. They have the advantage that shifting is carried out over a single operation. The layout is regular and hence highly efficient. (...)
Electronic Elementary Questions :: 21.06.2005 15:17 :: checkmate :: Replies: 3 :: Views: 836
Source code for a barrel shifter:
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.01.2006 21:14 :: drwho78 :: Replies: 3 :: Views: 2347
Hello friends,
Can anyone help me out with barrel shifters. I just want a simple theory on what barrel shifter and a easy spec of a 8-bit barrel shifter. Please provide me some material.
Thank you.
ASIC Design Methodologies and Tools (Digital) :: 09.03.2012 17:27 :: Plzhelp :: Replies: 1 :: Views: 516
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PLD, SPLD, GAL, CPLD, FPGA Design :: 24.04.2003 09:12 :: ddr :: Replies: 6 :: Views: 1924
Description
The OpenCores54x (OC54x) DSP core is a cleanroom implementation of a popular family of DSPs designed by the No.1 DSP supplier from the southern part of the US.
The core is designed to be software compliant with the original Texas Instruments C54x DSP. However, the core is not designe
Microcontrollers :: 15.05.2003 06:54 :: elcielo :: Replies: 1 :: Views: 1205
Hello Gurus,
You know that cell-based design employs a scan-chain method to perform DFT. When your chip goes mass production, test vectors are feed into the chip, walk through the scan-chain, and tell you whether the chip works or not.
The question is for full custom layout design. How to tell your component, e.g. domino circuit, barrel-sh
ASIC Design Methodologies and Tools (Digital) :: 14.10.2003 08:41 :: philewar :: Replies: 4 :: Views: 1096
See Goal's 8051-compatible uC with MAC and barrel shifter 8-)
Microcontrollers :: 07.10.2004 14:54 :: 777 :: Replies: 8 :: Views: 1578
Can anybody share me some information about the average or approximate gate count numbers for following ASIC building blocks?
1)16*16 booth multiplier
2) two 16bit inputs ALU, traditional arithmetic(add,sub....) and logic (and,or,xor....) operations supported
3)16bit barrel shifter,supporting traditional logic shift and arithmetic shift
4)16*16
ASIC Design Methodologies and Tools (Digital) :: 12.10.2004 15:43 :: eexuke :: Replies: 2 :: Views: 889
It is a known fact that the 8051 CPU lacks a barrel shifter.
On the other hand, the operation
ino = ino & (ino-1);
does not need a barrel shifter.
Microcontrollers :: 27.09.2005 20:54 :: svicent :: Replies: 11 :: Views: 18526
Hi all,
I am reading a article. It mentions "multi-layer switching networks including, e.g.
omega(perfect shuffle)/delta networks, log shifter networks, etc.".
But why not use single-layer instead of multi-layer switch network?
I know simple barrel shifter. What's omega, delta and log shifter?
Any suggestions (...)
Electronic Elementary Questions :: 01.12.2005 11:17 :: davyzhu :: Replies: 0 :: Views: 414
The trick to designing a good ARM ALU is to put the barrel-shifter for the second operand in a different pipeline stage to the adder.
ASIC Design Methodologies and Tools (Digital) :: 21.01.2006 20:53 :: moneychaser :: Replies: 4 :: Views: 1426
barrel shifter:
A barrel shifter is a hardware device that can shift a data word by any number of bits in a single operation. It is implemented like a multiplexer, each output can be connected to any input depending on the shift distance.
Take for example a 4-bit barrel shifter, with (...)
Digital Signal Processing :: 25.01.2006 11:37 :: sinu_gowde :: Replies: 2 :: Views: 626
Just as I promised, my IP-core is ready. Its code name is xMB32.
It's a clone of the well known Microblaze IP by Xilinx.
XMB32 is code compatible with the original Microblaze with the following architectural differences:
1). Dcache and Icache are not implemented,
2). FSL channels are absent,
3). hardware multiplicati
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.05.2006 20:41 :: yego :: Replies: 15 :: Views: 32941
What you have written according to it both the multiplication and
shifting should complete in one clock cycle only. For modelsim you are
not providing any timing information. So it generates no error.
To do shifiting of data in single clock one needs what is known as barrel
shifter circuit! and not shift register.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.10.2006 13:54 :: nand_gates :: Replies: 9 :: Views: 655
If shift operation is performed based on input clock then it is sequantial, else combinational. The barrel shifter is an example of combinational.
ASIC Design Methodologies and Tools (Digital) :: 22.02.2007 12:06 :: satyakumar :: Replies: 4 :: Views: 622
Hi Babu,
From what I understand your processor has "Two Decoders" this doesn't mean that if your processor is of 1Ghz then you can straight away multiply it by a factor of 2x.
Let me give you some insight into such an architecture as this will clear your doubts. Your processor might have a design in which it has a pipe-line of 5/7 instructions
Digital Signal Processing :: 01.05.2007 15:45 :: kalyanram :: Replies: 4 :: Views: 4141
Hi
Pls elaborate what do you mean by 'available'? you can design whatever you like
Usually I would say there are 2 kind:
single shift register: can shift 1 bit at a time
barrel shifter : can shift n bits at a time.
Then you can have categories: shift left, shift right, shift with paralle load or shift with just serial load etc...
Kr,
Av
ASIC Design Methodologies and Tools (Digital) :: 06.08.2007 13:22 :: avimit :: Replies: 4 :: Views: 570
The difference between a "stardard" CPU and a DSP is that the DSP has optimized multiplying and adding units .Also there is a barrel shifter means that it can do multiplications and accumulations very fast . People talk about MACs (multiply and accumulate operations) to do an important number of MACS the whole machine must very optimized to
Digital Signal Processing :: 05.02.2009 18:30 :: eltonjohn :: Replies: 2 :: Views: 584
16bits rotate left
can I write verilog like this:
rotate_left:
//Need 16 2-to-1mux to finish 1-bit shift left
if (!Cnt)
in_stage2 = In;
else
in_stage2 = {In,In};
//Need 16 2-to-1mux to finish 2-bit shift left
if (!Cnt)
in_stage3 = in_stag
ASIC Design Methodologies and Tools (Digital) :: 16.02.2009 01:34 :: yangbay81983 :: Replies: 0 :: Views: 522
Hi,
I am glad to hear that you are paying attention on my arm ip core. Maybe, you are the second person to simulate it I know.
As for 32x32 multiplier, it is the key component in my core. Almost every ARM instruction need it. It is used not only as RmxRs+Rn for MUL instruction, but also Rm>>Rs+Rn for most instructions which has shif
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.03.2009 13:07 :: mathswork :: Replies: 17 :: Views: 2985
You can use barrel shifter for this purpose. barrel shifter is combinational circuit that can shift or rotate a data word by any number of bits in a single clock cycle.
ASIC Design Methodologies and Tools (Digital) :: 20.04.2011 07:16 :: yadavvlsi :: Replies: 2 :: Views: 206
Hi guys,
I'm a noob trying to become more and more expert ;)
The project I'm trying to design should be able to correlate (or auto-correlate) a binary signal (i.e. an arbitrary binary sequence) and output the correlation coeffs using a 16-bit word.
All was coded under Verilog and I'm using Xilinx Spartan-6 as development board to run it.
S
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.06.2011 16:57 :: lorempa :: Replies: 0 :: Views: 317
the general solution is a barrel shifter. Firstly, I'd make sure you understand the problem. if this is 64/66 encoded data, it might be easier to decode the data and track the data/control bits separately. This is especially true if control data can be discarded or routed to different destination.
barrel shifters are (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.07.2011 04:14 :: permute :: Replies: 3 :: Views: 387
Hi guys,
I am doing a subject assignment in Uni.
I need to design a barrel shifter (4X4). I done the circuit and now i try to draw the layout and met some weird problem.
BTW: i am using IC station on RedHat.
For your information, while drawing the layout you can invoke the logic (circuit) and put it beside the layout you gonna draw to ha
Analog IC Design and Layout :: 27.07.2011 06:54 :: haircream :: Replies: 1 :: Views: 296
They are usually an integral part of a larger device but what you are asking for is normally called a "barrel shifter" rather than a shift register. They are used in fast math operations.
Brian.
Hobby Circuits and Small Projects Problems :: 24.09.2011 11:01 :: betwixt :: Replies: 13 :: Views: 864
Can I refer you to a document? I was about to try to explain it, but this says it a nutshell:
The dsPIC has a built in DSP, with facilities such as dual 40-bit accumulators, 16x16 multiply-and-accumulate, 40-bit barrel shifter, etc. That's in addition to a fully-featured (according t
Microcontrollers :: 17.02.2012 23:36 :: FoxyRick :: Replies: 1 :: Views: 574
A logic expense that can be traded for with a latency expense by pipelining. If you can tolerate a latency of log2(max_possible_shift_value) clock cycles delay then the barrel shifter can be implemented with a cluster of 2-> 1 muxes (or 4->1 muxes) feeding a cluster of flops.
But then I cannot use the "rol" operator ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.12.2012 13:37 :: shaiko :: Replies: 20 :: Views: 551
Hi,
I created an 8bit barrel shifter and now I want to simulate it using Xilinx ISE tools, specifically I want to do a Post-Route simulation (the last step).
I do these steps:
1. Synthesize - XST
2. Implement Design
3. I check the "Synthesis Report" and find: "Minimum period: 3.281ns (Maximum Frequency: 304.785MHz)
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.12.2012 04:25 :: K-J :: Replies: 6 :: Views: 258
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