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Hi friend please help me for design of 24h clock /3 digit counter just with gate & bcd counter IC thanks
Instead of using all those scary asynchronous counters and resets, you should redesign using only synchronous counters. Here is a two-digit synchronous bcd counter that counts from 00 to 66 then back to 00: module top (clk, bcd); input clk; output reg bcd = 0; always @ (...)
i need to do a project in verilog> design an 8-bit bcd counter using 2 74163 counters and multiplexer 4:1 TABLE OF CONTENTS 1. Project theme -design an 8-bit bcd counter using two 74163 counters and multiplexer 4:1 2. Theoretical approach 3. Structural description of the (...)
you can create a 2 digit bcd counter by using two 4 bit counters and some logic gates.The main idea is that when the count in the first(LSB) counter reaches the value "1001"( 9 in decimal) it is reset to zero and the second(MSB) counter is incremented by '1'. I am not sure about why you need a 4:1 MUX for (...)
We would like to design a 2-decade up/down bcd counter in HDL language using behavioral description. Since the counter is a 2-decade one, it is thus able to count from 00 to 99 and then back to 00. i need the code?
Here is verilog code for 16 bit bcd up counter translate this to VHDL! Hope this helps! module bcd_count ( // Outputs count, // Inputs clk, reset_n ); input clk, reset_n; output count; reg count; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin count <=
Hi, I am trying to simulate a bcd counter in Hspice, as you know bcd counters are consisted of flip-flops such as JK-FF. In my circuit there are four JK-FFs, the flip-flop subckt is working properly, I mean when I simulate a single JKFF individually in a netlist it works properly, but when I connect the JKFFs together the (...)
I am trying to write the VHDL code for a Timing Genarator Chip : in the VHDL code i have to incorporate a code for the 16 Bit bcd(Binary Coded Decimal) counter i.e. 4 Decades , i tried a lot but unable to figure it out how to get it working... as the 16 bit bcd counter can count from 0 to 9999 ,for the first 9 clock pulses (...)
Actually I plan to test the 2 digits bcd counter display on 7 seg. (in circuit I used two 7493s). I want to use (your) counter as a module and other module will call this module to run 2 digits bcd counter display on 7 seg. How to do. Pls..
bcd caunter for 8051 microcontroller.
Hi Navveed, The wireless transmission is fine. How many bits counter is it? Is it a bcd counter? The encoder decoder pair works on 4bit data - so ideal for bcd transmission. But the problem is you need to sequence these bcds both at transmission and reception side. A better way is to not use the (...)
Here it goes!! For this simple counter No need to have Statemachine! module bcd_count(clk, reset, ce, count); input clk, reset; input ce; // count enable output count; // two digit bcd counter reg count; always @(posedge clk or posedge reset) begin if (reset) begin count <= (...)
I have ton ot good examples of bcd or decade counters but NONE have a "real" counter which can be loaded with arbitrary value just like the one depicted on the pix, which is a genetic SN74LS168 up/down ripple bcd counter with load? Building it out of D flip-flops and ton of gates as the function diagram (...)
i need to do a 2 digit bcd counter testbench verilog ,here i attached the verilog but i dunno correct a not Where is the attachment Nandhu
You need a three bit bcd counter. A nice article is to be found shold also read about flipflops to be able to give an answer to the
Hi. I'm trying to plan a quite large DIY project. I'm aware that what I'm trying to do could possible be impossible to achieve. Well here's the plan: I want to make a circuit having TWO sinus outputs, let's call them sin1 and sin2. sin2 shall be about 90 deg after sin1. Finally I'll use those two voltages to have very fine control of a stepper
Hi Guys I have designed a bcd-counter that gets displayed on 2x 7 segment displays. Each display counts 9 and resets, i.e the least significant display starts off at 0 and when it reaches 9,it resets to 0 and it increments the most significant display to a one and so on. But the counting sequence of the least significant is not counting sequenti
>@ Mister_rf , Allow me to explain my concern on the Opto Design. Short path = no issue. Long path = some concerns Threshold of detection is dependant on; gain of photo-transistor (huge variance and aging effect) value of emitter resistor noise of stray light affecting shadow levels strength of stray reflections
hi all i need vhdl code for 0-99 bcd counter 7-seg display code Changed by pressing the Button tanx
hi all can someone help me in this question We would like to design a 2-decade up/down bcd counter in HDL language using behavioral description. Since the counter is a 2-decade one, it is thus able to count from 00 to 99 and then back to 00. The counter has the following input control signals: 1. Load signal to (...)
This seems to be ur homework!! The problem is clear and simple you have to write verilog code for the digital clock! Start with the counters hours => 00 to 23 bcd counter we need two such counters one for clock and one for alarm setting minutes => (...)
Hi,everyone! Can you tell me, please,how to make the following task: an bcd counter on 8 bits, using 74163 counters and logic gates. Can you tell me the code or some ideas? Thank you!
can u,please,help me doing a bcd counter implementation with 74163 counters and logic gates? In Verilog... Thank you a lot!
hey friends.. i am creating a digital timer with bcd counter but the problem is if the power is turned off its it starts again but i have to make like this if the power is switch off it should paused and start from the paused value when the power switch on again.. help me guys thanks ..:D
its my first basic code which is completely working fine... Its specially for all those beginners who dont know how to divide (decrease) the clock speed... u can also check out my video => codes are as follows: counter code: library ieee; use ieee.std_logic_1164.all; use ieee.numer
I have to design bcd counter with JK Flip Flops which should have Asynchronous Parallel load (Active high) Synchronous Reset (Active Low) What we mean by both these terms
Hi! I am now doing a project on delay fault test on 74series chips. The attachment is my quartus II project with design for delay fault test on 7400 (two inputs Nand gates) as example. Since the chips delays are in nanoseconds, I use pll in quartus to step up the frequency from 50Mhz to 500Mhz and I connected to the 74161 ( bcd counter). I
you should search for bcd to seven seg decoder IC and interface it to seven seg display then. ha ha, you mean the O P ???
hi all,,,,,,,,i made a 640x480 VGA controller in VHDL using Spartan-3. AND, i could display characters too. now, i'm trying to display a digital clock on screen. i tried to make bcd counter and address variables to the characters , but it didn't work. the question is, how i can combine the vga controller code and clock together , and addres
I am trying to implement the Intel 8253 PTI , i have written the code for the Binary counter and the bcd counter that i need to instantiate in the Main Code for 8253, but now i am facing some problem with the modes , as for every mode the Gate Input acts differently and effects the count in a different manner , so i cant make so many (...)
Below is the code for a 3-digit bcd-counter (Binary Coded Decimal) I implemented while studying Verilog. You have to change the compare values (I commented on the code) to make it count like a clock (i.e. up to 60 instead of 100) and you can also add more digits for a full scale clock. You can access the driver for the lcd here: [URL="www.e
Hi, I need help to develop three bcd counters 0 .. 9 on 3 independent displays on board BASYS. For a one counter could do. The code is as follows: ------------------------------------------------------------------------------------------------------------------------------------------------------------ counter: (...)
You need a way to convert binary numbers into bcd (binary coded decimal). With bcd each decimal digit occupies 4 bits (a nibble). Each nibble goes up to 9. The next increment causes the bcd digit to return to 0, and generates a carry to the next nibble. Say your resistors all transmit a '1'. In binary this occupies 2 nibbles as: 0111 (...)
Implement a 3-digit bcd counter. Display the contents of the counter on the 7-segment displays, HEX2��0. Derive a control signal, from the 50-MHz clock signal provided on the DE1 board, to increment the contents of the counter at one-second intervals. Use the pushbutton switch KEY0 to reset the (...)
Hello to all, I?m newbie in VHDL programming on FPGA. I need help from all of you out there. Right now I try to write a code for 2-digit bcd down counter, LCD display message and synchronization between both of them. For 2-digit bcd down counter, here?s my code library IEEE; use IEEE.std_logic_1164.all; use (...)
I want to make a counter with modulo 56 using MCU AT89C51 First, 1Hz pulse is applied to P1.0 Everytime when it rises from 0 to 1, the AT89C51 will "let" the port P2 know that, it must increase by 1 so through 74LS47 (bcd to 7-segment IC) LED displays the upper number (i.e. first, LED displays 08, after ths 0-to-1 edge is applied, LED displays
Hi all, I have problem in converting 26 bit binary to bcd using PIC 16F782 using assembly language. I need to convert eg 2FAF080 hex to 50 000 000 dec using 4 registers casade together.. which mean 4 bytes. actually my application is to make use of timer0 as a counter to count the input freqency and store them in a 4 byte register.. then conv
how do we interface dual bcd 7 segments with the anybody have the source code for this method especially for pulse gimme some answer bcoz this is for my project for this semester..:|
go for two 74190 if u want bcd counting or go for 74169 for binary counting. See the datasheets of these IC's then u will get how to do it
hello all, i am making a IR motion detector circuit(WITHOUT USING microcontroller)which also incorporates a counter circuit to it..thereby displaying the no. of times the IR beam is interrupted by obstructions. as of now.the counter circuit that i have come up with incorporates 3 IC's per 1 7-segment display,namely : (1)7447;bcd to 7-
hello all, i am making a IR motion detector circuit(WITHOUT USING microcontroller)which also incorporates a counter circuit to it..thereby displaying the no. of times the IR beam is interrupted by obstructions. as of now.the counter circuit that i have come up with incorporates 3 IC's per 1 7-segment display,namely : (1)7447;bcd to (...)
Are you using SystemVerilog? That module won't compile in Verilog because this statement can't go inside an 'always' block: reg hour1,min1,sec1; I moved it up a few lines, and now it compiles fine (I'm using ModelSim in Verilog mode). It appears to simulate fine too. It's a 24-hour bcd clock. What malfunction do you s
Hi all,have a question here is that,what is the function RBI,RBO and LT pin on the 7447 bcd-7segent decoder IC? It seems to suppressed zero on the 7 segment display,but I don't know how it works. About the LT, I only know has to connect to VCC, can anyone explain me? thx : )
Hi, I need to implement a simple VHDL frequency counter for a school project. Must be 4 multiplexed digits. (the FPGA as few macrocells). I know how to implement the counter and the bcd to seven segment. is the multiplexing and puting things togheter that i need help. Can anyone point me to an example? Must be very simple. Thank (...)
I need to modify an older counter where 74F190 chip died. Is there any chance to make a substitution with 74LVC (maybe 74LVC109) chips that can count up to 200MHz. Needed is only decade UP counting and reset to 0.
Hi All A newbee needs a little help coming up with a divide by 25 counter. Also a divide by 125 counter would be helpful too. I am beginning a UHF frequency counter project and have discovered a problem. :cry: Recently, I bought a number of surplus divide by 4 UHF (2 GHz) Pre-Scalers. Now I am trying to figure out how to get the (...)
allot 6(or9 ) bcd locations in internal data ram. when u want to count up, increment the lsd first . based on carry (bcd carry) ripple through all higher bcd digits . update the dataram . display the contents of these digits. srizbf 13thmay2010
I have searched the forum but couldn't find what i wanted exactly.. Say i have an output from an 8-bit binary counter "95" .. I want to display it on 7-segment displays on a spartan 3E FPGA board.. What is the solution of this problem even if i got the bcd conversion, how can I display it on 7-segments? Thanks for your concern..
Hello guys, Does anyone know how to design 16-bit up counter using verilog HDL? from the binary output produced, it need to be converted into bcd. Then the decimal number will be display at 7-segment. Does anyone know the step/flow should be done for this experiment?
Hi all, I am designing a four digit 7 segment display just using IC 74LS90 decade counter and 74LS47 bcd to 7 segment driver. My question is how to link the 74LS90 decade counter together so that the four 7 segment display will show me the result?