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72 Threads found on Bicmos Design
What is the max breakdown voltage for 0.35bicmos
Hi all, I am trying to design a Marchand balun (20GHz - 40GHz) using AWR Microwave Office. The process (PDK) that I am using is IHP 0.25um SiGe bicmos. My simple design is close to the required specifications though S11 is not matched for the center frequency (30GHz), it is currently matched for 38GHz. Also, the phase balance is around (...)
BJTs lack the fragile thin oxide of the gate. You can still do hot carrier type damage with an ESD event, and drift your front end out of offset spec or Iio/Iib, but you're not likely to see the functionality compromised. The reason for bicmos in that Unitrode part is, the op amp and reference especially are easier to design and work better (and
Hi, It's my first time to design circuit by using BJTs. I am doing a CML driver as below 108196 This is simply modified from CMOS CML circuits, but I found it doesn't work at this point, maybe due to the base current (ib) too large? but if I make the size larger to increase beta, the speed maybe affected. And it's
Does anybody knows about any commercially avaliable CFA (current feedback amplifier ) IC in CMOS technology ? The one's I know about are all in BJT or bicmos technologies like AD8001 , AD811 , LT1210 etc. Thanks Vipul
I have a task of designing an Up conversion mixer for cognitive radio using BJT SiGe bicmos Technoloy. I am new to ADS Mixer design. Helful tip on how to start, link of reference work or previous work will be highly appreciated.
Where can I find some resources with examples or tutorials that include RFIC laout examples to get started with IBM bicmos process using the Cadence design tools? My only experience has been with the schematic and circuit simulation. Thanks!
Hi.i need ihp 0.25um SiGe bicmos designkit.can any body help me?:cry:
Hi, Does anybody has any architectural schematic diagram or Paper on it. DDC manual doesnt provide much information about design details. Please, post it. If you have it. "A Single-Supply, Monolithic, MIL-STD-1553 Transceiver Implemented in bicmos Wafer Fabrication Technology " If you have this paper then please pass it. Thank You
Hello Every one, I want to design a analog mixer with 0.18um bicmos process. The mixer is used to be one module in the whole chip. One input signal of the mixer is a wide-band signal, for example , its bandwidth is 50MHz. The center frequency is variable between DC and 2GHz. The other input signal is a square wave whose maximum frequency is
Hi all, I am looking for an accurate model of HBT/Bipolar/bicmos(anything) with a ft greater than 200GHz. The simulation platform would be ADS. Please help. Thanks. Thank.
Hi, I am trying to design a high speed input buffers for my high performance ADC.I read that bicmos buffers are better than CMOS ones for this kind of applications. can anyone give me a good reference for this kind of buffers or advise me about using this kind of buffers in my design. using this buffers will force me to separate the (...)
I'm designing an opamp and need 78 dB gain and 4 GHz BW with 3.5 pF Cload and 2.5 V supply voltage. I can get the gain with a single stage folded-cascode opamp, but the best result for the BW is just 1.8 GHz. Would you please let me know your opinion about this design and any suggestions for the structure? I'm using bicmos process. Thank you.
You didn't provide enough info to get help. If this can be done depends on several details: Pure bipolar or bicmos process? Which device has to stand the 36V? BJT or MOSFET? Grounded or floating? Which current? If HV-MOSFET, how much voltage would be necessary between G-S resp. G-B? Does the foundry provide
1. when I use bicmos process to design a simple two stage amp, if bipolar as different input pair ,then small noise, large gm/Gain, any other..? if bipoalr as active load and second stage input , then what benefit for it??? 2. How to decided a OP Gain, GBW. For a OP used in BandGap, LDO, DC_DC ,..... how to choose the b
I am an electronics engineer with over 10 years experience in CMOS integrated circuits design and CMOS/bicmos IC layout design . If you need my services in IC layout design and PCB layout design please find more details at and don't hesitate to contact me.
Hi, I am located in Europe and looking for an analog/mixed IC design engineer position - Telecommuting or Freelance - Frequent travel is possible. EDA tools availability can be figured out. - 15 years strong experience in CMOS/bicmos IC design: PLLs, DLL, ADC/DAC, voltage regulators, AGC and control loops, switch cap, amplifiers, buffers, (...)
I'm going to design an output driver using a 0.35um tripple-well bicmos process. The supply voltage of this output driver is Vdd=3.3V, and Vss=0V. In really application, the Output pin could be accidentally connected to 16V (>3.3V) or -16V external unregulated battery. Customer's SPEC is that, not matter which of these two wrong connections happe
Hi I need to design an SPI MASTER (which sits in FPGA ) to communicate with the (16-Bit, 100 kSPS/200 kSPS bicmos AD977/AD977A)A/D Converter of analog devices. Can anyone tell me how to proceed? thank you
Hello all, I am designing a mixer and wanna use IBM SiGe bicmos transistor in my design. I downloaded a text file (t94h_7wl_4lm_am-params.txt) from MOSIS which also includes BSIM 3.1 parameters of this transistor for N and P type. My question at this point is how can I use this BSIM parameters at ADS? Do I have to enter whole parameters (...)
Hi amriths04 and thanks for you answer. Do you know that paper? Have you read it? I know about this paper, but have not read it. I'm using a 0.35 CMOS tech, not a bicmos,. That matters. Generally for cheaper design, people use parasitic pnp from a CMOS technology. If you use a bicmos
We are an IC design company. Our main expertise is in the area of ultra-low-power mixed-signal ASICs using Bulk/SOI CMOS, HV CMOS-compatible and bicmos technologies, particularly for safety critical applications. One characteristic that really set us apart from the rest of the design companies world-wide is the ?know how? of (...)
in your setup folder of the ams hit kit: u find the folder which is called "spectre" in it, according to your process: which may be s35 or c35 or bicmos process you choose a folder from the "spectre " folder let's say that your process, c35 so, choose: /spectre/c35 in this folder: add all files that have the extension: .scs so
Hi, I am trying to design an ADC with 8bit 2GS/s specifications with minimum power consumption. The process is 0.13um bicmos. I am trying to look for papers and found some groups used folding+interpolation to achieve >1G with 8bits resolution. Is F+I the only possible way to achieve the specs or there are better ways to do it? Do anyone have some r
We are an IC design company. Our main expertise is in the area of ultra-low-power mixed-signal ASICs using Bulk/SOI CMOS, HV CMOS-compatible and bicmos technologies, particularly for safety critical applications. One characteristic that really set us apart from the rest of the design companies world-wide is the ?know how? of (...)
Hi everybody, I am to design VCO of 20 GHz by using bicmos technology SiGE 0.25 micro metre with the help of ADS software.I know a little about the theory of VCO.Please guide me how I should start to design VCO.I just started using ADS,but do not know where to start.If possible,mention me the relavent material for my (...)
Hi all, I am going to design a 20-bit delta-sigma ADC. Before I start, I want to know the feasibility of doing it with CMOS at 5V single supply. Power consumption is not a major concern, as long as we can meet the performance. Do you have any advice on designing a 20-bit delta-sigma ADC? Do I need go to bicmos? Thanks. StanLangley
I repost this question. I am using IBM 0.18um bicmos process. For cadence schematic simulation, I used a bipolar transistor(BJT) for low noise amplifier design and simulated in DC analysis. BJT is always working in region 1 or region 3. I am so wondering region 3 is saturation region or breakdown region. I attach the picture for
We are an IC design company. Our main expertise is in the area of ultra-low-power mixed-signal ASICs using Bulk/SOI CMOS, HV CMOS-compatible and bicmos technologies, particularly for safety critical applications. One characteristic that really set us apart from the rest of the design companies world-wide is the ?know how? of (...)
It explains the device structures and technology for CMOS/BJT/bicmos using device layouts and cross sectional views. on transistor-level, not go to circuits. very pictorial, thanks.
In CMOS or bicmos RFIC design the power down mode is a typical design practice. In each circuit, each node is controlled (with CMOS small switches) in order to assure that the circuit goes properly in power down. I hope it can help. Mazz
do you have any idea how i could tune the transistor parameters for example MOS's wtot)? i hope this is possible with ADS
In the attachment is a Curvature-Compensated bandgap. Maybe you have seen it in the paper"Curvature-Compensated bicmos Bandgap with 1-V Supply Voltage". I'm now doing some design about this bandgap. But I get worse simulation result when use the curvature compensated circuit(it includes R4,R5,M12,Q3) than take it away. Can anyone have the experien
My opinions: -todays designs for commercial RFICs products are largely in bicmos. You're right for WLAN, but for Cellular or for high performance systems is still largely used. The reason is simple: less cost/performance. -CMOS has really sense where SOC is the system strategy. -being a good bicmos RFIC designer is the (...)
How much is the load capacitance? How much should be the power consumption? What is the process technology? CMOC, bicmos... What is the feature size? Above questions are very important to answer then ask about the amp specs. Also specs 1, 2, 4 and 5 is easily achievable, but 3 is extraordinarily difficult. You have to use either autozeroing
Hi.can any body help me? I want to design modulator with SiGe bicmos.I don`t have this design kit.If you have 0.25um SiGe bicmos designkit for ADS,please help me.I search for bicmos7RF from STMicroelectronics
In production lines, 0.25u bicmos, 0.18/0.13 CMOS are widely used for their balance of performance/cost/maturity status. In R&D yuo'll find only CMOS in 90 nm and below. I hope it can help. Mazz
It depends on what kind of technology you will choose. Here are two reference papers who are both wideband LNAs for UWB, and one of them are CMOS and the other SiGe bicmos. 1. Ismail A,Abidi A.A 3 to 10GHz LNA using a wideband LC-ladder matching network.In: ISSCC,2004 2.Bevilacqua A,Niknejad ultra-wideband CMOS LNA for 3.1 to 10.6 GHz
Abstract A VDSL receiver front-end with a programmable gain low noise amplifier is presented. The amplifier consumes only 35mW from a 3.3V supply in a 0.35μm bicmos technology and is suitable for DMT-based VDSL systems with bandwidths up to 12MHz. The linearity is expressed in Missing Band Depth (MBD) for a worst case bandplan . The LNA
Drear, I designed a single ended input stage inverting type TIA using 0.18-?m bicmos teachnology.Its- input current=1A,photodiode capacirance=0.5pf,parasitic capacitance=0.6pf,voltage(dc)=1.8v,bondwire inductance=0.5nh,n-mos transistor width=20?m & its fingure=1,p-mos transistor width=40?m & its fingure=1,frequency at 3db=1.4GHz. how can I
Usually People will use Virtuso ( layout tool in cadence) draw layout. and there is tool called Hercules which can do veification. and for the BIPOLAR or bicmos, it just depends on the process files the foundry can provide to you. not rely on the extraction tool.
Dynamic current mirrors... Any other Advanced CMOS and bicmos design courses like this one ?
I use GeSi bicmos 0.35 process to design some circuit. I feel confused about the connection between the component subtrate and the ground. Someone tell me that I shoud conncet the subtrate of the npn or mos transitor to the ground. but someone tell me they did not do so. I want to know the connection between the ground and the subtrate is necessary
@MS bicmos design rule ( 0.35 SiGe )
Refer to this paper: "P. Malcovati, F. Maloberti, M. Pruzzi, and C. Fiocchi, "Curvature compensated bicmos bandgap with 1-V supply voltage," IEEE J. Solid-State Circuits, vol.36, no.7, pp.1076?1081, July 2001"
Hi, are you working with only CMOS or bicmos.....if bicmos can use BJT/HBT (not the lateral available in pure CMOS) to enhance it... sankudey
SiGe technology is a bicmos technology that include HBT "hetrojunction Bipolar Transisitor" the base of this tarnsistor is a SiGe which make the devices very fast FT typically about 60 to 70 GHz so u can use these HBT's in VCO desing like cmos cross coupled pair khouly
which technology u want to dsign ur oscillator is it a discreet oscillator with tarnsistor or it will be an chip "in cmos technology" , or bicmos khouly
Hi all, I will design a low quiescent current (about 20uA), high PSRR (50kHz 90dB), because the supply voltage is from 2V to 18V. Because the process I will select bicmos so can anybody tell me some good structure?
Hello, I'm trying to design an integrated (on-chip) high speed pulse detector in bicmos technology. The detector is asynchronous and should be able to detect pulses of width 750 ps. Can anyone share any ideas/reference material/papers/articles on this design topic? Thanks, Bharath