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17 Threads found on edaboard.com: **Binary Divider**

Look for fast **binary** division, booth algorithm.

ASIC Design Methodologies and Tools (Digital) :: 01-27-2014 03:01 :: FvM :: Replies: **3** :: Views: **273**

Without seeing the schematic how are we supposed to tell?
Each of those is a **binary** counter but they have different **divider** outputs, whether they will work or not depends on how they connect to the rest of the circuit. The CD4020 is easily available almost everywhere, just because your local shop (wherever that is) does not have them, it doesn't

Analog IC Design and Layout :: 11-06-2013 09:55 :: betwixt :: Replies: **8** :: Views: **747**

In case you are using CMOS IC's:
If you cascade two 4017 decade counters, you can tap the '6' outputs and feed them to the inputs of an AND gate. It will produce a pulse every 66 counts. Wire the signal so it resets the 4017's.
Or if you are using 7400 series (some of the following might have a counterpart in CMOS):
7493 '4-bit **binary** counter'

Electronic Elementary Questions :: 04-17-2013 01:52 :: BradtheRad :: Replies: **3** :: Views: **723**

Can anyone please post a code for "16-bit **binary** division"..,????

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-04-2013 05:40 :: ponparithi :: Replies: **5** :: Views: **438**

Hello Friends
Sometime we have problems with scaling
the analog signal before connect to ADC.
Here I upload help file in PDF format.
And I can think it will be useful to many of us.

Microcontrollers :: 03-11-2013 04:12 :: derser :: Replies: **11** :: Views: **500**

I am doing a **divider** circuit in verilog and using the non-restoring division algorithm.
I am having trouble representing the remainder as a fractional **binary** number.
For example if I do 0111/0011 (7/3) I get the quotient as 0010 and remainder as 0001 which is correct but I want to represent it as 0010.0101.
Can Someone help ??

ASIC Design Methodologies and Tools (Digital) :: 11-10-2012 04:31 :: SparshPatwa :: Replies: **1** :: Views: **1230**

Hello I am trying to convert a std_logic_vector to integer. Here is how I did the std_logic_vector to integer conversion.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity programmable_**divider** is
port( clk : in std_logic;
clk_out : out std_logic;
divide_value : in std_logic_vector (9 downto 0)
);
end programmable_

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-08-2012 01:36 :: dumindu89 :: Replies: **3** :: Views: **1243**

The HC160 & HC161 are virtually identical - the HC160 is a BCD rather than **binary** counter so the circuit should be fine.
I have simulated it and it looks ok. The parallel load is 5 in my example so the counter counts 11 pulses (= 16 - 5).
Keith.

RF, Microwave, Antennas and Optics :: 12-14-2010 04:36 :: keith1200rs :: Replies: **7** :: Views: **536**

Hello Everyone,
I am new to electronic design. I want to generate a 102.4Khz signal by multiplying a 50Hz signal using a PLL CD4046 and a **binary** counter/**divider** CD4020B.Can any one please help me out with the circuit.
Thanks in advance
Regards
Lohith

Analog Circuit Design :: 06-26-2010 06:26 :: NeelaLohith :: Replies: **1** :: Views: **798**

HI, All:
The project is a 12bit SAR-ADC, the 6 MSBs is **binary**-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor **divider**.
In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the m

Analog IC Design and Layout :: 12-27-2009 08:07 :: hbchens :: Replies: **13** :: Views: **4577**

Have you heard about IEEE 754 standard. Please read about it..
Assume ur going to use a floating point **divider** u have to represent ur floating point numbers in a **binary** format and give it as an input to Xilinx CoreGen Fl

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-04-2009 15:28 :: teja321 :: Replies: **8** :: Views: **3867**

Hi
Try a CD4060, 14 Stage **binary** Counter/**divider** and Oscillator.
You find a example circuit at
regards
J

Professional Hardware and Electronics Design :: 01-07-2008 16:13 :: jzo777n :: Replies: **4** :: Views: **1370**

The normal way of making an FM receiver with digital frequency control is to make a superhetrodyne receiver that generates the local oscillator signal using a PLL. The frequency generated by the PLL is set by **binary** values in the programmable **divider**. Read some books about radio communications.
Making a fully digital broadcast FM receiver will

RF, Microwave, Antennas and Optics :: 06-01-2006 06:17 :: throwaway18 :: Replies: **3** :: Views: **1250**

hii everybdy..
hwz life and work goin on?
i have two questions:
1)actually m a student and being assigned project to make 8-bit **binary** counter and to optimize it in terms of critical path..cmos implemnetation of it. SO can anybdy guide me how shuld i pursue it..i have jst 2 weeks...not more than tht..
2)can anybdy provide me the solout

ASIC Design Methodologies and Tools (Digital) :: 10-14-2005 02:02 :: harry_madaan :: Replies: **0** :: Views: **1134**

hii evrybdy,
i want to design an 8-bit **binary** **divider**..its transistor level implementation..and thn i have to optimize it using its criitical delay under worst input pattern.
can anybdy hlp me or guide me in this regard
links , pdf files and e-books will b hlpful...
hope a sooner reply
thnxs in advance
harry

ASIC Design Methodologies and Tools (Digital) :: 10-04-2005 10:27 :: harry_madaan :: Replies: **4** :: Views: **2612**

What is Nx64k?
If you want to divide a clock by 65536, then feed it into a 16-bit **binary** counter, and output the most significant bit.
Do you need help doing that?

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-25-2005 09:23 :: echo47 :: Replies: **7** :: Views: **3025**

What are you trying to divide - voltage, frequency, **binary** number, ... ?

Analog Circuit Design :: 04-27-2005 08:03 :: echo47 :: Replies: **4** :: Views: **1245**

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matlab not power spectrum | matlab prentice hall | matlab rayleigh randn | matlab reed solomon | matlab query | matlab switching | matrix display htm | max transceiver | max density | mbist memory