41 Threads found on edaboard.com: Binary Divider
i want to design an 8-bit binary divider..its transistor level implementation..and thn i have to optimize it using its criitical delay under worst input pattern.
can anybdy hlp me or guide me in this regard
links , pdf files and e-books will b hlpful...
hope a sooner reply
thnxs in advance
ASIC Design Methodologies and Tools (Digital) :: 04.10.2005 10:27 :: harry_madaan :: Replies: 4 :: Views: 2424
hwz life and work goin on?
i have two questions:
1)actually m a student and being assigned project to make 8-bit binary counter and to optimize it in terms of critical path..cmos implemnetation of it. SO can anybdy guide me how shuld i pursue it..i have jst 2 weeks...not more than tht..
2)can anybdy provide me the solout
ASIC Design Methodologies and Tools (Digital) :: 14.10.2005 02:02 :: harry_madaan :: Replies: 0 :: Views: 1066
What are you trying to divide - voltage, frequency, binary number, ... ?
Analog Circuit Design :: 27.04.2005 08:03 :: echo47 :: Replies: 4 :: Views: 1158
What is Nx64k?
If you want to divide a clock by 65536, then feed it into a 16-bit binary counter, and output the most significant bit.
Do you need help doing that?
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.07.2005 09:23 :: echo47 :: Replies: 7 :: Views: 2870
Assuming that you want to divide by the number 1024, you change your value to binary. Then shift them to the right 10 times. That will give you the desired 1024 division. Remainders will be lost.
For example, if you have 10000, and want to divide by 1024,
0010 0111 0001 0000.
shift everything right by 10,
0010 01.11 0001 0000
ASIC Design Methodologies and Tools (Digital) :: 20.12.2005 00:25 :: wwfeda :: Replies: 3 :: Views: 908
Does x.xx.xxx mean 9 minutes 59 seconds 999 milliseconds? If that's true, then you probably need a 1 kHz clock, and you probably want it to be more accurate and stable than a 555 circuit.
You could buy a crystal oscillator that is a convenient multiple of 1 kHz, and then divide it down to 1 kHz. For example, buy a 2.048 MHz oscillator and an 11-
Hobby Circuits and Small Projects Problems :: 11.12.2006 03:20 :: echo47 :: Replies: 16 :: Views: 3414
Maybe using a PLL to multiply the 32768 Hz signal by 10 and use binary counter to divide the frequency by 32768 (15 stages).
Electronic Elementary Questions :: 26.11.2007 08:54 :: rkodaira :: Replies: 6 :: Views: 2293
Sometime we have problems with scaling
the analog signal before connect to ADC.
Here I upload help file in PDF format.
And I can think it will be useful to many of us.
Microcontrollers :: 11.03.2013 04:12 :: derser :: Replies: 11 :: Views: 420
Can anyone please post a code for "16-bit binary division"..,????
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.04.2013 05:40 :: ponparithi :: Replies: 5 :: Views: 291
In case you are using CMOS IC's:
If you cascade two 4017 decade counters, you can tap the '6' outputs and feed them to the inputs of an AND gate. It will produce a pulse every 66 counts. Wire the signal so it resets the 4017's.
Or if you are using 7400 series (some of the following might have a counterpart in CMOS):
7493 '4-bit binary counter'
Electronic Elementary Questions :: 17.04.2013 01:52 :: BradtheRad :: Replies: 3 :: Views: 525
Your question is not well specified. Divide ratios are not fractional it is only 3 modulus divider binary related. Please specify your requirements and do you looking for synth, chip or separate divider chip?
RF, Microwave, Antennas and Optics :: 10.03.2004 06:53 :: xtasa :: Replies: 4 :: Views: 1342
I did it before using Microcontroller, so I'll explain the idea and you can translat it into HDL.
Suppose you have number equal 32 (in binary form and you want to covert to decimal
1- Divide 32 by 10 --> it will produce 3 and the renaider is 2
2- the remaider 2 is the least significat digit in decimal number you can use a table like to generat t
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.04.2004 04:02 :: Al Farouk :: Replies: 4 :: Views: 1443
Its becoming a habit :)
When I wanted to test out my MIDI controller (basically a UART) I used 'hyperterimal'
once set to the correct baud, its doesn't show you the wave form, but it does display what the packet is in ASCII. After all, it was designed for text. There are some progs on the net (free ones) that are similar but
Microcontrollers :: 28.08.2005 17:17 :: Buriedcode :: Replies: 5 :: Views: 930
Are you familiar with such component? can you give me datasheet or part number for it?
Look at that datasheet ( for instance, you may findyourself many.. ).
In this data sheet the formulae is defined as
fVCO = x fOSC ¸ R (A < N)
RF, Microwave, Antennas and Optics :: 01.12.2005 17:08 :: BigBoss :: Replies: 4 :: Views: 600
The normal way of making an FM receiver with digital frequency control is to make a superhetrodyne receiver that generates the local oscillator signal using a PLL. The frequency generated by the PLL is set by binary values in the programmable divider. Read some books about radio communications.
Making a fully digital broadcast FM receiver will
RF, Microwave, Antennas and Optics :: 01.06.2006 06:17 :: throwaway18 :: Replies: 3 :: Views: 1190
If you are looking for a generic solution then checkout
8254 chip documentation. If you need specific solution
then look for binary counter designs. eg. if you need divide by 5
design a counter which will count from 0 to 4 in bianary, generally
the MSB or second MSB of bianary counter will provide you the
required divided clk output.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.10.2006 03:12 :: nand_gates :: Replies: 5 :: Views: 2043
iam not clear but if i remember correctly(90%) i saw the algorithm for binary division in digital design using VHDL by roth.i dont have soft copy of it.if u find plz mail to my ID.if it is thr in the book u may get code also.
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.01.2007 09:33 :: vinodkumar :: Replies: 3 :: Views: 1217
This discussion is a few weeks old, but ...
If you are using Xilinx ISE, it includes perl: xilperl.exe.
The fractional divider technique generates jitter that may be undesirable for the application.
The DDS technique can generate a nice low-jitter clock, but it requires an external DAC, low-pass filter, and comparator. You choose the accum
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.03.2007 19:14 :: echo47 :: Replies: 17 :: Views: 5020
A flash converter is just comparators for each discrete level (for your 3-bit that would mean 7 comparators), and usually a resistor string divider to provide the reference levels for comparison.
The output of the 7 comparators then goes through "thermometer-to-binary" conversion logic to go from the 7 levels to the 3 binary outputs. (...)
Analog Circuit Design :: 16.04.2007 15:19 :: dwayne22 :: Replies: 13 :: Views: 3111
Try a CD4060, 14 Stage binary Counter/divider and Oscillator.
You find a example circuit at
Professional Hardware and Electronics Design :: 07.01.2008 16:13 :: jzo777n :: Replies: 4 :: Views: 1313
Have you heard about IEEE 754 standard. Please read about it..
Assume ur going to use a floating point divider u have to represent ur floating point numbers in a binary format and give it as an input to Xilinx CoreGen Fl
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.06.2009 15:28 :: teja321 :: Replies: 8 :: Views: 3711
The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider.
In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the m
Analog IC Design and Layout :: 27.12.2009 08:07 :: hbchens :: Replies: 13 :: Views: 4228
I am new to electronic design. I want to generate a 102.4Khz signal by multiplying a 50Hz signal using a PLL CD4046 and a binary counter/divider CD4020B.Can any one please help me out with the circuit.
Thanks in advance
Analog Circuit Design :: 26.06.2010 06:26 :: NeelaLohith :: Replies: 1 :: Views: 720
I see, that 3.2768 MHz crystals are available a most catalog distributors and qualified DIY electronics shops. May be different in your country, unfortunately.
The best way is to find a crystal with a frequency, that's an integer multiply of 100 Hz. (You need a final 2:1 DFF for 50% duty cycle). 1 MHz or 4 MHz would be a common value. Then you
Hobby Circuits and Small Projects Problems :: 27.11.2010 04:52 :: FvM :: Replies: 7 :: Views: 1768
The HC160 & HC161 are virtually identical - the HC160 is a BCD rather than binary counter so the circuit should be fine.
I have simulated it and it looks ok. The parallel load is 5 in my example so the counter counts 11 pulses (= 16 - 5).
RF, Microwave, Antennas and Optics :: 14.12.2010 04:36 :: keith1200rs :: Replies: 7 :: Views: 491
The o/p from the micro is binary representation of threshold level. (ie: 0111 for my previous example)
Monitored voltage is pulses at around + analog comparator (and, perhaps + resettable latch).
Analog IC Design and Layout :: 18.01.2011 12:56 :: erikl :: Replies: 5 :: Views: 739
I'm doing a project on BPSK and DPCM. I have used LMS algorithm for the predictor and all the values I defined are in real. But I found that computation in real especially multiplication is taking too long. I want to convert real values to fixed point binary in the format for example 110.1011. How do I achieve
Digital Signal Processing :: 15.03.2011 14:51 :: pavankumarl73 :: Replies: 1 :: Views: 861
as 74hc393 is a binary ripple counter, this means my input frequency has to be binary. But my signal will be an analog signal. in that case what kind of frequency devider will be suitable?
Professional Hardware and Electronics Design :: 21.03.2011 05:49 :: sunshineshuvo :: Replies: 3 :: Views: 1116
There is no analog comparator (like lm339 or similar) in 16F819, like on some PICs.
All you get in analog is an A/D converter, but You'd have to sample manually to get the value and determine what to do from there.
You might(?) get by if you use an input like RB0 with interrupt on falling edge, and use an resistor divider to trigger the interru
Microcontrollers :: 13.06.2011 18:08 :: bjuric :: Replies: 3 :: Views: 464
You can use a 32.768kHz oscillator and then use timer or software delay to generate 585.5Hz
Yes, 585.14 would be an integer part. An uP also gives the option to implement a fractional divider, that achieves exact average frequency, but with a jitter. Everything depends on the specification.
To achieve the exact frequency with a
Microcontrollers :: 13.07.2011 08:40 :: FvM :: Replies: 7 :: Views: 410
you can do 1s complement and 2s complement operations on it directly a multiple is not possible but other ic's like 74261 2-bit by 4-bit Parallel binary Multiplier 74274 4-bit by 4-bit binary Multiplier 74284 4-bit by 4-bit Parallel binary Multiplier
74285 4-bit by 4-bit Parallel binary Multiplier 74508 8-bit (...)
Electronic Elementary Questions :: 07.11.2011 05:34 :: akshay985 :: Replies: 3 :: Views: 374
Welcome saikrish! :smile:
What you want is a counter: each clock period counter value increases with 1. With a binary counter, the lowest significant counter bit toggles between 0 and 1 at half the frequency you input as clock. Next bit at 1/4th of input frequency, next bit at 1/8th of input frequency, and so on. For example see the timing diagr
Electronic Elementary Questions :: 04.12.2011 08:57 :: RetroTechie :: Replies: 5 :: Views: 562
its a basic question :P
I wanted to ask if i do
temp = Adc_Read(1)
to read the adc, then a value is stored in temp. is this value binary? or can it be used as an analog value within the programming? Im reading the voltage from an ultrasonic sensor. its about 2V on a small distance which should slow down the speed of the motors by pw
Microcontrollers :: 11.12.2011 12:00 :: masab_ahmad :: Replies: 1 :: Views: 566
i would like to get a circuit wich use an LDR to provide the level of light in a room. My problem is that generally an LDR is use to get a binary information( light on or off).
I want each time to know what is the information about the light level stored in a voltage or a current.
Hobby Circuits and Small Projects Problems :: 24.12.2011 09:20 :: lonkenzo :: Replies: 2 :: Views: 887
Your figures are correct but beware that with the 4MHz clock the error is about 8% which will almost certainly cause problems. As a rule of thumb, the safe error limit is about 2%
The '0x' in front of the number just means the following characters are in hexadecimal (base 16) radix. 0x0A is equivalent to 10 in decimal. It is quite normal for pro
Microcontrollers :: 10.04.2012 12:20 :: betwixt :: Replies: 5 :: Views: 1165
4-ASK may be generated by anything that creates 4 discrete (and ideally equally spaced) amplitude levels, such
Here, the FETs switch in resistors R0 & R1 according to the binary value being transmitted. These resist
PCB Routing Schematic Layout software and Simulation :: 18.07.2012 03:49 :: thylacine1975 :: Replies: 1 :: Views: 290
Hello I am trying to convert a std_logic_vector to integer. Here is how I did the std_logic_vector to integer conversion.
But this didn't gave the correct output when I enter 4 as binary (0000000100) in the simulation via Quartus II 7.2 (The device is : MAX II EPM240T100C5). I mean the divider should divide the clk b
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.09.2012 02:53 :: pini_1 :: Replies: 3 :: Views: 1114
I think johnson counter are used for clock dividing, because they are faster, because we do not need much logic for this. At least compared to a binary counter.
e.g. for dividing by four you just need 2 FF and an inverter. If the FF would have an inverting output you do only need the two FF and loop the output of one FF to the input of the oth
ASIC Design Methodologies and Tools (Digital) :: 09.10.2012 14:48 :: qieda :: Replies: 3 :: Views: 592
I am doing a divider circuit in verilog and using the non-restoring division algorithm.
I am having trouble representing the remainder as a fractional binary number.
For example if I do 0111/0011 (7/3) I get the quotient as 0010 and remainder as 0001 which is correct but I want to represent it as 0010.0101.
Can Someone help ??
ASIC Design Methodologies and Tools (Digital) :: 10.11.2012 04:31 :: SparshPatwa :: Replies: 1 :: Views: 937
I am one of those who uses the FPGA once in a blue moon. As my major part has to deal with Analog field. So am teh worst kinds of newbies you would ever find . :grin:
I have seen a lot of codes on the forum on the aspect of Division VHDL code, I found that they are pretty much useless when we want to implement them onto an FPGA board.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.06.2013 04:22 :: sai1711 :: Replies: 1 :: Views: 485
You can miminize parasitics, or you can minimize their
consequences (such as driving the bottom plate with
a stiff enough amplifier that the parasitic charge is
But you mention these "large parasitics" without any
info on where they come from, what they're doing to
Driving a large cap probably means wanting a scaled
Analog IC Design and Layout :: 05.08.2013 14:33 :: dick_freebird :: Replies: 12 :: Views: 552