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hii evrybdy, i want to design an 8-bit binary divider..its transistor level implementation..and thn i have to optimize it using its criitical delay under worst input pattern. can anybdy hlp me or guide me in this regard links , pdf files and e-books will b hlpful... hope a sooner reply thnxs in advance harry
hii everybdy.. hwz life and work goin on? i have two questions: 1)actually m a student and being assigned project to make 8-bit binary counter and to optimize it in terms of critical path..cmos implemnetation of it. SO can anybdy guide me how shuld i pursue it..i have jst 2 weeks...not more than tht.. 2)can anybdy provide me the solout
What are you trying to divide - voltage, frequency, binary number, ... ?
What is Nx64k? If you want to divide a clock by 65536, then feed it into a 16-bit binary counter, and output the most significant bit. Do you need help doing that?
Assuming that you want to divide by the number 1024, you change your value to binary. Then shift them to the right 10 times. That will give you the desired 1024 division. Remainders will be lost. For example, if you have 10000, and want to divide by 1024, 0010 0111 0001 0000. shift everything right by 10, 0010 01.11 0001 0000 You get
Does mean 9 minutes 59 seconds 999 milliseconds? If that's true, then you probably need a 1 kHz clock, and you probably want it to be more accurate and stable than a 555 circuit. You could buy a crystal oscillator that is a convenient multiple of 1 kHz, and then divide it down to 1 kHz. For example, buy a 2.048 MHz oscillator and an 11-
Maybe using a PLL to multiply the 32768 Hz signal by 10 and use binary counter to divide the frequency by 32768 (15 stages).
Hello Friends Sometime we have problems with scaling the analog signal before connect to ADC. Here I upload help file in PDF format. And I can think it will be useful to many of us.
Can anyone please post a code for "16-bit binary division"..,????
In case you are using CMOS IC's: If you cascade two 4017 decade counters, you can tap the '6' outputs and feed them to the inputs of an AND gate. It will produce a pulse every 66 counts. Wire the signal so it resets the 4017's. Or if you are using 7400 series (some of the following might have a counterpart in CMOS): 7493 '4-bit binary counter'
Your question is not well specified. Divide ratios are not fractional it is only 3 modulus divider binary related. Please specify your requirements and do you looking for synth, chip or separate divider chip? XTASA :?:
I did it before using Microcontroller, so I'll explain the idea and you can translat it into HDL. Suppose you have number equal 32 (in binary form and you want to covert to decimal 1- Divide 32 by 10 --> it will produce 3 and the renaider is 2 2- the remaider 2 is the least significat digit in decimal number you can use a table like to generat t
Maverickmax, Its becoming a habit :) When I wanted to test out my MIDI controller (basically a UART) I used 'hyperterimal' once set to the correct baud, its doesn't show you the wave form, but it does display what the packet is in ASCII. After all, it was designed for text. There are some progs on the net (free ones) that are similar but
Are you familiar with such component? can you give me datasheet or part number for it? Thanks, Look at that datasheet ( for instance, you may findyourself many.. ). In this data sheet the formulae is defined as fVCO = x fOSC ¸ R (A < N)
The normal way of making an FM receiver with digital frequency control is to make a superhetrodyne receiver that generates the local oscillator signal using a PLL. The frequency generated by the PLL is set by binary values in the programmable divider. Read some books about radio communications. Making a fully digital broadcast FM receiver will
If you are looking for a generic solution then checkout 8254 chip documentation. If you need specific solution then look for binary counter designs. eg. if you need divide by 5 design a counter which will count from 0 to 4 in bianary, generally the MSB or second MSB of bianary counter will provide you the required divided clk output. Hope
Hi iam not clear but if i remember correctly(90%) i saw the algorithm for binary division in digital design using VHDL by roth.i dont have soft copy of it.if u find plz mail to my ID.if it is thr in the book u may get code also.
This discussion is a few weeks old, but ... If you are using Xilinx ISE, it includes perl: xilperl.exe. The fractional divider technique generates jitter that may be undesirable for the application. The DDS technique can generate a nice low-jitter clock, but it requires an external DAC, low-pass filter, and comparator. You choose the accum
A flash converter is just comparators for each discrete level (for your 3-bit that would mean 7 comparators), and usually a resistor string divider to provide the reference levels for comparison. The output of the 7 comparators then goes through "thermometer-to-binary" conversion logic to go from the 7 levels to the 3 binary outputs. (...)
Hi Try a CD4060, 14 Stage binary Counter/divider and Oscillator. You find a example circuit at regards J
Have you heard about IEEE 754 standard. Please read about it.. Assume ur going to use a floating point divider u have to represent ur floating point numbers in a binary format and give it as an input to Xilinx CoreGen Fl
HI, All: The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider. In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the m
Hello Everyone, I am new to electronic design. I want to generate a 102.4Khz signal by multiplying a 50Hz signal using a PLL CD4046 and a binary counter/divider CD4020B.Can any one please help me out with the circuit. Thanks in advance Regards Lohith
I see, that 3.2768 MHz crystals are available a most catalog distributors and qualified DIY electronics shops. May be different in your country, unfortunately. The best way is to find a crystal with a frequency, that's an integer multiply of 100 Hz. (You need a final 2:1 DFF for 50% duty cycle). 1 MHz or 4 MHz would be a common value. Then you
The HC160 & HC161 are virtually identical - the HC160 is a BCD rather than binary counter so the circuit should be fine. I have simulated it and it looks ok. The parallel load is 5 in my example so the counter counts 11 pulses (= 16 - 5). Keith.
sorry I realised I described the problem badly. The o/p from the micro is binary representation of threshold level. (ie: 0111 for my previous example) Monitored voltage is pulses at around 20-50kHz. EDIT: thanks for replying Prototyp_V1.0, Am fiddling about with your suggestion, brain is fried after long day atm though :)
Hello everyone, I'm doing a project on BPSK and DPCM. I have used LMS algorithm for the predictor and all the values I defined are in real. But I found that computation in real especially multiplication is taking too long. I want to convert real values to fixed point binary in the format for example 110.1011. How do I achieve
as 74hc393 is a binary ripple counter, this means my input frequency has to be binary. But my signal will be an analog signal. in that case what kind of frequency devider will be suitable?
There is no analog comparator (like lm339 or similar) in 16F819, like on some PICs. All you get in analog is an A/D converter, but You'd have to sample manually to get the value and determine what to do from there. You might(?) get by if you use an input like RB0 with interrupt on falling edge, and use an resistor divider to trigger the interru
You can use a 32.768kHz oscillator and then use timer or software delay to generate 585.5Hz Yes, 585.14 would be an integer part. An uP also gives the option to implement a fractional divider, that achieves exact average frequency, but with a jitter. Everything depends on the specification. To achieve the exact frequency with a
you can do 1s complement and 2s complement operations on it directly a multiple is not possible but other ic's like 74261 2-bit by 4-bit Parallel binary Multiplier 74274 4-bit by 4-bit binary Multiplier 74284 4-bit by 4-bit Parallel binary Multiplier 74285 4-bit by 4-bit Parallel binary Multiplier 74508 8-bit (...)
Welcome saikrish! :smile: What you want is a counter: each clock period counter value increases with 1. With a binary counter, the lowest significant counter bit toggles between 0 and 1 at half the frequency you input as clock. Next bit at 1/4th of input frequency, next bit at 1/8th of input frequency, and so on. For example see the timing diagr
hi all, its a basic question :P I wanted to ask if i do temp = Adc_Read(1) to read the adc, then a value is stored in temp. is this value binary? or can it be used as an analog value within the programming? Im reading the voltage from an ultrasonic sensor. its about 2V on a small distance which should slow down the speed of the motors by pw
Hello, i would like to get a circuit wich use an LDR to provide the level of light in a room. My problem is that generally an LDR is use to get a binary information( light on or off). I want each time to know what is the information about the light level stored in a voltage or a current. Thank you
Your figures are correct but beware that with the 4MHz clock the error is about 8% which will almost certainly cause problems. As a rule of thumb, the safe error limit is about 2% The '0x' in front of the number just means the following characters are in hexadecimal (base 16) radix. 0x0A is equivalent to 10 in decimal. It is quite normal for pro
Hi soharca! 4-ASK may be generated by anything that creates 4 discrete (and ideally equally spaced) amplitude levels, such Here, the FETs switch in resistors R0 & R1 according to the binary value being transmitted. These resist
Hello I am trying to convert a std_logic_vector to integer. Here is how I did the std_logic_vector to integer conversion. But this didn't gave the correct output when I enter 4 as binary (0000000100) in the simulation via Quartus II 7.2 (The device is : MAX II EPM240T100C5). I mean the divider should divide the clk b
Hi, I think johnson counter are used for clock dividing, because they are faster, because we do not need much logic for this. At least compared to a binary counter. e.g. for dividing by four you just need 2 FF and an inverter. If the FF would have an inverting output you do only need the two FF and loop the output of one FF to the input of the oth
I am doing a divider circuit in verilog and using the non-restoring division algorithm. I am having trouble representing the remainder as a fractional binary number. For example if I do 0111/0011 (7/3) I get the quotient as 0010 and remainder as 0001 which is correct but I want to represent it as 0010.0101. Can Someone help ??
Hi All, I am one of those who uses the FPGA once in a blue moon. As my major part has to deal with Analog field. So am teh worst kinds of newbies you would ever find . :grin: I have seen a lot of codes on the forum on the aspect of Division VHDL code, I found that they are pretty much useless when we want to implement them onto an FPGA board.
You can miminize parasitics, or you can minimize their consequences (such as driving the bottom plate with a stiff enough amplifier that the parasitic charge is just "eaten"). But you mention these "large parasitics" without any info on where they come from, what they're doing to the circuit. Driving a large cap probably means wanting a scaled

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