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17 Threads found on Binary Divider
Look for fast binary division, booth algorithm.
Without seeing the schematic how are we supposed to tell? Each of those is a binary counter but they have different divider outputs, whether they will work or not depends on how they connect to the rest of the circuit. The CD4020 is easily available almost everywhere, just because your local shop (wherever that is) does not have them, it doesn't
In case you are using CMOS IC's: If you cascade two 4017 decade counters, you can tap the '6' outputs and feed them to the inputs of an AND gate. It will produce a pulse every 66 counts. Wire the signal so it resets the 4017's. Or if you are using 7400 series (some of the following might have a counterpart in CMOS): 7493 '4-bit binary counter'
Can anyone please post a code for "16-bit binary division"..,????
Hello Friends Sometime we have problems with scaling the analog signal before connect to ADC. Here I upload help file in PDF format. And I can think it will be useful to many of us.
I am doing a divider circuit in verilog and using the non-restoring division algorithm. I am having trouble representing the remainder as a fractional binary number. For example if I do 0111/0011 (7/3) I get the quotient as 0010 and remainder as 0001 which is correct but I want to represent it as 0010.0101. Can Someone help ??
Hello I am trying to convert a std_logic_vector to integer. Here is how I did the std_logic_vector to integer conversion. But this didn't gave the correct output when I enter 4 as binary (0000000100) in the simulation via Quartus II 7.2 (The device is : MAX II EPM240T100C5). I mean the divider should divide the clk b
The HC160 & HC161 are virtually identical - the HC160 is a BCD rather than binary counter so the circuit should be fine. I have simulated it and it looks ok. The parallel load is 5 in my example so the counter counts 11 pulses (= 16 - 5). Keith.
Hello Everyone, I am new to electronic design. I want to generate a 102.4Khz signal by multiplying a 50Hz signal using a PLL CD4046 and a binary counter/divider CD4020B.Can any one please help me out with the circuit. Thanks in advance Regards Lohith
HI, All: The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider. In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the m
Have you heard about IEEE 754 standard. Please read about it.. Assume ur going to use a floating point divider u have to represent ur floating point numbers in a binary format and give it as an input to Xilinx CoreGen Fl
Hi Try a CD4060, 14 Stage binary Counter/divider and Oscillator. You find a example circuit at regards J
The normal way of making an FM receiver with digital frequency control is to make a superhetrodyne receiver that generates the local oscillator signal using a PLL. The frequency generated by the PLL is set by binary values in the programmable divider. Read some books about radio communications. Making a fully digital broadcast FM receiver will
hii everybdy.. hwz life and work goin on? i have two questions: 1)actually m a student and being assigned project to make 8-bit binary counter and to optimize it in terms of critical path..cmos implemnetation of it. SO can anybdy guide me how shuld i pursue it..i have jst 2 weeks...not more than tht.. 2)can anybdy provide me the solout
hii evrybdy, i want to design an 8-bit binary divider..its transistor level implementation..and thn i have to optimize it using its criitical delay under worst input pattern. can anybdy hlp me or guide me in this regard links , pdf files and e-books will b hlpful... hope a sooner reply thnxs in advance harry
What is Nx64k? If you want to divide a clock by 65536, then feed it into a 16-bit binary counter, and output the most significant bit. Do you need help doing that?
What are you trying to divide - voltage, frequency, binary number, ... ?