40 Threads found on edaboard.com: Body Effect In Cmos
what is body effect in cmos?and how it will come and how it will reduced?
ASIC Design Methodologies and Tools (Digital) :: 08.09.2009 05:37 :: vamsi_addagada :: Replies: 4 :: Views: 15788
how can one tackle body effect in a circuit ?????????
Analog Circuit Design :: 13.03.2007 12:34 :: engrvip :: Replies: 10 :: Views: 943
body effect is due to voltage difference between source and body terminal so it will be present in both MOS,,,.....
ASIC Design Methodologies and Tools (Digital) :: 27.10.2007 11:26 :: A.Anand Srinivasan :: Replies: 2 :: Views: 1311
can anybody elobarate on this (MTcmos) specific applications.
Analog IC Design and Layout :: 22.02.2006 07:37 :: vijay.kumarreddy :: Replies: 5 :: Views: 3861
can anyone tell me what is body effect in cmos?
and what is meant by process in PVT conditions..
thanks in advance
Check the below link for a brief description of process, voltage and temperature variations,
ASIC Design Methodologies and Tools (Digital) :: 01.11.2011 03:34 :: f1freak :: Replies: 4 :: Views: 454
as far as i thought ,,body effects makes the threshold voltage of mosfet changes,,,so,,you must care when placing the mosfets in series that they still operate in saturation region and this depend to a great extend on the supply voltage ;as it shrinks down ,placing mosfets in series becomes more difficult
check this also
Electronic Elementary Questions :: 28.04.2006 04:09 :: husseinadel :: Replies: 3 :: Views: 1629
i am highly confuse that why do ground body pin of R, C & L in cmos device, but i know the reasion for actice device. but 4 passive i dont know the reasion.
In order to model the parasitic effect of these passive devices we need 3 terminals.... Now, the question is where do we want to connect
Analog Circuit Design :: 01.08.2006 10:32 :: pbs681 :: Replies: 4 :: Views: 596
Can anyone plz explain the body effect
Electronic Elementary Questions :: 19.06.2007 06:53 :: Shans60 :: Replies: 5 :: Views: 891
The rectifier block uses a cascaded Dickson voltage multiplier circuit with multiple cascaded sections in order to convert the extremely low input voltage up to a potential suffi cient for operating cmos circuits.
The bulk terminals of the PMOS transistors were tied to the gate and drain terminals (back-bias) to reduce the effective threshold vol
Analog Circuit Design :: 26.08.2008 10:09 :: standup :: Replies: 0 :: Views: 476
In razavi's design of analog cmos integrated circuit, chapter 3, it states/shows that body effect decrease the output resistance.
But I find it puzzling. I bias the NMOS source with a certain voltage, eg 0.3V.
Setup 1: Base and Source are connected together to 0.3V bias. (No body effect) (...)
Analog IC Design and Layout :: 17.05.2011 12:20 :: surreyian :: Replies: 2 :: Views: 742
i have a question on the substrate connection for mixed signal circuit with p-sub lightly-dopled submicron cmos process. In my mixed block, we have seperate analog vdd/gnd and digital vdd/gnd for crosstalk reduction from digital part.
I want to know the substrate connection, in my cicruit, i connected it to the analog gnd for which we beli
Analog IC Design and Layout :: 24.12.2005 02:37 :: John Xu :: Replies: 3 :: Views: 792
In MOS , there are two pn junctions formed
1) Between n+ Source and PSubstrate
2)Between n+ Drain and PSubstrate
In Kang,I read that these junctions are always reverse biased ...
How does this happen ??
If the junction 1 is to be reverse biased , then source has to be at a higher potential than the Psubstrate
But to eliminate the body ef
Analog Circuit Design :: 10.10.2006 10:41 :: its_thepip :: Replies: 3 :: Views: 1915
we know, for the MOS transistor, there is a parasitic bipolar transistor or body diode when the its body and source shorted together. I wonder if this parasitic bjt or diiode can be simulated in spice simulation?
I asked this questiion is because our circuit will trigger this parasitic diode sometimes. I hope to evaualte its affect.
Analog IC Design and Layout :: 23.01.2007 01:58 :: chang830 :: Replies: 5 :: Views: 866
You would have to calculate the value of CLM from plots.
Get the Id Vs Vds transfer characteristic for the MOS. Use the claculator function in ADE and chop the curve so that you have curve for saturation region.
Extrapolate the lines to X axis and get the early volatge value. Inverse of that would give you CLM value.
You can you equatio
Analog Circuit Design :: 06.05.2007 05:21 :: ambreesh :: Replies: 21 :: Views: 5784
we can not say which is beter or which is worse.
In different situation, the answer is different.
NMOS, the speed is better than PMOS,but PMOS can connect its bulk to its source which can avoid body effect.
cmos has very small static current in digital logic circuit.
Analog Circuit Design :: 13.06.2007 05:52 :: RDRyan :: Replies: 7 :: Views: 2745
This is the circuit from the book. You can find all the images from
For the circuit: It looks simple, works with very small Vgs-Vt due to resistor and the body effect of M5R. But you need to take into count the additional resistor noise. This is a simple one, hope it works for you.
Analog IC Design and Layout :: 29.06.2008 12:03 :: smoked :: Replies: 5 :: Views: 957
in layouts I have seen, usually dummy transistors are used when the source is connected to vdd or vss (PMOS or NMOS respectively). no body effect to worry about.
can you use dummy transistors when the PMOS source is connected to the well to remove the body effect (standard cmos (...)
Analog IC Design and Layout :: 28.06.2008 11:32 :: dac5bits :: Replies: 2 :: Views: 788
hi, I read "Noise in Current-commutating cmos Mixers",in this paper, he said "
it is worth noticing that no specific value of VT is needed to calculate the drain current of M1 and M2. The behavior ofthe switching pair is independent of VT and therefore to a first order is independent of the body effect and the common-mode
LO voltage. This (...)
RF, Microwave, Antennas and Optics :: 27.12.2008 04:18 :: bibi0413 :: Replies: 1 :: Views: 476
how these effect the performance of short channel and long channel?
body effect, velocity saturation channel length modulation, hot carrier, cmos latch up effect.
which effect is more prominent in short channel and why?
Electronic Elementary Questions :: 25.04.2011 11:33 :: syeda amna :: Replies: 3 :: Views: 894
Hi everyone! I am reading a paper about a cmos LNA design. But I am not sure where the parameters' values of a cmos technology are from???
The process used in the paper is SMIC 0.18um RF cmos processes. The values cited are:
(1) Gate oxide capacitance per unit area, Cox=9mF/(m^2);
(2) body effect (...)
RF, Microwave, Antennas and Optics :: 05.04.2012 13:24 :: jianke :: Replies: 1 :: Views: 417
that is a psrr problem. look at increasing the psrr of your error amp by cascoding mirrors at the top and bottom of your diff pair. you also need to increase length way beyond 0.18u. not sure what gds would be in your process, but start at 1um and work up. I think somewhere around 2um for pmos and 5um for nmos will be a good guess but you need
Analog IC Design and Layout :: 04.03.2004 00:13 :: electronrancher :: Replies: 1 :: Views: 1762
One of the biggest. You could simulate your regular working analog cmos circuit is you modify each
bulk. For PMOS and for NMOS make an additional series RC network. That mimic the floating body. But
negleate the intercoupling. So you now that about 20-30% of the gate charge is put into substrate.
Now also the sereis RC network react by controlli
Analog IC Design and Layout :: 14.07.2004 10:17 :: rfsystem :: Replies: 1 :: Views: 1113
you should think about the mos case (no base current).
for example. a cmos voltage follower has 3v on the gate, so the source wants to rest at about 3v-Vth, maybe 2.2v or so. it's drain is connected to VDD, so it can just POUR current into the load to satisfy Vout=2.2v, therefore it is considered VERY low output impedance.
only problem i
Analog Circuit Design :: 08.11.2004 22:26 :: electronrancher :: Replies: 9 :: Views: 2047
vt is a parameter of channel lenght in both pmos and nmos. this effect is called channel modulation effect considered with parameter lambda in the equation of cmos current equation.
the best way to bypass this altering effect is to connect source to bulk of the mosfet.
I think what you said should be (...)
Analog IC Design and Layout :: 25.03.2005 09:53 :: Alles Gute :: Replies: 15 :: Views: 6393
Deep Nwell process is for RF purpose and needs extra mask and charge.
But it offers better noise performance and the cascode device will not have body effect.
Analog IC Design and Layout :: 13.05.2005 09:34 :: yibinhsieh :: Replies: 6 :: Views: 1489
i run hspice simulations recently, found that the threshold voltage is different for same device, i mean other than body effect, is there any other factors affect threshold voltage?
I guess you better clarify what's mean "the same device"
Same W, same L, same biasing condition ????
Otherwise, it is very difficult to
Analog Circuit Design :: 16.12.2005 09:36 :: scottieman :: Replies: 8 :: Views: 1216
substrate are negative biased in Digital and most Analog Circuit, which meas the p-substrate is connected to VSS, and n-substrate is connected to VDD.
however, this would could cause body effect when source are not connect to ground or supply.
ASIC Design Methodologies and Tools (Digital) :: 01.03.2006 08:03 :: jackson_peng :: Replies: 7 :: Views: 1323
the inverter acts like a weak buffer. with a reduced noise margin/ output voltage swing.
H= Vdd -Vthn
L= Vss + Vthp
Reasono for this is body effect .. look it up in google.
ASIC Design Methodologies and Tools (Digital) :: 24.05.2006 23:06 :: rogger123 :: Replies: 6 :: Views: 958
Does the body effect limit the number of transistors that can be placed in series in a cmos gate at low frequencies. Please explain
Electronic Elementary Questions :: 04.10.2006 13:38 :: blackhawk_ :: Replies: 2 :: Views: 620
Thank you.I got it.
If we use PMOS instead of Nmos,How to connect the Pmos substrate ?Using floating Nwell?
As far as I known, there are at least 3 solutions:
1. Floating well, as you mentioned.
2. Dynamic substrate connection switching: At least 2 methods. Please refer to
a. Pierre al, "
Analog Circuit Design :: 07.12.2006 23:14 :: ycj :: Replies: 4 :: Views: 886
Here are some Questions.........
Explain why & how a MOSFET works
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation
Explain the various MOSFET Capacitances & their significance
Draw a cmos Inverter. Explain its
ASIC Design Methodologies and Tools (Digital) :: 10.04.2007 08:21 :: Guru59 :: Replies: 8 :: Views: 6643
For two MOS transistors both of them should have source connected to well to prevent body effect.
So if your substrate is p-type use PMOS, if substrate n-type use NMOS.
Analog IC Design and Layout :: 04.06.2007 06:40 :: Fom :: Replies: 13 :: Views: 1039
For the below two topology, I thought the linearity of (b) should be better than (a) for there is no body effect. However, the Specture simulation results show that (a) is better than (b). Anyone know why? Thanks
Analog Circuit Design :: 25.12.2007 00:11 :: noiseless :: Replies: 2 :: Views: 401
Thank you! timesmile!
A：dnwpw is the model name, and you have to provide model info for spectre。
Q：i'm using chrt 0.18 rf pdk. and i can find the model of dnwpw_1p8 in the pdk models. but there is no model for dnwpw. how could this dnwpw be produced ,
A：The problem may be fixed by renaming that mod
Analog IC Design and Layout :: 21.11.2008 10:27 :: timesmile :: Replies: 3 :: Views: 1263
I use 0.18um cmos process to design my opamp, and the telescopic structure with Nmos input transistor is used. The body of input transistor is connected to gnd, however i find that when i do corner simulation, the opamp works abnormally at some corner condition, and the problem comes from the large vth variation of the input Nmos.
Analog Circuit Design :: 23.10.2009 05:50 :: iamxo :: Replies: 3 :: Views: 713
These are only three current mirrors: the linearization is achieved by using a wide M5R so its Vgs~Vth hence (neglecting body effect): the voltage across the resistor in the source of M5R is VinVCO-Vth and the branch current is (almost) linear
If you have problems mirroring accurately you should still be able to increase L to reduc
Analog IC Design and Layout :: 10.03.2011 18:18 :: dgnani :: Replies: 12 :: Views: 1761
Substrate or body effect is discussed more detailed in paragraph 2.3 As an intuitive explanation, the subtrate acts as a second gate or backgate with it's own transconductance contribution. Because substrate and gate are both grounded AC-wise in the diode load configuration, the total transconductance and in return the source output c
Analog Circuit Design :: 13.01.2012 02:54 :: FvM :: Replies: 4 :: Views: 355
So, what happens when the source/bulk of the NMOS transistor is biased positively?
Will the bulk/body voltage rise, due to a current injection (majority carriers - holes) into the substrate, that will be picked up (extracted from the substrate) by the neighboring p+ contacts / guard rings?
Do you want to account for that body voltage increase in
RF, Microwave, Antennas and Optics :: 10.08.2012 02:05 :: timof :: Replies: 1 :: Views: 483
Has any body designed low noise Operational Amplifier? In which way you minimized the noise? What i mean is mainly based on cmos process.
Analog Circuit Design :: 12.06.2005 23:30 :: tia_design :: Replies: 4 :: Views: 673
CAN ANY body GIVE ME GOOD DOCUMENTATION ON SHORT CHANNEL effectS PLEASE.
Analog IC Design and Layout :: 19.03.2008 00:42 :: sridhar540 :: Replies: 3 :: Views: 711