1000 Threads found on edaboard.com: Cable Model Simulation
Can anyone tell me how to convert S-parameter cable model in touchstone format to Spice format so that I can simulate in Hspice?
Analog Circuit Design :: 11-13-2009 02:28 :: firstname.lastname@example.org :: Replies: 3 :: Views: 2743
Hello everybody! Does anyone experience to make coaxial cable model (not straight line model. It must be curved line) by using HFSS? If someone has make it can you explain a little bit how you was make it and what materials you was use in this model.
Electromagnetic Design and Simulation :: 11-19-2004 03:28 :: luumar :: Replies: 1 :: Views: 2677
TSMC.18 model simulation error!! use spectre model
hpeesofsim (*) 2005A.400 Aug 5 2005 (built: 08/05/05 22:12:30)
Copyright Agilent Technologies, 1989-2005.
Compiling Verilog-A file
AGILENT-VACOMP (*) 2005A.400 Aug 5 2005 (built: 08/06/05 01:59:36) (...)
Software Problems, Hints and Reviews :: 06-12-2006 14:30 :: czn :: Replies: 1 :: Views: 929
Hi all, please tell me how to model cat5 cable in 100/1000M ethernet PHY transmitter simulation , I am pullzed in this for several months.
IEEE 802.3 only gives 10M cable model , but it doesnot fit for 100/1000M.
Thank you in advance!
Analog IC Design and Layout :: 07-01-2008 22:14 :: wwwww12345 :: Replies: 0 :: Views: 1389
If I have a touchstone 8-port cable model, how can I do the simulations in Hspice for transient analysis and also the S-parameters, can u give me an example?
Analog Circuit Design :: 11-17-2009 21:16 :: email@example.com :: Replies: 7 :: Views: 2309
If I am using BSIM model for simulation. Do I need to key parameter like AD, AS, PD and PS. Does BSIM model account for these parameters in the simulation?
Analog IC Design and Layout :: 07-13-2006 11:34 :: tfwee :: Replies: 2 :: Views: 1218
i have downloaded the .zap file of ATF36163 from avago website.but when i start the DC simulation with ADS2008,it said that :
simulation / Synthesis Messages
Warning detected by hpeesofsim during DC analysis `DC1'.
Matrix is singular (detected at node or branch `X1.L56.i').
Warning detected by hpeesofsi
Electromagnetic Design and Simulation :: 09-24-2009 06:57 :: mariapeter :: Replies: 2 :: Views: 2650
I have imported LT op amp simulation sub circuit model from LTSpice library (.mod) file. I did it by simply changing ext from .mod to ckt.
Altium Accepted this model.
However when it came to simulation it looks Altium does not understand SPICE.
The line which cause error:
ESHD1 88 0 (...)
PCB Routing Schematic Layout software and Simulation :: 12-16-2009 11:00 :: joanna_seczkowska :: Replies: 0 :: Views: 4118
how can i get relatviely accurate W-element U model form of RG58 coaxial cable?
i want to simulate the coaxial cable with hspice simulator.
RF, Microwave, Antennas and Optics :: 06-20-2010 10:46 :: prcken :: Replies: 2 :: Views: 1262
I want to simulate o dc booster in spice. I would like to make a model simulation of Lbreak. I try values from 1u to 1m but I'd like to have results after a period of time. As it is known a dc booster gives results after some mseconds. How could I make a model simulation of Lbreak after, for example, 10mseconds?? (...)
Software Problems, Hints and Reviews :: 05-20-2013 10:13 :: johnnysp :: Replies: 0 :: Views: 359
I need your help. I'm trying to make a pv cell model to charge a capacitor in my simulation in Proteus ISIS.
I have made model attached, but the current and voltage at the output are inverted (i.e. negative).
I have searched the web for a functioning model or proper explanation with no success. (...)
Power Electronics :: 05-03-2014 01:12 :: kel :: Replies: 0 :: Views: 678
who have LVDS cable model ( DVD rw pick-up head cable )
I measure real LVDS signal have "overshoot /undershoot"
but in spice I use delay-line , waveform is very good ..
by the way , have anyone simulation eye pattern for LVDS ?
Analog IC Design and Layout :: 04-08-2004 21:34 :: andy2000a :: Replies: 18 :: Views: 5842
I'm asking for a software tool for implementing the clients server model simulation blocks .
Software Requests :: 05-10-2006 03:53 :: marwa75_ibrahim :: Replies: 1 :: Views: 291
I would like to use different mutual coupling in LTSPICE but I think it doesn't work.
I have a three wire cable model with their 3 inductances L1 L2 L3
I would like to use these coupling :
K1 L1 L2 0.3
K2 L2 L3 0.7
K3 L1 L3 0.7
I have the analytical formula to determine the equivalent inductance, and when I want to compare simulati
Software Problems, Hints and Reviews :: 01-11-2007 03:45 :: yann59 :: Replies: 0 :: Views: 956
Can anyone tell me about the design flow on how the bsim model is created?
Thanks in advance.
Analog IC Design and Layout :: 08-16-2007 21:59 :: richloo :: Replies: 1 :: Views: 1042
Can anyone tell how can i do behvioral level sumlation of my analog circuit???
is it possible in SPICE or ORCAD will be more useful as i have heard from others??and how is it to learn ORCAD???
Analog Circuit Design :: 10-16-2007 12:28 :: engrvip :: Replies: 8 :: Views: 826
Hey can anyone tell me where I can download SPICE model for IR2110....
Analog Circuit Design :: 12-28-2007 06:43 :: elankart :: Replies: 1 :: Views: 4142
Has anyone made Spatial Channel model for MIMO according specification
3GPP TR 25.996 v8.0.0 (2008-12)?
I am trying to simulate,according to this specification, MIMO channel in
I have few issues to discuss about random variables incorporated in this
I would be grateful for finding someone eager for chatting this
Digital communication :: 06-25-2009 17:50 :: thefczyc :: Replies: 0 :: Views: 1347
Are you still be able to convert touchstone S-parameter format into Spice format?
I have a USB30 cable model and I need to convert it into spice
Electromagnetic Design and Simulation :: 11-13-2009 02:25 :: firstname.lastname@example.org :: Replies: 16 :: Views: 3529
I followed the method of kundert and constructed a pll time domain model to simulate the total phase noise.The model can work correctly,but when I extended it to sigma-delta fractional pll,the output phase noise seems unreasonable.The sigma-delta modulator is a MASH1-1-1 one.I wanted to see the output phase noise only from sigma-delta
Analog IC Design and Layout :: 09-10-2009 04:57 :: hhq414 :: Replies: 4 :: Views: 1220
I am simulating USB Transceiver IBIS model through HSPICE.I have OE for Output enable/disable,SPD for selecting LowSpeed/FullSpeed,SUS to suspend the IO.
Can any one help me how to instantiate the SPD control pin in the SP file and run it through HSPICE.
Analog Circuit Design :: 11-13-2009 07:30 :: bharatsmile2007 :: Replies: 0 :: Views: 979
I want to calculate the current flowing in the outer conductor of the Coaxial cable in case of mismatching at the load of the cable in HFSS. I have simulated the simple coaxial cable model in HFSS...Can anyone guide me how to measure the current flowing in the outer conductor of the Coaxial cable under (...)
RF, Microwave, Antennas and Optics :: 03-15-2010 03:45 :: jawadysf :: Replies: 0 :: Views: 893
I am simulating an IBIS model in HSPICE..can anyone give a small demo example code for doing the same?
Analog Circuit Design :: 04-24-2010 12:34 :: milind_tile :: Replies: 0 :: Views: 724
Yes, it's a low capacitance (large D/d ratio), resistive wire coax cable. Exact simulation may be difficult, because the lossy line models of most simulators are representing the loss frequency characteristic (mainly set by skin effect losses) rather poor. I know the Aplac simulator as an exception, there may be others.
Analog Circuit Design :: 06-28-2010 14:35 :: FvM :: Replies: 12 :: Views: 2000
I think, the basic question is, if AWR has a suitable cable model and is using it in time domain simulation? Did you calculate the expectable pulse response by hand?
Electromagnetic Design and Simulation :: 04-19-2011 15:48 :: FvM :: Replies: 3 :: Views: 1099
For the time being, just assume ?r = 1 and G = 0, which correctly represents an isolating and non-magnetic medium. If you expect any benefit from the lossy cable model, you should however put in a frequency dependent R value for the intended operation frequency, which will be surely much higher then the DC resistance you calculated above. If the ob
Analog Circuit Design :: 06-06-2011 11:30 :: FvM :: Replies: 3 :: Views: 403
I added LT1009 spice model to Pspice library. When I am trying to simulate, I am getting the following error:
.SUBCKT LT1009 1 2 3
RBIAS 0 12 1
IBG 0 12 1.249
ECOMP1 11 0 1 2 0.5
GTEMP 0 12 21 22 1E-3
R3 0 21 100
ERROR -- Missing node
**** EXPANSION OF SUBCIRCUIT X_U34 ****
X_U34.RBIAS 0 X_U34.12 1
Analog Circuit Design :: 07-26-2011 00:26 :: helpforpspice :: Replies: 2 :: Views: 657
I am using ISE suite 13.3.. I am simulating behavioral model fine, but when I am trying to simulate the post route model I get these errors, when modelsim opens.
model Technology modelSim DE vcom 6.5e Compiler 2010.02 Feb 26 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# ** (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-13-2012 20:02 :: qwerty_asdf :: Replies: 3 :: Views: 692
Does anyone know if EMcos EM studio or Feko 6.1 has bi-directional capabilities for cable bundle simulation similar to what is available in CST cable studio? Which is easier to use for complex cable harness simulation in aircrafts?
Electromagnetic Design and Simulation :: 07-03-2012 17:57 :: Element7k :: Replies: 1 :: Views: 643
I am designing a 2D model of a three-phase core-type transformer in ANSOFT MAXWELL 14.0. While doing so I have encountered a strange problem.
Start of the problem:-
While designing the transformer, I wanted to incorporate core losses. So, I did the following steps:-
Excitations -> Set Eddy Effects -> checked the various core section
Electromagnetic Design and Simulation :: 02-06-2013 22:05 :: Shantanav :: Replies: 0 :: Views: 874
this is my first post in this forum.
I have designed an MPPT (maximum power point tracker) in proteus and need Photovoltatic model for test the circuit .
I know PV model consist of diode and current source but i pick those model from proteus's Library and the result of it is not correct for me
the I-V characteristic is like below (...)
Power Electronics :: 03-12-2013 07:22 :: h1368 :: Replies: 3 :: Views: 796
i am working on comparator and i want to include bsim model for cmos in lt spice ...can anyone tell me how to do this??
and fro where can i download it...becuase i have download i from
but i dont know which file i have to add in lt spice and how to add it...please someone help
Power Electronics :: 03-26-2014 21:18 :: rizwan rashid :: Replies: 0 :: Views: 307
can anybody provide me 1n6642 pspice model or is there any equivalent for 1n6642 with same physical characteristics,
pls reply soon
Analog Circuit Design :: 03-28-2014 08:12 :: shrinivas.gotur :: Replies: 1 :: Views: 411
Does anyone have experience in simulate using smartmodel and design using xinlinx isev4. I want to construct a board level simulator enviroment using these two tools. I need using smartmodel's 386 model and fpga designed using xinlinx. How can i do this?
ASIC Design Methodologies and Tools (Digital) :: 07-10-2002 07:56 :: zhoury :: Replies: 2 :: Views: 1562
I can to program it
The hardward is connected as:
use Xilinx ISE 4.3i sp3's iMPACT to read , use ScanChain mode, when initial Chain,error comes:
Professional Hardware and Electronics Design :: 10-15-2003 22:37 :: liuzhili :: Replies: 3 :: Views: 2065
hi, i build some code in spartan 3, but there is strange thing in "simulation model" simulation. chip is not responding on signals before there was 10 clocks. then work as was designed. does it need some "warm up" time? to warm up all cathodes in tranzistors? :))
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-27-2004 02:32 :: Mazi3 :: Replies: 0 :: Views: 727
this question might be a little bit of topic under ASIC design tools - but I didn't found a better place - and methodologies fits at least a little bit ...
Could someone guide me to some material that explains how "reduced matrix spice solvers" like HSim are working in principial and how/why they gain their speed advantage towards
ASIC Design Methodologies and Tools (Digital) :: 04-25-2005 10:01 :: avt :: Replies: 1 :: Views: 1194
a problem about modelSim , It is expressed by a picture.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-30-2005 04:53 :: ymq8328 :: Replies: 3 :: Views: 643
Which book is the best one for us to study switching power!!
Analog IC Design and Layout :: 05-14-2006 02:57 :: pswatw :: Replies: 23 :: Views: 2953
Who is doing the research on the pipeline adc using estimatioin method?
how I can deceide the parameter inside in order to do the behavior model simulation
Analog Circuit Design :: 10-22-2007 11:01 :: shineqi :: Replies: 0 :: Views: 568
In the verilog model simulation(NC-SIM), when Q_i changes, Q0 doesn't change at all...
who can help me on this?
ASIC Design Methodologies and Tools (Digital) :: 02-23-2009 04:10 :: bradyue :: Replies: 0 :: Views: 440
i heard the models given by a foundry is the most important staff in the design of a chip. and i have some models found in the internet. but i don't know whether or not my models is suitable for my design , for example, a switched capacitor circuits? so who can tell me the method of testing the models ? (...)
Analog Circuit Design :: 03-27-2009 03:19 :: bm429 :: Replies: 3 :: Views: 678
Hey, I am desiging an 800MHz LNA. The spec for it its S11 and S22 <-10, NF<0.8 and Gain preferably as high as possible.
Before biasing the network, i would able to get those results. After biasing it, i failed to achieve the goal that i want. Could anyone help me in this?
I need it urgently.
RF, Microwave, Antennas and Optics :: 06-02-2009 12:13 :: jun86dia :: Replies: 4 :: Views: 1143
Please help to check the attached schematic of Transmission line pulse generator and its corresponding waveforms at each node.
S1 is a switch controlled by the voltage pulse “swctl” as shown in the picture, when swctl is 0V, S1 is open (huge resistance), when swctl is 1V, S1 is closed (zero resistance).
I have 2 questions:
RF, Microwave, Antennas and Optics :: 06-22-2010 11:43 :: prcken :: Replies: 1 :: Views: 651
Hi, everyone. I want to design a PLL, and never have designed it before. Could you tell me what the procedure of pll design? Is it firstly caculate each blocks' spec, phase noise, bandwidth, Kvco and so on, then do each block design?
Thanks you very much!
Analog Circuit Design :: 05-21-2011 07:22 :: incol :: Replies: 6 :: Views: 825
I was working with Linecal utility in ADS to design a coaxial cable model. Generally when you select the component it shows a component illustration window with a nice diagram showing all the parameters on the sketch. For some reason I am not getting to see the picture inside the linecal. This is for any of the component I try to work in Line
Electromagnetic Design and Simulation :: 05-26-2011 03:28 :: abbeyromy :: Replies: 0 :: Views: 681
HELO .EVERY BODY
HOW CAN start to DESIGN lna in hfss
RF, Microwave, Antennas and Optics :: 08-04-2011 01:24 :: t_heidari_elc :: Replies: 2 :: Views: 516
I am going to design UWB filter with bandwidth (3.1 to 10.6)GHz. Kindly suggest me best software to design this filter. I have 5 options (HFSS, ADS and AWR -MO, sonnet and CST).
Software Links :: 05-11-2012 05:45 :: sohkha :: Replies: 2 :: Views: 57
What softwares are available to simulate SIM300 GSM Module?
Electromagnetic Design and Simulation :: 03-08-2013 08:12 :: qwwq :: Replies: 0 :: Views: 367
I am stuck on a part of my design. I would be greatful for any help/info given.
I am trying to design a circuit in Proteus from datasheet EL5170 by Intersil page 10 Figure.22 single supply twisted pair.
The chip is not in the ISIS library so I have designed it my self. I designed the chip by looking at the datasheet and assigned a packa
Analog Circuit Design :: 10-27-2013 06:23 :: phat1 :: Replies: 5 :: Views: 1318