1000 Threads found on edaboard.com: Cadence Cdf
from the CIW window: choose: Tools >> cdf >> Edit
Brouse for you MIM, use Edit/Add paramters to modify it to what you aim to be.
Read cadence cdf user manual for more details.
hope this helps,
Software Problems, Hints and Reviews :: 12-02-2006 01:18 :: ahmad_abdulghany :: Replies: 2 :: Views: 1729
For more details of cdf you can refer 'cdfuser' ie the Component Description Format User Guide in the cadence Documentation.
Analog IC Design and Layout :: 03-03-2005 06:00 :: gunturikishore :: Replies: 5 :: Views: 7293
suppose that i have created a symbol for a circuit that includes 2 NMOS's.....let call them NMOS_1 and NMOS_2.
now, i wish to use multiple instances of this symbol to build up a bigger circuit.....but i wish to be able to have different values for W of NMOS_1 & 2 for each of the instances.
i am told that this
Analog IC Design and Layout :: 04-20-2006 09:58 :: tsb_nph :: Replies: 4 :: Views: 8070
I am not sure is this the right place to ask.
What are these? Why they are done ? are they necessary?
The layout drawings has only two colors,how to fix them?
You should read about this in the cadence documentation...
cdf is the Component Description Form, the part of the database that is mostly used for Analog
Linux Software :: 06-10-2008 04:40 :: n1cm0c :: Replies: 7 :: Views: 4859
Yeah I know that cdf is something using which we can change the most basic parameters of the components. But, one question always linger my mind. When I say refresh (Ctrl+r ) in the cadence/icfb window, it pops up a window where it asks "refresh cdf's? ". below this question there will be many cells from the analog lib and other (...)
Analog IC Design and Layout :: 09-22-2014 02:53 :: starinspace :: Replies: 0 :: Views: 210
How to create an instance using skill languahe in cadence, say NMOS.
I have seen the syntax for creating instance
dbCreateInst( d_cellView d_master t_name l_point t_orient
To be specific what should I enter for d_master.
Also how can we edit the parameters like width and length of nmos
Analog IC Design and Layout :: 06-11-2004 02:48 :: Hughes :: Replies: 5 :: Views: 7894
I'm looking for tutorials on PCell generation in cadence Virtuoso. Is there any documention or tutorial that could help?
Analog IC Design and Layout :: 02-01-2006 07:50 :: DoctorProf :: Replies: 4 :: Views: 6559
I used cadence IC5141 to do EXPORT -> CDL for some schematic diagram as below,(see attachment)
I always got a poor netlist as:
XI13 net043 net23 inv
XI4 net23 XPA XPB XPC nand3
But, what I need is as:
XI13 net043 net23 inv lp=0.35 ln=0.35 wp=1.6 wn=0.8
XI4 net23 XPA XPB XPC nand3
ASIC Design Methodologies and Tools (Digital) :: 02-04-2006 03:09 :: sean202 :: Replies: 2 :: Views: 1632
What I will say will probably used against me at th ecourt of law but anyway - TSMC does not create their PDKs. Those are done by cadence and there ARE disconnects. I did not see ANy PDK working 100% yet.
My personal and private opinion is that if they would provide perfect pDK and something would go wrong , companies would use it against them and
Analog IC Design and Layout :: 03-25-2006 22:22 :: Teddy :: Replies: 6 :: Views: 1563
I've a netlist that describe a circuit.
In cadence, generally, we draw schematic and a corresponding symbol. We then connect the symbol with Signal source for simulation.
Instead of schematic, can I draw a symbol that point to this netlist and then connect the symbol with signal source for simulation? Can it be done and how?
Analog Circuit Design :: 06-30-2006 11:04 :: yolande_yj :: Replies: 5 :: Views: 1890
I don't remember. U can look for cadence documentation (for ex. verilogamsref).
Analog IC Design and Layout :: 08-04-2006 03:41 :: DenisMark :: Replies: 9 :: Views: 6849
This is not a cadence option, it is a design kit option. U can find the equation from the process documents.
Analog IC Design and Layout :: 08-07-2006 04:57 :: eng_Semi :: Replies: 4 :: Views: 1094
I don't mean it, but anyway, it's not a very repeatively needed thing, i can do it from CIW window directly, thanks,
But, if you have a pdf contains as many as possible of cadence Virtuoso Schematic, Layout, analog environment, etc. and any other keyboard bindkeys and short-cuts, so please attach it to your next reply.....
Analog IC Design and Layout :: 11-20-2006 12:52 :: ahmad_abdulghany :: Replies: 5 :: Views: 1203
Did anyone try to make the cdf parameters for a component using SKILL on cadence before?
I want to write it for an MIM capacitor..
How can i attach it to the symbol after creation? In other words, how to point to that SKILL file containing parameters?
Thanks in advance,
Analog IC Design and Layout :: 11-30-2006 09:32 :: ahmad_abdulghany :: Replies: 2 :: Views: 1614
Maybe the V5 waveform type is not defined. it is a bug in old version cadence. You can copy the V5 from the analogLib to your own lib, then edit the cdf of V5, you can define the waveform type
Analog IC Design and Layout :: 06-17-2007 22:35 :: pfd001 :: Replies: 5 :: Views: 3214
I am using IC5.0.33 in Fedora Core 4. The cadence runs fine except for the following things:
1. When I open a schematic and try to check the properties of transistor or
resistor or any other component then the parameters like the lengt, width,
multiplier etc. do not show up. All the cdf parameters are absent.
Electromagnetic Design and Simulation :: 08-10-2007 19:12 :: bibhudattas :: Replies: 0 :: Views: 846
there are many ways to extract netlist from schematic in the cadence.
I used one among many way. it was cdl extraction method. extraction process is following figure.
Question : in Initialize Environment, Simulator Name is "Other : cdl".
When I want to modify some device or model name, what I have to modify to change device parameter?
Analog Circuit Design :: 10-28-2007 20:53 :: 020170 :: Replies: 5 :: Views: 5278
Under the cadence schematic design environment, I get a device symbol from the PDK, then attach it to it's model file. In that case, the simulation result is strange and wrong.
If I get the symbol from the analoglib, the simulation result will be all right.
I don't know what happened here. Is it something wrong with the configurati
Analog IC Design and Layout :: 06-28-2009 02:15 :: ddrr :: Replies: 3 :: Views: 739
Open your symbol and save as Spectre view. Try to generate the netlist and see that the symbol is identified in the netlist first including the interface pins.
Probably you need to modify cdf also if it dont work after that also. Open cdf for the symbol and include the pin list in the "Simulation Information" section of the symbol. Later you mig
Analog Circuit Design :: 09-16-2009 22:01 :: gunturikishore :: Replies: 1 :: Views: 2023
Firstly, I use Spectre, mmsim-72, cadence 5.10.41.
I have an interesting problem. I want to measure the drain current of a nMOSFET; however I get different results based on what I actually look at. Here is what I mean:
1. If I simply click to the drain terminal of the NMOS and plot the transient current, I get one value.
Linux Software :: 01-22-2010 09:24 :: andich :: Replies: 2 :: Views: 880
I have .cir file and I want to create part in cadence virtuoso with that model.
Is it possible?
Analog IC Design and Layout :: 12-20-2010 04:46 :: sarge :: Replies: 4 :: Views: 5087
in cadence i hav simulated the circuit and tried to plot node transient response,but it doesn't
showing the plot, a warning (no "VT" data for node "/netxxx" ) is displayed in the icfb window
can anyone help me how to eliminate the warning " no VT data for node xxx in cadence".
Analog IC Design and Layout :: 03-15-2011 02:33 :: surender.k :: Replies: 2 :: Views: 1138
I established a voltage source model(named vsrc) based on the standard voltage source model(vsource) in cadence. I want to use it in my monte carlo analysis. But there in no model name in cdf of vsource, so my new model could not be found by .scs file. when the netlist is created, voltage sources in my circuit are always been created based on vsour
Analog Circuit Design :: 04-06-2011 06:39 :: jing.tutallinn :: Replies: 3 :: Views: 536
I'm using cadence IC6.1.4. I'm trying to annotate the operating point information on the schematic for the transistors and I can't. Transistors are defined as primitives, not subcircuits. Similar to the nmos and pmos from analogLib (for which I can annotate the op). I can annotate the node voltages but not the id, vgs, vth, gm etc. However,
Software Problems, Hints and Reviews :: 05-03-2011 13:43 :: sutapanaki :: Replies: 0 :: Views: 1544
Do you know if i can change the temperature coefficient of a resistor in my simulation and how? I am using cadence.
Thank you very much
Analog IC Design and Layout :: 05-23-2011 09:05 :: geozog86 :: Replies: 3 :: Views: 925
i want to divide the o/p freq of Quad-VCO i.e. 4.8 GHz into 2.4 GHz. for this purpose i need a freq divider ckt.
i saw the freq divider from RF library in cadence. it is containing 4 pins (pin, pout,nin, nout).
how to apply stimulus to this pins & check the o/p
what does nin & nout stands for????????????
RF, Microwave, Antennas and Optics :: 11-15-2011 01:19 :: ddis :: Replies: 7 :: Views: 1181
I think you are trying to pass a swept variable in ADE L with name "w" that is the naming of transistor's width at the cdf so they conflict and that's why you get this error.Avoid using names for your variables that already are part of the cdf.
HI jimito13, thank you for your reply but I didn't have any variable w.
Analog IC Design and Layout :: 12-20-2011 16:50 :: gift4jo :: Replies: 2 :: Views: 1025
I'm wonder does any one knows that if its possible to get the cdf (cumulative Density Function) diagram in cadence spectre?
or it should be done through Matlab
Appreciate for help and hints
Analog Circuit Design :: 02-17-2012 09:33 :: farid82xxx :: Replies: 0 :: Views: 435
what's the difference between the job of cdf parameter, which can be set manually in cadence build-in dialog window when try to "i" an part on the schematics, and that of simulation model file, like .scs, which is loaded in the procedure when try to do spectre simulation?
Maybe some parameters are overloaded or dependence between parameters of t
Software Problems, Hints and Reviews :: 02-07-2013 06:48 :: iamyuchenjie :: Replies: 0 :: Views: 407
PSPICE syntax is pretty classic, from what I see of vendor
device models; the command interface, I have not used.
But I import PSPICE models to cadence often enough, with
no trouble (as long as I remember to add
as a header line).
If you're already working in the cadence environment I'd
forget about the PSPICE step, just
Analog Circuit Design :: 03-13-2014 18:04 :: dick_freebird :: Replies: 6 :: Views: 566
Thanks for reply. I can edit cdf once I created cellview. But I am not able to create cell view. when I am trying to create cellview it shows syntax error in verilog code. Can u plz helpme ???
Yes, the cadence-spawned veriloga editor will automatically
check syntax and you may have to save-as
Analog Circuit Design :: 08-11-2014 11:48 :: dick_freebird :: Replies: 4 :: Views: 492
in my memory,Analog Artist contain many source include FM Am sin ,pulse and so on,you can directely use it for simulating,in fact if you can devolp the .cdf file,you can input anything for entring for any tools can be integreting in cadence.
read the help of cadence carefully,you can find the results
ASIC Design Methodologies and Tools (Digital) :: 02-21-2002 21:48 :: nmtr :: Replies: 11 :: Views: 4456
If you are after some better documentation than what openbook may provide please have a look all * to t)
At the above site there are real manuals for C@dence and which hold a lot more info than openbook.
On 2002-04-26 02:37, cuiyujie wrote:
Openbook from cadence is
ASIC Design Methodologies and Tools (Digital) :: 04-30-2002 20:45 :: Pim :: Replies: 2 :: Views: 1407
I am looking for Cell library or Design kit for cadence IC 4.4x
If anyone has it, please PM me.
ASIC Design Methodologies and Tools (Digital) :: 06-14-2002 01:00 :: iop3001 :: Replies: 7 :: Views: 2246
the cadence ic 5.0 bis out already, but we don't think the application is stable enough yet. it has toons of bugs.
this is the solarias version, i know cadence has been working arround the clock to get the port to linux, but for what i see is not there yet.
i talked to one of the developers, the code is ready but it will not be released to cu
Linux Software :: 07-23-2002 01:46 :: MOS21 :: Replies: 3 :: Views: 3668
Plz Plz Help
I am lookig for SpectreRF of cadence...
Please Help me....
ASIC Design Methodologies and Tools (Digital) :: 07-03-2002 10:28 :: pjuice :: Replies: 0 :: Views: 1406
Ja too write skiil script.
1. in .cdsinit write load("~/name.il")
2. in .icdsinit write top function for exicated wen loade cadence
ASIC Design Methodologies and Tools (Digital) :: 04-03-2003 02:14 :: Lenin :: Replies: 7 :: Views: 2924
1. -> t
Microcontrollers :: 07-11-2002 02:39 :: jimjim2k :: Replies: 0 :: Views: 1987
1. -> t
Microcontrollers :: 07-11-2002 02:41 :: jimjim2k :: Replies: 3 :: Views: 1584
I am look for cadence ic 4.4.3 and ic 4.4.5
ASIC Design Methodologies and Tools (Digital) :: 07-31-2002 23:38 :: syncmaster :: Replies: 1 :: Views: 1590
Looking for 1 corrupt file from cadence IC446 CDs
I got cadence IC446, ISR 20020224 version, and
a file named FS.128 from the 2nd CD in image directory
is corrupt. If anyone has this CD, please let me know.
I just need this one 6MB size file.
ASIC Design Methodologies and Tools (Digital) :: 10-03-2002 17:08 :: iop3001 :: Replies: 3 :: Views: 1804
if you want to study cadence software ,please access this site "
This is the best tutorial of cadence that I have seen !!
ASIC Design Methodologies and Tools (Digital) :: 12-01-2002 21:26 :: cnz :: Replies: 0 :: Views: 2185
cadence Design Tools
1. -> t
Microcontrollers :: 01-02-2003 04:57 :: jimjim2k :: Replies: 0 :: Views: 1275
cadence CAD Tutorial
1. -> t
Microcontrollers :: 01-02-2003 04:58 :: jimjim2k :: Replies: 3 :: Views: 1854
Your post was OK, and Technical Info, or Tools Comparison is OK too in Elektroda. The follow-up post was indeed irrelevant to your Technical Info request.
It looks like Protel DXP is gaining ground, even though being perceived as a weak PCB tool. Still - the top leaders are:
Mentor Boardstation (WG2002),
cadence PSD (AKA Allegro),
PCB Routing Schematic Layout software and Simulation :: 01-11-2003 06:16 :: roli :: Replies: 2 :: Views: 2544
trying tu use cadence allegro, i allays start with pink color for all components.
Can i save the color assignement, find a confiuration file with a such color assignement ?
Are there skilled users of cadence allegro here ?
or you can make your own coloring schem
PCB Routing Schematic Layout software and Simulation :: 01-14-2003 11:08 :: CADPCB :: Replies: 6 :: Views: 2905
cadence Schematic Simulation w/Spectre
* -> t
Microcontrollers :: 01-18-2003 08:45 :: jimjim2k :: Replies: 2 :: Views: 1407
DOes anyone know if a windows version of cadence design kit exists.
Software Links :: 02-13-2003 20:58 :: nitr8 :: Replies: 2 :: Views: 1027
cadence Nanometer Design
Latest Technology Addresses Critical Issues Throughout Semiconductor-Foundry Design Chain
1. -> t
Microcontrollers :: 02-09-2003 07:36 :: jimjim2k :: Replies: 0 :: Views: 661
cadence to use IBM Linux power in EDA
IBM and cadence Design Systems have announced an agreement to jointly optimise and market electronic design solutions from cadence using IBM's advanced Linux-based technology.
1. Look at:
cadence expects shift to Intel-based Lin
Linux Software :: 02-09-2003 07:38 :: jimjim2k :: Replies: 0 :: Views: 1235