76 Threads found on edaboard.com: Cadence Cdf
How to create an instance using skill languahe in cadence, say NMOS.
I have seen the syntax for creating instance
dbCreateInst( d_cellView d_master t_name l_point t_orient
To be specific what should I enter for d_master.
Also how can we edit the parameters like width and length of nmos
Analog IC Design and Layout :: 11.06.2004 02:48 :: Hughes :: Replies: 5 :: Views: 6970
from the CIW window: choose: Tools >> cdf >> Edit
Brouse for you MIM, use Edit/Add paramters to modify it to what you aim to be.
Read cadence cdf user manual for more details.
hope this helps,
Software Problems, Hints and Reviews :: 02.12.2006 01:18 :: ahmad_abdulghany :: Replies: 2 :: Views: 1530
I am trying to draw an inverter chain using the cadence schematic composer. And at each node it will have 3 inverters parallel(fanout=3 for each inverter). I heard there is a parameter m. If we set the m=3, then we don't need to draw three inverters. How to do this in composer?
Also I draw the schematic in two hierarchy. I defined the inverter s
Analog IC Design and Layout :: 23.02.2005 20:05 :: triquent :: Replies: 11 :: Views: 3492
For more details of cdf you can refer 'cdfuser' ie the Component Description Format User Guide in the cadence Documentation.
Analog IC Design and Layout :: 03.03.2005 06:00 :: gunturikishore :: Replies: 5 :: Views: 6443
I'm looking for tutorials on PCell generation in cadence Virtuoso. Is there any documention or tutorial that could help?
Analog IC Design and Layout :: 01.02.2006 07:50 :: DoctorProf :: Replies: 4 :: Views: 6072
I used cadence IC5141 to do EXPORT -> CDL for some schematic diagram as below,(see attachment)
I always got a poor netlist as:
XI13 net043 net23 inv
XI4 net23 XPA XPB XPC nand3
But, what I need is as:
XI13 net043 net23 inv lp=0.35 ln=0.35 wp=1.6 wn=0.8
XI4 net23 XPA XPB XPC nand3
ASIC Design Methodologies and Tools (Digital) :: 04.02.2006 03:09 :: sean202 :: Replies: 2 :: Views: 1432
What I will say will probably used against me at th ecourt of law but anyway - TSMC does not create their PDKs. Those are done by cadence and there ARE disconnects. I did not see ANy PDK working 100% yet.
My personal and private opinion is that if they would provide perfect pDK and something would go wrong , companies would use it against them and
Analog IC Design and Layout :: 25.03.2006 22:22 :: Teddy :: Replies: 6 :: Views: 1393
suppose that i have created a symbol for a circuit that includes 2 NMOS's.....let call them NMOS_1 and NMOS_2.
now, i wish to use multiple instances of this symbol to build up a bigger circuit.....but i wish to be able to have different values for W of NMOS_1 & 2 for each of the instances.
i am told that this
Analog IC Design and Layout :: 20.04.2006 09:58 :: tsb_nph :: Replies: 4 :: Views: 6884
I've a netlist that describe a circuit.
In cadence, generally, we draw schematic and a corresponding symbol. We then connect the symbol with Signal source for simulation.
Instead of schematic, can I draw a symbol that point to this netlist and then connect the symbol with signal source for simulation? Can it be done and how?
Analog Circuit Design :: 30.06.2006 11:04 :: yolande_yj :: Replies: 5 :: Views: 1658
I don't remember. U can look for cadence documentation (for ex. verilogamsref).
Analog IC Design and Layout :: 04.08.2006 03:41 :: DenisMark :: Replies: 9 :: Views: 6098
This is not a cadence option, it is a design kit option. U can find the equation from the process documents.
Analog IC Design and Layout :: 07.08.2006 04:57 :: eng_Semi :: Replies: 4 :: Views: 972
when i export cdl netlist ,i have got the problem
the nmos and pmos i got the param of modelname ,l,w
but the res i can not got these param .
deos somebody can help me ???
Analog Circuit Design :: 08.11.2006 21:50 :: wjlzhx :: Replies: 2 :: Views: 1827
I don't mean it, but anyway, it's not a very repeatively needed thing, i can do it from CIW window directly, thanks,
But, if you have a pdf contains as many as possible of cadence Virtuoso Schematic, Layout, analog environment, etc. and any other keyboard bindkeys and short-cuts, so please attach it to your next reply.....
Analog IC Design and Layout :: 20.11.2006 12:52 :: ahmad_abdulghany :: Replies: 5 :: Views: 1040
Did anyone try to make the cdf parameters for a component using SKILL on cadence before?
I want to write it for an MIM capacitor..
How can i attach it to the symbol after creation? In other words, how to point to that SKILL file containing parameters?
Thanks in advance,
Analog IC Design and Layout :: 30.11.2006 09:32 :: ahmad_abdulghany :: Replies: 2 :: Views: 1436
I use hspiceD simulator for generating hspice netlist( IC5141 ).
My netlist has a big problem in subckt definition.
I want like below
.subckt inv_p a y inh_vdd inh_vss pw=default_value nw=default_value
Analog IC Design and Layout :: 27.03.2007 10:09 :: forestgim :: Replies: 1 :: Views: 1476
Maybe the V5 waveform type is not defined. it is a bug in old version cadence. You can copy the V5 from the analogLib to your own lib, then edit the cdf of V5, you can define the waveform type
Analog IC Design and Layout :: 17.06.2007 22:35 :: pfd001 :: Replies: 5 :: Views: 2911
any one can help to solve this error ( following lines taken from CDS log file) :
\o cdf: An error occurred when evaluating callback.
\o Callback: model->display => C035a_mosDisplay('model)
\o Message: *Error* eval: undefined function - C035a_mosDisplay
Analog IC Design and Layout :: 11.07.2007 23:26 :: mohazaga :: Replies: 5 :: Views: 1938
I am using IC5.0.33 in Fedora Core 4. The cadence runs fine except for the following things:
1. When I open a schematic and try to check the properties of transistor or
resistor or any other component then the parameters like the lengt, width,
multiplier etc. do not show up. All the cdf parameters are absent.
Electromagnetic Design and Simulation :: 10.08.2007 19:12 :: bibhudattas :: Replies: 0 :: Views: 690
The prolem is finding a way to export CDL netlist contains parameters defined by myself of specified model.
Take resistor for example. By deafult, a resistor in a CDL netlist have a form below:
R1 VDD VSS 1K RP
It means a resistor connect to VDD and VSS has a 1K ohms value and model name is RP.
Now I need 2 additional parameters
Software Problems, Hints and Reviews :: 03.09.2007 02:49 :: starrinesss :: Replies: 1 :: Views: 1576
there are many ways to extract netlist from schematic in the cadence.
I used one among many way. it was cdl extraction method. extraction process is following figure.
Question : in Initialize Environment, Simulator Name is "Other : cdl".
When I want to modify some device or model name, what I have to modify to change device parameter?
Analog Circuit Design :: 28.10.2007 20:53 :: 020170 :: Replies: 5 :: Views: 4900
I used to cdl extraction, I want to modify some paramneter and model name, Bu ti cannot.
In the net, I can find some way to modify auCdl. But This is not work for me.
In my case, I have only 4 view component in the one cell, cdl, lvs, symbol, verilog.
"cdl" is the key to extract cdl netlist. But I don't know how to modify it.
when I ope
Analog Circuit Design :: 12.11.2007 19:09 :: 020170 :: Replies: 2 :: Views: 1191
I am not sure is this the right place to ask.
What are these? Why they are done ? are they necessary?
The layout drawings has only two colors,how to fix them?
You should read about this in the cadence documentation...
cdf is the Component Description Form, the part of the database that is mostly used for Analog
Linux Software :: 10.06.2008 04:40 :: n1cm0c :: Replies: 7 :: Views: 4515
I'm having two issues with the cadence/spectre analog enviroment. Perhaps someone more experienced than me can help me solve them?
1) In the schematic: Next to my transistor are three lines of red text. They go as follows:
The first line is the device model name and the third line is the number of fingers.
Analog IC Design and Layout :: 28.01.2009 11:57 :: shlomo22 :: Replies: 3 :: Views: 2721
In fact, I´m dissapointed a little because I´ve got another PC with the same Linux, the same cadence IC51041, and the same design kit and a simulation works perfectly there. There is one difference only, the soft on those PC were installed by another guy :)
I know it is possible!!!!
Analog IC Design and Layout :: 12.03.2009 09:19 :: yxo :: Replies: 13 :: Views: 3614
Under the cadence schematic design environment, I get a device symbol from the PDK, then attach it to it's model file. In that case, the simulation result is strange and wrong.
If I get the symbol from the analoglib, the simulation result will be all right.
I don't know what happened here. Is it something wrong with the configurati
Analog IC Design and Layout :: 28.06.2009 02:15 :: ddrr :: Replies: 3 :: Views: 677
I want to test a model of an op amp in cadence written in Verilog-AMS. I have compiled the verilog-ams code successfully. I have also created the symbol. But I have found problem when I have tried to put the symbol in a schematic window and simulate a test bench circuit. I think there is a configuration : creating a config view etc..
Analog Circuit Design :: 16.09.2009 09:24 :: goldeboy :: Replies: 1 :: Views: 1863
Firstly, I use Spectre, mmsim-72, cadence 5.10.41.
I have an interesting problem. I want to measure the drain current of a nMOSFET; however I get different results based on what I actually look at. Here is what I mean:
1. If I simply click to the drain terminal of the NMOS and plot the transient current, I get one value.
Linux Software :: 22.01.2010 09:24 :: andich :: Replies: 2 :: Views: 806
I use 4 depending current sources in a subckt. The voltage should be depending on the current which flows through one of the others.
I decided to use ccvs sources. How can I configure such a source to work like I want. What is the port parameter? How can I set the dependency?
Analog IC Design and Layout :: 27.03.2010 08:15 :: chippendale :: Replies: 2 :: Views: 2149
I posted this question yesterday, but it looks like it got lost somewhere. So, here it is again...
I simulated my voltage comparator schematic without glitches, got the layout done, and got it to pass the DRC checks, successfully extracted (I think...) the layout. But, when I run LVS, it terminates, displaying on the screen : "..... L
Analog Circuit Design :: 09.05.2010 07:29 :: Terp :: Replies: 0 :: Views: 1470
Hi, recently I've been working with cadence SKILL and I have several questions.
First, From my understanding if i do something like
wi = "1u"
I am making a string. If I have a variable, let us say width1, which contains an integer/float number inside, how do I make the variable number a string.
Second, how do I truncate a variable (float
Analog IC Design and Layout :: 19.06.2010 23:08 :: wholegrain :: Replies: 7 :: Views: 2546
i need some helps!
i use IC5141 USR6 schematic editor and PDK symbols from TSMC.
For P/NMOS transistor, I want to remove the bulk terminal since almost all MOS transistors' bulk terminal is tied with source supply VDD/VSS. so the circuit look simply if all MOS bulk terminal is removed.
i want to create 2 new MOS symbols which have only 3 termina
Analog Circuit Design :: 03.08.2010 23:00 :: dongzz201 :: Replies: 2 :: Views: 1105
I encountered an interesting problem here.
u create a schematic, u can change the size of MOS as u wish,at this time the pdk is working properly;
while u step in analog envrioment, generate the netlist of schematic , if u want to change the size of mos (such as W,L,FINGER,MLTI),an error occured :
cdf:an error occurred when evaluating callb
Analog IC Design and Layout :: 12.10.2010 03:50 :: chooly :: Replies: 3 :: Views: 1650
While annotating the transistor for its operating point, i can display only 3 types of component display properties (eg, Id, Vgs, Vds or any other 3 types)... but if i want to display more than 3, say 4 or 5 such type of properties .... is there any way?
Analog IC Design and Layout :: 10.11.2010 11:28 :: mfhanif :: Replies: 9 :: Views: 1621
I created hierarchy in Virtuoso 6.1.x
I created the transistors from scratch , I mean my basic cell is just
a transistor with pins because I want to simulate my basic transistor with some more adjustments to leakage currents and some reliability issues ,
and than I built my architecture with this basic cells .
My problem is I want to ha
Analog IC Design and Layout :: 14.11.2010 12:51 :: yans123 :: Replies: 5 :: Views: 802
I have .cir file and I want to create part in cadence virtuoso with that model.
Is it possible?
Analog IC Design and Layout :: 20.12.2010 04:46 :: sarge :: Replies: 4 :: Views: 4026
in cadence i hav simulated the circuit and tried to plot node transient response,but it doesn't
showing the plot, a warning (no "VT" data for node "/netxxx" ) is displayed in the icfb window
can anyone help me how to eliminate the warning " no VT data for node xxx in cadence".
Analog IC Design and Layout :: 15.03.2011 02:33 :: surender.k :: Replies: 2 :: Views: 809
I established a voltage source model(named vsrc) based on the standard voltage source model(vsource) in cadence. I want to use it in my monte carlo analysis. But there in no model name in cdf of vsource, so my new model could not be found by .scs file. when the netlist is created, voltage sources in my circuit are always been created based on vsour
Analog Circuit Design :: 06.04.2011 06:39 :: jing.tutallinn :: Replies: 3 :: Views: 366
I would like to create a buffer chain by having the # of fan-outs as a parameter. This is probably a cdf thing.
i know I can instantiate multiples of a block in parallel with something like I1<4:0> for a fanout of 4, but I cannot parameterize this fanout with something like I1<0>, for example. Any help would be great. Thanks in adva0>
Analog IC Design and Layout :: 09.04.2011 12:15 :: patricky :: Replies: 1 :: Views: 368
I'm using cadence IC6.1.4. I'm trying to annotate the operating point information on the schematic for the transistors and I can't. Transistors are defined as primitives, not subcircuits. Similar to the nmos and pmos from analogLib (for which I can annotate the op). I can annotate the node voltages but not the id, vgs, vth, gm etc. However,
Software Problems, Hints and Reviews :: 03.05.2011 13:43 :: sutapanaki :: Replies: 0 :: Views: 1286
Do you know if i can change the temperature coefficient of a resistor in my simulation and how? I am using cadence.
Thank you very much
Analog IC Design and Layout :: 23.05.2011 09:05 :: geozog86 :: Replies: 3 :: Views: 735
i want to divide the o/p freq of Quad-VCO i.e. 4.8 GHz into 2.4 GHz. for this purpose i need a freq divider ckt.
i saw the freq divider from RF library in cadence. it is containing 4 pins (pin, pout,nin, nout).
how to apply stimulus to this pins & check the o/p
what does nin & nout stands for????????????
RF, Microwave, Antennas and Optics :: 15.11.2011 01:19 :: ddis :: Replies: 7 :: Views: 964
I think you are trying to pass a swept variable in ADE L with name "w" that is the naming of transistor's width at the cdf so they conflict and that's why you get this error.Avoid using names for your variables that already are part of the cdf.
HI jimito13, thank you for your reply but I didn't have any variable w.
Analog IC Design and Layout :: 20.12.2011 16:50 :: gift4jo :: Replies: 2 :: Views: 870
Is there any DRC rule which measures width to check if it is even number?
please let me know, thank you
Analog IC Design and Layout :: 16.12.2011 14:23 :: deedeepr :: Replies: 1 :: Views: 1888
Ive got 3 questions regarding layout of current mirror and differential amplifier:-
Q-1. Ive got a current mirror with the pairs having large widths such that their finger numbers are 100 and 200 ( so as to keep the finger width <10 um )... now for this if i go for common centroid it will take lots of time for routing... so my questio
Analog IC Design and Layout :: 31.12.2011 00:28 :: bestvlsi :: Replies: 2 :: Views: 701
I'm wonder does any one knows that if its possible to get the cdf (cumulative Density Function) diagram in cadence spectre?
or it should be done through Matlab
Appreciate for help and hints
Analog Circuit Design :: 17.02.2012 09:33 :: farid82xxx :: Replies: 0 :: Views: 291
I have a PDK in which I have all standard cells (inverters, nands,etc.) defned in one common .spi file.
I have standardlib symbols and used them within my analogic schematic for simulation.
I defined on the toplevel global vdd!, gnd!, and also used cdf (VDD netSet vdd!, and VSS netSet gnd!) to be sure that the instantiated inverter ha
Analog IC Design and Layout :: 25.03.2012 07:54 :: tstoll :: Replies: 1 :: Views: 633
From TSMC manual, I find this "The designers will need to turn off (mismatchflag=0) or turn on (mismatchflag=1) in the macro model for nominal or Monte-Carlo analysis". Any idea, how can I turn it on?
Analog Circuit Design :: 23.06.2012 23:46 :: guow06 :: Replies: 4 :: Views: 716
may i know how to calculate Ion/Ioff for FINFET in cadence and theoretically. If any one knows please reply to this post
thanks in advance
Analog IC Design and Layout :: 20.11.2013 11:24 :: venkateshjuturu :: Replies: 4 :: Views: 555
what's the difference between the job of cdf parameter, which can be set manually in cadence build-in dialog window when try to "i" an part on the schematics, and that of simulation model file, like .scs, which is loaded in the procedure when try to do spectre simulation?
Maybe some parameters are overloaded or dependence between parameters of t
Software Problems, Hints and Reviews :: 07.02.2013 06:48 :: iamyuchenjie :: Replies: 0 :: Views: 266
in my memory,Analog Artist contain many source include FM Am sin ,pulse and so on,you can directely use it for simulating,in fact if you can devolp the .cdf file,you can input anything for entring for any tools can be integreting in cadence.
read the help of cadence carefully,you can find the results
ASIC Design Methodologies and Tools (Digital) :: 21.02.2002 21:48 :: nmtr :: Replies: 11 :: Views: 4207