101 Threads found on edaboard.com: Cadence Dft
u can use digital proccessing method
In cadence? How?
Analog IC Design and Layout :: 13.01.2005 22:55 :: djalli :: Replies: 11 :: Views: 10221
Maybe refer to the following survey:
Subject: Synopsys dft Compiler/TetraMAX vs. Mentor dft Advisor/FastScan
Synopsys dft Compiler: ########################### 68%
Mentor dft Advisor: ############# 32%
ASIC Design Methodologies and Tools (Digital) :: 27.12.2005 03:24 :: joe2moon :: Replies: 16 :: Views: 1815
For sigma delta modulator, the output is a bit stream containing the quantization noise and the signals ( DC or sinewave ). PSD Estimation is the right way to reveal the information.
Assume your sample frequency is 10M, your run 1.8ms, then you will get 18,000 points, do PSD on last 16,384 points (I forgot if you can do it in cadence Calculator,
Analog IC Design and Layout :: 22.03.2005 22:00 :: field_catcher :: Replies: 1 :: Views: 2329
How to do FFT in cadence with Spectre as simulation tool?
which window should I use in the function "dft"?
I found if I use "rectangle", the spectrum looks best, is it ok?
I used "Kiaser" in my Matlab simulation, but if I use "Kiaser" in cadence
the output spectrum looks bad.....
Is there any thing wrong?
If I wanna use the (...)
Analog Circuit Design :: 03.05.2005 16:54 :: yiyin :: Replies: 3 :: Views: 2828
I've been using cadence for some time. From the tools available in calculator, they offer dft but no FFT.
Analog Circuit Design :: 18.05.2005 03:39 :: yeechyan :: Replies: 5 :: Views: 6037
Several of the high end PCB tools is about to launch support for what you are asking. Mentor Graphics (Expedition) will do this. cadence (Allegro) too. Thus you can enter your DFM requirements directly into the tool's constraint set-up.
PCB Routing Schematic Layout software and Simulation :: 17.09.2005 15:23 :: Uky :: Replies: 5 :: Views: 1376
I am simulating in Spectre the ideal 8bit DAC from the AhdlLib. What seems strange is that from the dft analysis the SFDR is about 60db. It is to small for the ideal case. Have you ever come up with this case?
Analog IC Design and Layout :: 11.10.2005 07:05 :: moisiad :: Replies: 1 :: Views: 1511
I'm designing an op amp and want to calculate the HD3. The input signal is 1KHz. I found that there's a "dft" function in the calculator. But how to set the variables in it? ("from", "to" means what?) And how to get the HD3 from the dft result?
btw: how long should I run the transient simulation to calculate the HD3?
Thank you for your
Analog Circuit Design :: 07.12.2005 01:35 :: princerock :: Replies: 2 :: Views: 2074
Can someone tell me in detail how to test the adc? I want to input sin wave and the run FFT/dft on it, how to implement this in cadence or matlab?
I will really appreciate your help,
Analog IC Design and Layout :: 14.02.2006 23:00 :: ASICK :: Replies: 3 :: Views: 1220
I always use Synopsys dft compiler as dft insertion tools, but now I want to do dft insertion by cadence RTL Compiler( Just learn), can someone give me help?thanks.
In addition, I also learn ENCOUNTER now, what I have is userguide only,how can I do.
ASIC Design Methodologies and Tools (Digital) :: 07.03.2006 05:43 :: deodar_li :: Replies: 0 :: Views: 805
please just check the cadence spectre RF manual, in which there are very detailed description and examples. from there you can find much better explaination and step-by-step proceduures than all the answers here.
Analog Circuit Design :: 21.03.2006 14:22 :: pengboy :: Replies: 12 :: Views: 7731
cadence STA tool:
CTE (common timing engine): static timing analysis
+ SignalStorm: delay calcularor (using ECSM library)
+ Celtic: crosstalk analysis
= IR-aware timing/crosstalk analysis tool
cadence dft tool:
- 1) dft (...)
ASIC Design Methodologies and Tools (Digital) :: 08.04.2006 03:56 :: joe2moon :: Replies: 13 :: Views: 6080
I have a ADC , and want to simulate it SNR & SNDR
but found there is no method can directly simulate it , and i use newest cadence spctre the calculator is no contain snr function.
I only have result of FFT , i avoid translate data to matlab because too larger,
so is anybody has method to calculate SNR & SDNR in cadence spectre ?
Analog Circuit Design :: 01.06.2006 22:44 :: lije :: Replies: 6 :: Views: 2764
Does cadence or Synopsys dft products support the IEEE 1149.6 standard?
ASIC Design Methodologies and Tools (Digital) :: 01.11.2006 16:08 :: maksya :: Replies: 4 :: Views: 1185
synopsys has dft max/dft compiler. mentor graphics has fastscan / dft advisor. i'm sure u can find such similar products in cadence also.
if i want to have some tutorials on them, i usually try . almost all eda vendors have some demos there. i'm not a dft guy. so, haven't looked for anything related to (...)
ASIC Design Methodologies and Tools (Digital) :: 19.11.2006 12:19 :: sree205 :: Replies: 15 :: Views: 1908
I want to simulate the SFDR of my design by "dft" in caculator. But I got a very small SFDR, no more than 20dB. I think this is not correct, not because of my design, but my simulation. I check my simulation, and I find a strange thing that when I caculate the input signal (by ''dft'' in caculator), which is set as a ideal sin (...)
Analog Circuit Design :: 06.12.2006 07:48 :: stephenlucky :: Replies: 4 :: Views: 1232
anantha_09: I think Mentor would beg to differ on your assertion that TetraMAX is the most widely used tool. TetraMAX is one of many dft tools out there.
Here's a more complete list:
Mentor: FastScan (ATPG), TestKompress (compression) , MBIST Architect (memory BIST), BSD Architect (boundary scan/JTAG), dft Architect (scan insertion), etc.
ASIC Design Methodologies and Tools (Digital) :: 24.05.2007 13:33 :: dft_guy :: Replies: 3 :: Views: 1279
when using cadence sim. analog env. , the output signal of my ckt (Transit sim.) is voltage pulse , so how we find out its power spectral density? which function we use in cadence calculator ? how?
Analog IC Design and Layout :: 27.08.2007 05:36 :: mohazaga :: Replies: 7 :: Views: 1866
any body has an idea how to get FFT using cadence spectre calaculator?
i have a output voltage signal/time and I want to do FFT over it.
Analog IC Design and Layout :: 29.09.2007 02:39 :: mohazaga :: Replies: 9 :: Views: 6143
Might be useful for someone.
Practically no one uses cadence to do dft-insertion. Synopsys dft-compiler or that third-party one (FastScan?) have the most marketshare.
I used cadence Ambit/PKS test-insertion in the past -- it's not even close to Synopsys dft-compiler in terms of usability and (...)
ASIC Design Methodologies and Tools (Digital) :: 31.01.2008 11:49 :: boardlanguage :: Replies: 3 :: Views: 1132
I AM PRASADH, I AM DOING MY PROJECT ON FLASH ADC IN cadence..
HOW CAN I DO THE FFT ANALYSIS IN cadence SPECTRE FOR MY CIRCUIT..
ACTUALLY I HAVE TO MEASUER SFDR,SNDR FOR MY CIRCUIT .
CAN ANYONE HELP ME PLEAE....
Analog Circuit Design :: 07.05.2008 01:20 :: prasadel06 :: Replies: 1 :: Views: 1933
you can use calculator's dft in cadence, or use SpiceExplorer, the inner function of FFT is very convient.
Analog IC Design and Layout :: 07.05.2008 06:25 :: caosl :: Replies: 5 :: Views: 1641
Raju you can find demos for the same at
You may register to get your materials.
ASIC Design Methodologies and Tools (Digital) :: 31.05.2008 16:02 :: asicmktg :: Replies: 9 :: Views: 2275
Does anyone know how to simulate THD in circuit design environment of cadence ic6.1 version?
how to right the thd() expression with calculator?
Analog Circuit Design :: 10.06.2008 15:12 :: jingxuelu :: Replies: 17 :: Views: 6484
I'm still confused about the THD simulation result, I pasted the simulation figure, the left one is sinewave, and right one is the dft simulation (only sampled the last period as LvW suggested) with rectangula window,
Analog Circuit Design :: 18.06.2008 15:29 :: jingxuelu :: Replies: 1 :: Views: 1299
when i use the dft function in cadence to calculate the sfdr i get frequency components outside the bandwidth that we working on is that normal if not can any one explane to me the right way for this simulation
Analog Circuit Design :: 26.06.2008 12:12 :: mahgoub :: Replies: 0 :: Views: 798
I want simulate my first first order delta sigma ADC, attached schematic. I can simulate it and I see behind the LP again my input signal.
My problem is I cant see the noise shift to higher frequency. I simulate transient and adjust transient noise (noisefmin noisefmax and noisescale) measure it at the input (dft) and compare with the
Analog Circuit Design :: 02.09.2008 05:54 :: olzanin :: Replies: 2 :: Views: 2321
hey u doing work on which tool
actually i require help for cadence Encounter Test architect tool
can u give the required material plzzzzzzzzzzzzz
ASIC Design Methodologies and Tools (Digital) :: 15.12.2008 03:37 :: madhavisai :: Replies: 8 :: Views: 1865
Can you guys share any dft documentation using any vendor tool such as cadence, Synopsys or Mentor Graphic?
ASIC Design Methodologies and Tools (Digital) :: 22.10.2008 04:46 :: cafukarfoo :: Replies: 0 :: Views: 551
Sometimes tha defined output parameters are not saved in ADE state files, or they are not loaded. defined variables and simulation and all other settings are loaded, but not the ouptut parameters. Does anybody have similar experience and how to avoid it or recover the output parameters?
Analog IC Design and Layout :: 19.01.2009 18:15 :: fathi :: Replies: 4 :: Views: 786
I am doing a Δ-Σ Fractional-N Frequency Synthesizer, and I want to know how to analyse the output spectrum in cadence spectre simulation, please?
I do the dft analyse to the output signal, and change Y axis of the dft output result to dB10 format, but I find the spectrum analyse use the unit of dBc, how can I get this unit (...)
Analog IC Design and Layout :: 05.03.2009 01:56 :: gaom9 :: Replies: 0 :: Views: 825
Hi, my name is Breno and I'm working with RTL Compiler.
The problem is that the new version of cadence don't support the commands insert_scan and insert_boundary_scan.
To insert the boundary scan, it can still be done using the command build_top_shell of ET. But to insert the scan chains I have to use RC.
I'm trying to do this, reading the docu
ASIC Design Methodologies and Tools (Digital) :: 11.05.2009 09:04 :: brenox :: Replies: 1 :: Views: 1105
Make sure your message frequency or the frequencies you are interested in knowing about lie in the fft bin. The greater the number of points in the fft the greater is the resolution in frequency domain.
I would suggest you to google these 2 keywords;
a) spectral leakage.
if you have problems with the calculator user-interface
Analog IC Design and Layout :: 16.07.2009 11:57 :: amriths04 :: Replies: 3 :: Views: 2096
I am trying to measure my 10 bits ADC ENOB.
My input signal is 7.5KHz sine wave, sampling frequency is around 552KHz (required by application). And output is the sampled data through dac (written in veriloga, no filter).
First, I selected my input signal and do the dft as,
From 30u to 1m (did transient simulation from 0 to 1ms
Analog IC Design and Layout :: 09.08.2009 01:19 :: coffeelox :: Replies: 9 :: Views: 4915
I am working on ATPG using cadence encounter test, getting low coverage for transition faults( at speed) . the tool reported the warnings but these warnings are not affecting the low coverage.
Can anyone help me how to dig further to find which part of the logic is not tested? how to improve the coverage
ASIC Design Methodologies and Tools (Digital) :: 01.09.2009 11:28 :: jaanki :: Replies: 2 :: Views: 1301
How can i get the spectrum of a singal in the time domain ploted in cadence Spectre? You reach it in ADS by inserting a function such as fs(name,,,,,,,indep(m1),indep(m2)) in the data window after a transient simulation. Does there exist any counterpart function can do the same job in cadence Spectre? Thank you!
RF, Microwave, Antennas and Optics :: 29.11.2009 22:18 :: wyttl :: Replies: 2 :: Views: 1824
my 2 cents,
At first you need to know the complete asic design flow,
There are pointed tools available for performing specific task if you need accuracy , you can get the list of the tools and their datasheets, and what functionality or what portion of the asic design it will be covering can be found at the EDA vendor portal for examp
ASIC Design Methodologies and Tools (Digital) :: 22.12.2009 09:03 :: vlsichipdesigner :: Replies: 4 :: Views: 3559
Newbie here. Trying to learn about phase noise in cmos VCOs. I have a assignment I was given, and have been scouring the internet and textbooks trying to get past one part.
I have a current starved VCO I designed in cadence. Part of one of the tasks is the following:
"There is difficulty in using CAD tools to assess phase noise of non
Analog IC Design and Layout :: 18.03.2010 23:14 :: fuz :: Replies: 0 :: Views: 935
Could someone please help me to plot the frequency spectrum in cadence. Use dft analysis. See this thread , or search for dft!
Analog IC Design and Layout :: 01.05.2010 09:06 :: erikl :: Replies: 4 :: Views: 1973
my opinion, Mentor dft tools are efficient than cadence or synopsis.
for ATPG, the compression logic by Mentor's TestKompress is really good, and the pattern count is relatively less when compared to synopsis Tetramax (i did a case study on this) not sure about cadence. Apart from the cost, I would say Mentor is better than other tools. (...)
ASIC Design Methodologies and Tools (Digital) :: 09.06.2010 18:25 :: somu.atluri :: Replies: 2 :: Views: 2160
Hi,I want to simulate dft results in a sampling cuicuit. The sampling clock is 4ns，so I set fsig/fclk=127/512. In ADE tran option,I set strobeperiod is 2.048u/512.Will I need to set maxstep,and how much it should be?
Analog IC Design and Layout :: 26.09.2010 04:43 :: xy85061182 :: Replies: 0 :: Views: 717
I am trying to use dft to get the THD of my design.
But somehow the output waveform give only a input frequency component and some of its harmonics with the same magnitude. ( I used Hspice to verify that the dft result should not be like that.)
can anyone tell me how to fix it ?
Analog Circuit Design :: 19.11.2010 05:19 :: whlinfei :: Replies: 1 :: Views: 900
STIL as a dft drc file should be interchangable across all three test tools; Synopsy-Tetramax, Mentor-FastScan & cadence Encounter-Test . . .
This is pretty well controlled by the IEEE standard of STIL. Previously, in 2006 when STIL was evolving, some interoperability issues were seen. Pretty robust now!
ASIC Design Methodologies and Tools (Digital) :: 31.12.2010 11:39 :: Adam.Yakuvitz :: Replies: 4 :: Views: 611
Can anyone give me some idea how I can calculate SFDR from the dft plot obtained by using cadence ADE calculator. I want to know after getting the dft plot, what function in the calculator do i need to choose to obtain SFDR?
Analog IC Design and Layout :: 10.02.2011 15:25 :: abhisek.dey007 :: Replies: 7 :: Views: 1613
Suppose I am good at Synopsys Design compiler but do not know cadence RC Compiler at all. How long will it take to adapt to cadence RC Compiler? Will it be difficult to adopt to RC Compiler?
ASIC Design Methodologies and Tools (Digital) :: 17.04.2011 07:06 :: ASIC_intl :: Replies: 8 :: Views: 1707
Basically, you can check clocks & resets controlability using tools like cadence's HAL.
Also there are:
- combinational loops
- latches presence (if you are going to use multiplexed flip-flop scan style)
- resetless flip-flops
ASIC Design Methodologies and Tools (Digital) :: 26.07.2011 05:41 :: kornukhin :: Replies: 3 :: Views: 512
How to choose two tones for IP3 simulation (PSP+PAC) in cadence Virtuoso for Class E power amplifier operating at 433MHz?
Shall I set 10MHz as fundamental frequency and choose 420MHz and 450MHz as two tones? Thanks.
RF, Microwave, Antennas and Optics :: 26.07.2011 16:58 :: sharethewell :: Replies: 4 :: Views: 978
By macro model I include analog block (custom), mémoires, pads...
in our internal methodology, we must run the stuck patterns on the timing netlist.
A bits controller could be generate by the dft tool from cadence, Mentor, Synopsys or other one EDA vendor.
the Bist could be made by software or hardware is really dependent of your goal, area, power,
ASIC Design Methodologies and Tools (Digital) :: 01.03.2012 07:21 :: rca :: Replies: 14 :: Views: 701
Can any one help me how to define test_mode ,shift_enable,scan_chain in cadence rtl compiler ..................there are so may options are their for every command, which option i want to use i am not getting so plz can u help
ASIC Design Methodologies and Tools (Digital) :: 20.04.2012 02:06 :: manju540 :: Replies: 2 :: Views: 845
The compression algo is tool dependant, and mainly your choice is dependant of the tools policy of your company, Synopsys/cadence/Mentor/others?
As indicate by maulin sheth, the compression capability is related to your design, and the goal is reduce the memory usage with the same coverage target which also depend of your ATE capacity and coverage
ASIC Design Methodologies and Tools (Digital) :: 22.05.2013 12:40 :: rca :: Replies: 2 :: Views: 238