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## How to calculate THD and HD2 and HD3 of an OTA in cadence

Hello Can any one help me in calculating THD, HD2 and HD3 in cadence. I am designing an OTA. I dont know what sampling frequency to use? In some forum I have read I have to calculate dft aswell for THD can any one help? Thanx

Hi guys, I am not familiar with dft of calculator in cadence spectre. The problem is in frequency domain i observe very low resolution and steps are 200Mhz ! how can i increase resolution ??? 132731 I have a 2.5 Ghz signal and i cannot observe it ! and neither other tones !!!

## what is 'verilog libraries' for ATPG and simulation while working with Cadence Genus

Hi all, I am working on a dft . its an academic project where iam using cadence tools - genus synthesis solution (formerly RTL compiler) for dft and Encounter test(ET) for ATPG. now the question is, after performing dft synthesis, i was supposed to write ET scripts which were used by ET for generating testpatterns (...)

## Dyanmic Range from DFT in Cadence

I have done dft in cadence for my low pass filter. 1) Does the difference between first and third harmonic gives a rough estimate of the dynamic range of the filter? 2) Should the dynamic range change with change in input amplitude? (I think yes and in y case it is changing) 3) I have also done thd, but thd is not changing while dft plot (...)

## thd of low pass filter for ultra low frequency

I have designed a low pass biquad for cutoff 14Hz. I have done its dft and thd. I got thd 125.814. What does this value mean. In the help guide of cadence calculator, it say the formula returns voltage percentage. Please help me to understand this. With dft I got the follpwing graph 124160 When I use the log scale I

## Cadence RTL compiler DFT synthesis problem

Hello! I tried to synthesize my dft boundary scan design in cadence RTL compiler. Before synthesis i passed all dft rules checks and seemingly everything was fine, but when I started synthesize -to_mapped I got the following errors: Operation Area Neg Slk Worst Path (...)

## [DFT] Power reduction in chain test

Hello All, Can any one brief me about power reduction techniques we can do for chain test pattern? And what are the switches that takes care power reduction in cadence Encounter True time ATPG. Thanks & Regards, Maulin

## Power calculation for rectangular waveform in Cadence

Hi to all, I'm trying to built simple power amplifier with cmos output. I need to calculate output power in tran analysis, usually I do it with dft function and rms value for signal. For example for sinus we know: P=\frac{V^2 }{2R } Also, from wiki crest factor for rectangular

That is just your sampling window. So you may be simulating your ADC in a time interval but dft is going to calculate ft for the time interval specified by from-to parameters. Please refer to cadence documentation, most of the special functions are really well documented. Also to give you a straight answer, let's say that the number of samples you

## Can people provide information on what is meant by Compression efficiency in DFT?

The compression algo is tool dependant, and mainly your choice is dependant of the tools policy of your company, Synopsys/cadence/Mentor/others? As indicate by maulin sheth, the compression capability is related to your design, and the goal is reduce the memory usage with the same coverage target which also depend of your ATE capacity and coverage

## DFT by using Cadence RTL COMPILER

use define_dft followed by the signals type u wanna define. For more info on the switches search the rc command reference from cadence site.

## How to plot power in dBm using Calculator of Spectre

As you might know already, in cadence Spectre, we can plot the spectrum of a signal (say, output of an amplifier) using "dft" function of the Calculator.Don't mix up Simulation with Post Processing. They are completely different phase. It is an issue of cadence Post Processing Environmen

## question about the SC circuits

I need to implement a Nth parallel bandpass circuit with complex FIR and IIR; So, first, I want just to try a simple sample SC sample cirucuits in the test.jpg with input frequency 100 and sample frequency 1k,however, after i use the dft in the cadence and found that the output frequency is not the fout = fin +k*fsample, which should be 900,1100

## Bootstrapped switch Sample and Hold circuit - with dummy and without dummy

Dear all, I am designing a low-to-medium S/H circuit for an ADC. The sampling switch is a bootstrapped switch to linearize the on-resistance. I first designed a bootstrapped switch, and I simulated the waveforms and obtained dft and THD in cadence with the calculator. After that, I also designed a dummy switch to cancel the charge-injectio

## Why are the lint check done ?

Lint tools checks RTL code, helps to make the HDL design reusable, portable, synthesizable, and testable. Checking properties: naming conventions file format coding style synthesizability FSM structural dft clockdomain scanchain Tool example: cadence hal (included into ius) Synopsys DC also perform linting checks, report may get w

## DFT checks at RTL level

Basically, you can check clocks & resets controlability using tools like cadence's HAL. Also there are: - combinational loops - latches presence (if you are going to use multiplexed flip-flop scan style) - resetless flip-flops

## integration of mentor and synopsis dft tools

STIL as a dft drc file should be interchangable across all three test tools; Synopsy-Tetramax, Mentor-FastScan & cadence Encounter-Test . . . This is pretty well controlled by the IEEE standard of STIL. Previously, in 2006 when STIL was evolving, some interoperability issues were seen. Pretty robust now! -- adam

Hi all, I am trying to use dft to get the THD of my design. But somehow the output waveform give only a input frequency component and some of its harmonics with the same magnitude. ( I used Hspice to verify that the dft result should not be like that.) can anyone tell me how to fix it ? Thanks. Best Regards, whlinfei

Hi,I want to simulate dft results in a sampling cuicuit. The sampling clock is 4ns，so I set fsig/fclk=127/512. In ADE tran option,I set strobeperiod is 2.048u/512.Will I need to set maxstep,and how much it should be?

## can any one help me to plot Harmonic Distortion vs frequency

I m working in line driver project and i want to plot output HD2 and HD3 vs frequency plot in cadence. Thanks in Advance

## Comparison between Mentor DFT and Cadence Encounter Test

Hi All, Can someone tell me the difference between Mentor dft tool and cadence Encounter Test tool from Test generation / MBIST pattern generation and diagnosis of vectors point of view? It will be very helpful. we are in the middle of deciding between the two to go with which. Thanks

## Calculating phase noise from dft.

Hello all, Newbie here. Trying to learn about phase noise in cmos VCOs. I have a assignment I was given, and have been scouring the internet and textbooks trying to get past one part. I have a current starved VCO I designed in cadence. Part of one of the tasks is the following: "There is difficulty in using CAD tools to assess phase noise of non

## How to get the spectrum of a singal in cadence spectre?

How can i get the spectrum of a singal in the time domain ploted in cadence Spectre? You reach it in ADS by inserting a function such as fs(name,,,,,,,indep(m1),indep(m2)) in the data window after a transient simulation. Does there exist any counterpart function can do the same job in cadence Spectre? Thank you!

## DFT- how to improve the coverage?

I am working on ATPG using cadence encounter test, getting low coverage for transition faults( at speed) . the tool reported the warnings but these warnings are not affecting the low coverage. Can anyone help me how to dig further to find which part of the logic is not tested? how to improve the coverage

## problem while using cadence calculator DFT

Hi there, I am trying to measure my 10 bits ADC ENOB. My input signal is 7.5KHz sine wave, sampling frequency is around 552KHz (required by application). And output is the sampled data through dac (written in veriloga, no filter). First, I selected my input signal and do the dft as, From 30u to 1m (did transient simulation from 0 to 1ms

## How to get the dBc unit in Cadence spectrum analyse, please?

Hi, I am doing a Δ-Σ Fractional-N Frequency Synthesizer, and I want to know how to analyse the output spectrum in cadence spectre simulation, please? I do the dft analyse to the output signal, and change Y axis of the dft output result to dB10 format, but I find the spectrum analyse use the unit of dBc, how can I get this unit (...)

## ET(encounter test architect) tool help

hi everybody I am final year M.tech student ...and doing project in dft tool like ET from cadence we have license for this tool but i am new to it Can anybody help me how to work with this tool Thanks in advance

hey u doing work on which tool actually i require help for cadence Encounter Test architect tool can u give the required material plzzzzzzzzzzzzz

## DFT documentation using vendor tool

Hi Sir/Madam, Can you guys share any dft documentation using any vendor tool such as cadence, Synopsys or Mentor Graphic? Thanks.

Does anyone know how to simulate THD in circuit design environment of cadence ic6.1 version? how to right the thd() expression with calculator?

Hello, I want simulate my first first order delta sigma ADC, attached schematic. I can simulate it and I see behind the LP again my input signal. My problem is I cant see the noise shift to higher frequency. I simulate transient and adjust transient noise (noisefmin noisefmax and noisescale) measure it at the input (dft) and compare with the

## what does hookup polarity mean

Hi When defining dft signals in Scan insertion using RC we use an option called hook up polarity. what does that mean. I am not clear from the explanation given in the cadence manual. _________________ Thanks Prasad

## How to correctly calculate the sfdr in Cadence?

when i use the dft function in cadence to calculate the sfdr i get frequency components outside the bandwidth that we working on is that normal if not can any one explane to me the right way for this simulation

I'm still confused about the THD simulation result, I pasted the simulation figure, the left one is sinewave, and right one is the dft simulation (only sampled the last period as LvW suggested) with rectangula window, from t

## How to simulate the SFDR of an ideal 12-bit DAC?

Hello, I have a question about the use of dft in cadence. My 12-bit DAC has the sampling frequency 1.5Ghz. I use an ideal 12bit ADC to generate the input signal of DAC. My target is to find the SFDR of 2 frequencies(any) between 0-750MHz. So the questions are 1. how should I choose this input frequency? An arbitrary frequency or in my

you can use calculator's dft in cadence, or use SpiceExplorer, the inner function of FFT is very convient.

## FFT ANALYSIS IN CADENCE SPECTRE

HI... I AM PRASADH, I AM DOING MY PROJECT ON FLASH ADC IN cadence.. HOW CAN I DO THE FFT ANALYSIS IN cadence SPECTRE FOR MY CIRCUIT.. ACTUALLY I HAVE TO MEASUER SFDR,SNDR FOR MY CIRCUIT . CAN ANYONE HELP ME PLEAE.... THANK YOU

## Does the EDA vendor's tool support the Latch-based design?

Why cant you try RTL COMPILER from cadence. It can support all features of LSSD.. and latch based design.

Might be useful for someone. Practically no one uses cadence to do dft-insertion. Synopsys dft-compiler or that third-party one (FastScan?) have the most marketshare. I used cadence Ambit/PKS test-insertion in the past -- it's not even close to Synopsys dft-compiler in terms of usability and (...)

## how to simulate I/Q phase mismatch in divider?

Yes, indeed the zero crossing is missing some accuracy. I think spectre could be forced to set a time step exact at the zero crossing of I and Q signal. But there is another method. Take the FFT or in the case of cadence calculator dft of the I and the Q signal. The calculate the difference of the argument of the complex number result of the fun

## How to get FFT using Cadence Spectre calculator?

Hi any body has an idea how to get FFT using cadence spectre calaculator? i have a output voltage signal/time and I want to do FFT over it. thanks

## Where are the synthesis results stored in various tools?

Dear Friends, Synthesis using DC STA-using prime time dft- Mentor graphics CFT Advisor PNR- Nano route DRC and LVS cadence Assura,Virtosuo its nothing by step step process for this under what extension r these files stored.

## Tools used for Design for testability

Each vendor has their on set of tools. Please refer to the websites of the following vendors Mentor Graphics Synopsys cadence Magma

## Freelance ARM / XScale Designers available.

Orlin Technology has the expertise to deliver your ARM or X-Scale embedded design. We have many years experience, especially with Intel IXPxxx and Intel/Marvell PXAxxx products. Also NXP, ST and Atmel. PCB design to 16-layers. Impedance controlled. DFM, dft Mentor and cadence toolsets. Prototype and production builds. We're looking for c

## ARM and X-Scale based hardware design specialists.

Orlin Technology has the expertise to deliver your ARM or X-Scale embedded design. We have many years experience, especially with Intel IXPxxx and Intel/Marvell PXAxxx products. Also NXP, ST and Atmel. PCB design to 16-layers. Impedance controlled. DFM, dft Mentor and cadence toolsets. Prototype and production builds. We're looking for

## Weird THD results of a SH circuit

Dear Friends I designed a SH circuit as first stage for my pipeline ADC. I use cadence Analog Design environment and spectre for simulations. I performed a dft analysis on data obtained by transient analysis (coherant sampling, strobeperiod option used). The plot looks fine. I also included the "fourier" component from the "analogLib" to g

## How to simulate SNR & SNDR in cadence ?

Hi~~all I have a ADC , and want to simulate it SNR & SNDR but found there is no method can directly simulate it , and i use newest cadence spctre the calculator is no contain snr function. I only have result of FFT , i avoid translate data to matlab because too larger, so is anybody has method to calculate SNR & SDNR in cadence spectre ? th