1000 Threads found on edaboard.com: Cadence Layout Hfss
Export the layout from cadence to hfss or from hfss to cadence.
Analog IC Design and Layout :: 11-05-2008 18:10 :: elite631 :: Replies: 0 :: Views: 1034
Is there anybody familiar with simulation of a layout extracted from cadence in hfss. Is there any voltage pulse generator source in hfss that we can use it with lumped port?
Any comment is appreciated,
RF, Microwave, Antennas and Optics :: 02-21-2009 16:26 :: hn1 :: Replies: 0 :: Views: 1117
If you have the tool cadence IC446 or cadence IC500, or cadence IC610. Look on the document section you will find the tutorial
Analog IC Design and Layout :: 12-20-2006 09:10 :: gerryhsu :: Replies: 7 :: Views: 1324
someone can tell me how to print cadence layout to pdf file .
I want to print some layers to pdf and print in papers!!!!
Software Problems, Hints and Reviews :: 05-29-2008 02:44 :: zhaozenghui :: Replies: 2 :: Views: 1384
one good way out is export GDS file from magic and import it in to cadence layout.
keep an eye on layer table.
draw the schematic again in cadence, do LVS and verify.
ASIC Design Methodologies and Tools (Digital) :: 03-23-2009 04:56 :: hock :: Replies: 1 :: Views: 689
I'd like to stream out in cadence layout selected nets containing all the attached polygons or, at least, the metal layers composing such nets. I know how to stream out selected layers by defining a layer map table in Stream options, but I need to stream out all layers composing selected nets still matching the original layout. Can (...)
Analog IC Design and Layout :: 05-13-2010 16:08 :: rpagano :: Replies: 2 :: Views: 929
I am a beginner of hfss. Currently I met a problem about the model extraction between cadence and hfss and was wondering if anyone could give me help.
I want to first extract a device model in cadence such as an inductor to hfss and simulate it in hfss because I don't trust the (...)
RF, Microwave, Antennas and Optics :: 07-16-2010 11:14 :: yfluo2004 :: Replies: 1 :: Views: 762
I recently worked on cadence layout XL where my task was to design a butterworth filter to match a specification using ASIC Process.I started with CMOS level schematic - to testing the schematic - extracting it to form an extracted Op-Amp - using the Op-Amp to make an 8th order butterworth filter. (and to extract the filt
Electronic Elementary Questions :: 12-28-2010 10:12 :: manrajgujral :: Replies: 3 :: Views: 656
Does anyone know how to use Skill code to show the layers used in the current cadence layout window? That is, only for the layers shown on the current Virtuoso layout window.
Analog IC Design and Layout :: 11-17-2011 10:55 :: Vanderpollator :: Replies: 2 :: Views: 917
Can any one send me the complete layout tutorial?
Analog IC Design and Layout :: 11-02-2013 08:36 :: erikl :: Replies: 3 :: Views: 377
this sites is for fabrication/layout process
a book on asic digital
gives idea abt cadence tool(spectre etc)
Software Links :: 03-10-2003 08:19 :: HBK :: Replies: 0 :: Views: 991
Design with other layout editor as magic and then export to cadence in GDSII format.
ASIC Design Methodologies and Tools (Digital) :: 01-25-2004 06:12 :: bastos4321 :: Replies: 4 :: Views: 2221
From L-Edit, export your design in GDS2 format, then stream in the GDS data into Virtuoso.
Please make sure that the GDS layers between Tanner and cadence are the same.
Analog IC Design and Layout :: 01-23-2005 08:15 :: mm6349 :: Replies: 4 :: Views: 2836
Try and check the .cdsenv file in your cadence Home directory. You will have a field for the layout editor Background.....
I am not sure from here.But with some browsing, it will be done.....I hope that it helps...
Analog IC Design and Layout :: 03-31-2005 02:54 :: Vamsi Mocherla :: Replies: 3 :: Views: 1118
Hi I am trying to export a layout from cadence to a .eps file to import in a LaTeX doc, but the eps file is very heavy (3 MB) even with a small design (100 mu x 300 mu in 0.35 mu tech.). Has anyone found a way to reduce this ?
Analog IC Design and Layout :: 09-05-2005 04:14 :: peterVM :: Replies: 2 :: Views: 1068
goto the newsgroup:
they will provide the information or at least point you in the right direction.
Analog IC Design and Layout :: 11-01-2006 11:17 :: k_90 :: Replies: 1 :: Views: 831
Maybe your version lost few librarys. You can copy these librarys at another person also have cadence. Or you can use L-edit (Tanner EDA) to draw layout(Tanner have version 7.12 for student,you can download free)!
Analog IC Design and Layout :: 11-03-2006 03:31 :: anhtuan :: Replies: 4 :: Views: 946
Maybe you are using the extractor of Diva. There are better tools which can also work with virtuoso. The two mostly used are Assura from cadence and Calibre from Mentor.
Software Problems, Hints and Reviews :: 07-10-2007 01:51 :: tsinghua :: Replies: 1 :: Views: 973
Hi, can anyone help me about this?
I am using ST 0.13um designkits in cadence.
when I am trying to make some layout and DRC, there is an error :
' Poly without implant not allowed'.
Can anyone tell me that does this mean? Thanks a lot.
Analog IC Design and Layout :: 02-19-2008 06:34 :: Beardolphinaries :: Replies: 10 :: Views: 1421
I have created my dxf file in MWO. I then try to import the file to cadence to do some layout but the import always comes up with a blank layout. I have only the thickmetal layer selected in MWO.
Electromagnetic Design and Simulation :: 02-19-2008 09:25 :: drewcam888 :: Replies: 3 :: Views: 2378
If you just want a example for a start, you can copy from the cadence installation directory.
Maybe you need other tools for DRC. Diva is not so powerful and efficient for 0.25um technology.
Analog IC Design and Layout :: 03-28-2008 21:32 :: Hughes :: Replies: 4 :: Views: 894
i am unable to DRC on my layout .
It says No DRC or DRC License (312) is available.
I have checked my license file there is drc license available.
Please suggest something as i have not found anything which helps me out even on cadence Sourcelink database.
This is output after i run the drc in
Analog IC Design and Layout :: 08-13-2008 04:49 :: bhav :: Replies: 9 :: Views: 1559
For cadence layout, do you guys like to generate layout cells from schematic via Virtuoso XL, or prefer to instantiate your own cells and then manually correspond the devices in schematic with the layout?
For me, I have had trouble mapping multiple devices in schematic with my designed multi-fingered (interdigitated) (...)
Software Problems, Hints and Reviews :: 01-25-2010 23:11 :: patricky :: Replies: 0 :: Views: 862
to perform LVS of an inductor in IBM cms9flp on cadence, i need to draw a guard ring around the inductor. when i try to draw a guard ring around the inductor using layout Editor-->Create-->Guard Ring this error message which was generated
*WARNING* (LE-103399): leHiCreateGuardRing: The create guard ring command requires MPP guard
Analog IC Design and Layout :: 02-21-2010 10:38 :: falloutred :: Replies: 2 :: Views: 1793
Even it directly interfaces to cadence Virtuoso...
Here's a description of the design flow for Sonnet within the cadence RFIC environment:
See page 15 ff for a design flow overview with some screenshots.
For interconnect/lines, you m
RF, Microwave, Antennas and Optics :: 05-19-2010 09:35 :: volker_muehlhaus :: Replies: 2 :: Views: 655
1. dump the gds from cadence source
2. calibredrv (mentor tool) will be able read gds
CMD --> calibredrv -m cell.gds
ASIC Design Methodologies and Tools (Digital) :: 05-23-2010 23:59 :: nav_vlsi :: Replies: 2 :: Views: 958
i am having a problem related to layout in cadence.... i made a layout of two stage op-amp in cadence for a perticular set of length of transistors..... now i want to make another layout of same op-amp but now this time the length of transistor is different(change is very little)....... how can i edit the (...)
Analog IC Design and Layout :: 06-14-2010 14:30 :: lokesh garg :: Replies: 3 :: Views: 660
Post added at 16:04 ---------- Previous post was at 16:03
ASIC Design Methodologies and Tools (Digital) :: 10-05-2010 12:04 :: john blue :: Replies: 1 :: Views: 1535
hi i am using cadence 5.1.41 on a redhat platform.
i have generated a symbol for a schematics and the check option shows no errors.
yot when i go to design synthesis layout xl and try to extract a layout a errror pops up saying there is no lx extract layer info in my cdsDefTechLib library
what is the error and how do i get rid of (...)
ASIC Design Methodologies and Tools (Digital) :: 01-15-2011 01:26 :: dipanjan :: Replies: 2 :: Views: 876
I am using cadence LE for doing layout.If I try to make summary report or tree hirachy list from 'design' menu an error window comes.The error is as follows
"Cannot create View file /tmp/Summarya27670"
I checked the permission to craete a file in /tmp/ folder. I have write permission in that folder.
Analog IC Design and Layout :: 02-21-2011 06:26 :: cool_ic :: Replies: 1 :: Views: 623
I have extracted PI model parasitics of inductor in ASITIC and imported CIF file in cadence. It is visible in cadence layout window.
How to use this layout of inductor in my LNA (low noise amplifier) circuit and layout for Schematic and DRC ,LVS respectively. Please help me its very urgent for me. waiting (...)
Analog IC Design and Layout :: 05-22-2011 09:12 :: kapil86 :: Replies: 4 :: Views: 594
I imported a design from cadence into hfss using GDS. Now my problem is I cannot see the coordinates of the geometric solid. Can anyone help me with this? I imported a transformer and I needed to add definitions for the silicon dioxide and substrate, which I plan to add in hfss since cadence does not do this in (...)
RF, Microwave, Antennas and Optics :: 07-03-2011 13:43 :: acbalbason :: Replies: 0 :: Views: 683
I would like to know if any of you has a simple help, tutorial and example of (for example: an inverter) how to layout and post simulate a circuit in cadence 6.1. I do appreciate it.
Analog IC Design and Layout :: 08-10-2011 04:59 :: s_babayan :: Replies: 1 :: Views: 559
Hi, I have just installed a new PDK on my cadence IC 6.1.4, and I have the following errors that I cannot solve! :
1/ When I launch cadence IC6.1.4 with the command: "virtuoso", I can see in the CIW window that the initialization runs a lot of time and finally ends with : "*Error* unknown: Value Stack Overflow!!! (possibly due to too many arg
Linux Software :: 08-26-2011 04:47 :: rlevy :: Replies: 1 :: Views: 725
Following links may help you:
cadence Tutorial 1
Analog IC Design and Layout :: 10-31-2011 07:15 :: sulabh :: Replies: 3 :: Views: 437
Instance cadence' Pcell (parametrized cell) layout views, edit them (q), and fill in W, L, and contact positions.
Analog IC Design and Layout :: 11-10-2011 07:00 :: erikl :: Replies: 1 :: Views: 885
I am using the very useful NCSU design kit for creating masks for microfabrication. I have a major frustration which is the grid spacing is always reset when a new layout is opened. I would like to take this opportunity to create a script (ocean?!) in cadence icfb (5.14) to change the x and y snap spacing with a hotkey.
Can someone p
Analog IC Design and Layout :: 03-09-2012 12:02 :: dfreedman :: Replies: 0 :: Views: 656
If you don't get an answer either here or on your thread in the EDAboard forum, you could still ask in the cadence Custom IC Design forum. I guess they will happily answer!
Analog IC Design and Layout :: 03-21-2012 16:59 :: erikl :: Replies: 1 :: Views: 671
I meet thease DRC errors in my layout in cadence
1. off grid polygon in layer poly, NIMP or...
2.figure having no stamped connectionS.
N+SD to Psub tap spacing must be <=10u
it should be mentioned that thease errors occur even i draw only one transistor using its standard library (create->instance)
I use IC5141 and 0.18um GPDK (...)
Software Problems, Hints and Reviews :: 12-16-2012 07:56 :: rojyar_2020 :: Replies: 0 :: Views: 790
There is a warning "gate used as conductor" after DRC when I use cadence to create layout. The layout is shown in the figure. What's the meaning of the warning? Does that mean I can't connect two transistor's gate using poly?
Analog IC Design and Layout :: 03-09-2013 18:04 :: yuxiaojian01 :: Replies: 2 :: Views: 440
i am new to analog cadence design..i want to ask is it the cadence can automatic layout from the schematic that we draw..??how to carry out it..??
Can somebody teach me..??
Analog IC Design and Layout :: 03-10-2013 23:38 :: jlim :: Replies: 1 :: Views: 327
Iam drawing a layout in cadence for a 2 input nand the Pull down network i used a p substrate for each of the NMOS. For the lower NMOS i connected the substrate to Ground.But, when i connect the substrate of the upper NMOS to the its source as in the schematic,i get the errors
"p substrate stamp error mult,psubstrate stamp error connect" i
Analog IC Design and Layout :: 10-06-2013 13:27 :: gsbkbharath :: Replies: 4 :: Views: 729
Can anyone please help me in knowing the difference between cadence virtuoso layout editor and cadence virtuoso XL editor??
Electronic Elementary Questions :: 02-17-2014 06:19 :: vrinda.thingale :: Replies: 0 :: Views: 257
Hi, anybody knows that there is a way to convert the cadence layout techfile to laker ?
Analog IC Design and Layout :: 07-12-2004 23:12 :: naughtyboy :: Replies: 0 :: Views: 1017
Does cadence ICxxx have a tools or an add-on to manage IC bonding?
... tool that can evaluate the bonding length and inductance :?
Analog IC Design and Layout :: 03-21-2005 09:28 :: okguy :: Replies: 3 :: Views: 1236
you can export your design as gdsii in tanner and import it in cadence.
Software Problems, Hints and Reviews :: 06-01-2005 11:36 :: m_mosazadeh :: Replies: 1 :: Views: 672
Use the cadence documentation, it is the best
U will find it in <cadence_Directory>/doc/vlehelp
Analog IC Design and Layout :: 11-10-2005 07:05 :: eng_Semi :: Replies: 4 :: Views: 1535
I am really confused by the terms in cadence layout tool virtuoso:
active, nactive, pactive, nselect, pselect. anyone can help?
ASIC Design Methodologies and Tools (Digital) :: 12-31-2005 16:28 :: air :: Replies: 2 :: Views: 812
I am running VNCSERVER for the cadence layout.
I want to get the picture of my layout by screencut.
The screencut could work for any kind of desktop except for VNCSERVER, it doesn't work at all.
Analog IC Design and Layout :: 05-01-2006 16:25 :: katrin :: Replies: 2 :: Views: 633
Agilent ADS is not so good for layout design...
There much better tools available such as AWR Microwave Office...
MyChipStation from MyCAD
and of course cadence layout tools
Analog IC Design and Layout :: 11-28-2006 03:51 :: Manjunatha_hv :: Replies: 9 :: Views: 1265