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Cadence Technology Setup

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20 Threads found on edaboard.com: Cadence Technology Setup
Hi everyone, I am trying to convert the tool flow from mixed cadence and Synopsys tools to only Synopsys tools and have a question related to the technology files for the process technology. Is the technology file format for cadence and Synopsys tools the same or different. If i have the (...)
Hi all, I need a tutorial regarding the circuits characterisation/simulation using cadence tools. I need to know the margine (of temperature, voltage, ...etc) in which test are done for the 65 nm technology. Please help.
I encountered an interesting problem here. u create a schematic, u can change the size of MOS as u wish,at this time the pdk is working properly; while u step in analog envrioment, generate the netlist of schematic , if u want to change the size of mos (such as W,L,FINGER,MLTI),an error occured : CDF:an error occurred when evaluating callb
I have recently installed NCSU cadence Design Kit and when i creat a new library and attache the technology file i ge this error *Error* eval: undefined function - pcDefinePCell can anyone show me what is the error and how to fix it
Hi, this is my first post here, and I am new in layout, I just finished a course on layout design, 8 mouths, now I installed fedora core 4 and cadence ic5141 on it,(tried ubuntu 6.06, FC5, no go, seems FC4 is the only one can accept ic5), I got almost all help tips from here, and I am about to ask more, sorry about it, I should contribute more late
hi , i m making a asynchronous fifo in cadence the time of simulation this is giving the same error. if it is not according to the particular process technology parameter then what should i do for this . plz reply as soon as possible .i will be remain very thankful to u.
Hi all! Please let me know if there is any form in the tool cadence SoC encounter where we can declare no. of routing layers for our design with limited no. of metals say 5. But my tool & technology supports 8 Layer Metal. One solution what I found is during design Import we can call technolgy file(.lef) of say 5 Layer metal. Is there any
I am using cadence 514 version i think. there is a parametric analysis function, but i could not sweep corners like ss, typical ff. how could I make it beside ocean script?
hello , can anyone please help me , that my set up time is independent of capacitive load and i am not getting any explanation for that. i extracted my h spice net list from cadence virtuoso layout editor with 45nm technology.also, my setup time is linear with data transition time up to 150 p transition time(data) it possible? any exp
Hello Ppl I would like to know how do u set the grid spacing in cadence for a specific standard library cell ?? Thanks in advance BB
Hello, I am trying to simulate three inverters connected in sequence using cadence ams simulator and a stimulus file that drives the input with a vpulse. I cannot make it work. The input is not driven and stays at 0.3V with vdd at 1v. (All views are schematic) I use the same stimulus file with simulator spectre and the simulation is OK!
after installing a technology file u must add the path to its directory by Library Path editor, after that u can reach the components of the process. the environmet variables u have attached is necessary for launching the cadence tools NOT the technology file! BEST!
Calibre Interactive Hello, I am looking for a layout verification tool (DRC, LVS, extraction...) and I came across Calibre Interactive. Have anyone used it before? Does it have everything that I need (DRC, LVS, parasitic extraction)? Is it easy to install? How easy is it to use compare to Diva? (from what I heard, it only allows gds layou
I am planing to learn ckt design at home. i have managed to get cadence pspice a/d simulator. Now i need some device models to start. where can i get ? can i use it with this tool ?
Hi, Astro (Synopsys) uses a .tdf file to get the input arrangement of I/O cells. I suppose there was a demand for conversion between the tools previously, although I think a LEF-DEF usage would seem more efficient. But you know how this industry is, Synopsys acquires someone, cadence acquires someone... and pretty soon, you have a bunch of d
Hi, I am designing a circuit using AMI 0.6 micron technology in cadence. To design the circuit theoretically, I have a set of equations for gain, BW etc etc.. I need the values of process transconductance parameters kn,kp for the AMI 0.6u process and also the value of lambda (channel length modulation). Can anybody help me out on this?
Sorry,i am not familiar with such a QRC setup...with the settings i see mainly in the first tab i doubt if you can perform an extraction in this best recommendation is to review the cadence QRC manual (located in your Assura installation directory) along with your technology training guide/manuals for a proper extraction procedure. B
HI i am new to the analog based circuit design.. I have been designing folded cascode OTA for 9-bit 200MSPS pipeline ADC in 90nm CMOS technology with the following specifications power supply =1v dc gain= 62db unity gain b/w =1.162Ghz phase margin =68.38deg But when i simulate the following ota for dc gain using cadence tool, im nt able to g
Hi, I have IC614 installed. DRC and LVS are running fine but there is a problem facing during QRC run. Before the details of the error, please have a look at the configuration of my current setup: Platform: Cent OS 5.8 Installed cadence Products: IUS08.20.017, IC06.14.512, MMSIM10.11.218, ASSURA4.12-614 technology: UMC_180_ANALOG [
Dear darockdr, logic synthesis with cadence tools is performed using Encounter RTL Compiler. To perform synthesis you need to provide the tool with the following information: list of HDL files composing your design, top-level entity (while launching the synthesis script), absolute path to the technology library of interest and, in case you have s