10 Threads found on edaboard.com: Cadence Technology Setup
what is the initial region of operation for comparator when we use in 90nm in cadence?
Analog Circuit Design :: 03-20-2015 13:35 :: kvk1806 :: Replies: 3 :: Views: 245
i am using cadence 5.1 on CentOS (RedHat)
i got a free technology files FreePDK45
and i don't know how to add to cadence
i hope you can help me doing this
(iam beginner in cadence)
Thanks a lot
Analog IC Design and Layout :: 09-23-2013 14:32 :: MahmoudHassan :: Replies: 5 :: Views: 515
I have IC614 installed. DRC and LVS are running fine but there is a problem facing during QRC run. Before the details of the error, please have a look at the configuration of my current setup:
Platform: Cent OS 5.8
Installed cadence Products: IUS08.20.017, IC06.14.512, MMSIM10.11.218, ASSURA4.12-614
technology: UMC_180_ANALOG [
Software Problems, Hints and Reviews :: 06-08-2012 07:43 :: samiran_dam :: Replies: 7 :: Views: 982
can anyone please help me , that my set up time is independent of capacitive load and i am not getting any explanation for that. i extracted my h spice net list from cadence virtuoso layout editor with 45nm technology.also, my setup time is linear with data transition time up to 150 p transition time(data) it possible? any exp
ASIC Design Methodologies and Tools (Digital) :: 04-07-2011 16:25 :: email@example.com :: Replies: 1 :: Views: 1182
I encountered an interesting problem here.
u create a schematic, u can change the size of MOS as u wish,at this time the pdk is working properly;
while u step in analog envrioment, generate the netlist of schematic , if u want to change the size of mos (such as W,L,FINGER,MLTI),an error occured :
CDF:an error occurred when evaluating callb
Analog IC Design and Layout :: 10-12-2010 03:50 :: chooly :: Replies: 3 :: Views: 2225
I am using cadence 514 version i think.
there is a parametric analysis function, but i could not sweep corners like ss, typical ff.
how could I make it beside ocean script?
Analog Circuit Design :: 03-21-2010 23:07 :: casual :: Replies: 2 :: Views: 1486
Please let me know if there is any form in the tool cadence SoC encounter where we can declare no. of routing layers for our design with limited no. of metals say 5.
But my tool & technology supports 8 Layer Metal.
One solution what I found is during design Import we can call technolgy file(.lef) of say 5 Layer metal.
Is there any
ASIC Design Methodologies and Tools (Digital) :: 07-01-2009 12:17 :: jitendravlsi :: Replies: 2 :: Views: 923
i m making a asynchronous fifo in cadence the time of simulation this is giving the same error. if it is not according to the particular process technology parameter then what should i do for this .
plz reply as soon as possible .i will be remain very thankful to u.
PCB Routing Schematic Layout software and Simulation :: 03-18-2009 11:04 :: purnima.somkuwar :: Replies: 2 :: Views: 3586
I am trying to convert the tool flow from mixed cadence and Synopsys tools to only Synopsys tools and have a question related to the technology files for the process technology. Is the technology file format for cadence and Synopsys tools the same or different.
If i have the (...)
ASIC Design Methodologies and Tools (Digital) :: 10-07-2007 06:39 :: vikasvij1982 :: Replies: 2 :: Views: 2312
I have recently installed NCSU cadence Design Kit and when i creat a new library and attache the technology file i ge this error
*Error* eval: undefined function - pcDefinePCell
can anyone show me what is the error and how to fix it
Linux Software :: 03-05-2006 14:05 :: ashi :: Replies: 3 :: Views: 1058