37 Threads found on edaboard.com: Cadence Text Editor
You may set editor environment variable in the shell profile. ( .cshrc for csh). The text editor useb by cadence may also be set int the '.cdsinit' file or .Xdefaults.
Analog IC Design and Layout :: 07.01.2005 08:05 :: Hughes :: Replies: 3 :: Views: 5610
I'm a newbie in vhdl coding and ready to learn. I want to enter vhdl file. How to create VHDL file in cadence using text editor is confusing me. Any help would be appreciated.
Thanks in advance.
Electronic Elementary Questions :: 27.12.2011 18:43 :: William22 :: Replies: 2 :: Views: 547
i have an error when trying to close the verilog text editor to compile using :wq
cannot find ncvlog excutable from your path. Please updateyour path to point to the correct excutable or use vmsNcvLogExcutable variable to specify the excutable to use.
any fast help plzzz.
Software Problems, Hints and Reviews :: 05.02.2006 12:25 :: safwatonline :: Replies: 0 :: Views: 1395
If you use the vpulse cell from analogLib library shipped with cadence (not modified) and get these errors, maybe it is a bug.
Software Problems, Hints and Reviews :: 21.03.2006 10:18 :: Hughes :: Replies: 14 :: Views: 4951
i am useing cadence IC 5.141 on Suse 10
i tried to change the editor by be gedit or kwrite instead of the defult editor vi
but when i try open any cell view (eg.verilogA) i get this error
/usr/local/cdstree/tools/lib/libgcc_s.so.1: version `GCC_3.3' not found (required by /usr/lib/libstdc++.so.6)
i tried it with gedit ,kwrite, kate , (...)
Linux Software :: 29.03.2006 19:36 :: ramy_maia :: Replies: 7 :: Views: 7511
Thanks in advance.
Software Problems, Hints and Reviews :: 15.05.2006 04:43 :: asic_ant :: Replies: 6 :: Views: 3467
I am designing DIGITAL PHASE LOCKED LOOP using cadence.
I have written VERILOG-A code for the Digital Phase Locked Loop. But the actual problem is :--
1. I am opening Verilog-A window from CIW and editing the verilog code. It is giving `include "constants.vams" instead of `include "constants.h".
2. If I edit the verilog code by Pressing
Analog Circuit Design :: 23.11.2006 08:20 :: prashanthsree :: Replies: 3 :: Views: 993
Are the model files for MC simulation different than for parametric sweep ?
For EG: I want to sweep Beta but in model files it is given a constant value i.e. bf= 250 if i write bf = BETA only then i can sweep it !
So, Can i edit the model files in text editor and name them differently to use them in parametric analysis?
Digital communication :: 23.05.2007 13:13 :: dozy_walia :: Replies: 0 :: Views: 871
cadence PAS (PDK Automation System) can help create PDK.
Who knows which features needed to run this tool?
Analog IC Design and Layout :: 05.05.2009 04:16 :: tsinghua :: Replies: 5 :: Views: 4398
There are many example model files in cadence installation directory..
Analog IC Design and Layout :: 17.12.2010 15:40 :: BigBoss :: Replies: 14 :: Views: 5134
Select move and in the find filter turn off everything and turn on only the mark in "text". Now move Your txt's and ritgh click to be able to turn the txt.
You might wanna look at cadence forums or at sourcelink to find some skill that do task automatically.
PCB Routing Schematic Layout software and Simulation :: 25.08.2009 06:38 :: lhademmor :: Replies: 1 :: Views: 2108
cadence, like other vendor, has their own proprietary format, so you won't be able to use any other tool (e.g. text editor) to view their file (it's in a binary form by the way). However, cadence, like other vendors, also support the open format VCD, which is in a text file.
For your purpose, it's (...)
ASIC Design Methodologies and Tools (Digital) :: 18.02.2010 04:08 :: skyfaye :: Replies: 2 :: Views: 1458
Set the environment variable editor=<editor PATH> in your run cadence script.
Software Problems, Hints and Reviews :: 05.05.2010 16:26 :: kingweck :: Replies: 1 :: Views: 1113
I just want to ask, is it possible to plot a model parameter.
I want to plot vth (threshold voltage) of a transistor as i sweep input voltage.
Analog IC Design and Layout :: 23.08.2010 01:19 :: aindejeje :: Replies: 6 :: Views: 2109
For cadence simulation I am not using ADE instead I have to generate spice netlist, generate the test bench according to circuit parameters, convert it to spectre and then run the simulation using unix command. My problem is this method is totally new for me and don't have any idea how to edit test bench, write a syntax and run sim
Analog IC Design and Layout :: 04.10.2011 18:38 :: brjaiswal :: Replies: 7 :: Views: 1602
Whenever I did not have Viewall() in the cadence Virtuoso layout editor, I could not see the note text in cadence Composer schematic editor. Every time it happened, I had to open the layout editor, hit the Viewall() command, then, went back to schematic editor to see all (...)
Analog IC Design and Layout :: 14.11.2011 10:00 :: Vanderpollator :: Replies: 3 :: Views: 967
I have tsmc18rf technology with all necessary files. I tried to add that new library so I can make simulations and layouts in this technology.
I go File->New->Library. Appears new window where I give a name to my technology, ande where I should choose Technology File. I check "Compile an ASCII technology file" then go Ok. Now I ne
Analog IC Design and Layout :: 05.02.2012 09:55 :: Spliter :: Replies: 3 :: Views: 1447
Hello to everyone,
I am new to the cadence OrCAD Capture CIS and Allegro suite. Now I need to create a pcb with those tools. When I activate the generation of the netlist I get the following errors/warnings:
* Netlisting the design
PCB Routing Schematic Layout software and Simulation :: 01.08.2012 06:59 :: clupus :: Replies: 4 :: Views: 1805
There is a bin to transform the nxtgrd file to it, provide by cadence.
Some foundry provide this icy file was well.
ASIC Design Methodologies and Tools (Digital) :: 05.05.2013 02:37 :: rca :: Replies: 2 :: Views: 708
something weird going on - anyone have expertise here? i have run out of options to try...
new project (library), new cellview (called onefet). edit schematic to include 1 nmos, 1 resistor from drain to vcc, 1 vcc of 5v and 1vg of 2v (to gate). all seems fine.
when simulated with spectre, it reports that nmos N0 has no model. this happens
Linux Software :: 25.06.2003 05:45 :: electronrancher :: Replies: 9 :: Views: 1845
annyone who can tell me how can i convert spice3 model to pspice9 model? i use pspice 9.21 in cadence PSD 14.0.
Thanks a lot!!
Software Problems, Hints and Reviews :: 16.11.2003 19:36 :: yaodao :: Replies: 4 :: Views: 1424
edit your profile file in a text editor and write these two lines
PATH=$PATH :/path to executable of cadence in bin folder
Software Problems, Hints and Reviews :: 01.06.2005 11:41 :: m_mosazadeh :: Replies: 4 :: Views: 1186
We have cadence IC 445 installed on a Sun machine ( SunOS 5.8 ) and it works nice.
Recently we have installed IC 5.0.33. However, some strange things happend. In Virtuoso schematic editor, the grid is not shown, altough it's set and the instances align to the grid, which tells me that it exits but it's not drawn. In IC 445 the grid is shown
Linux Software :: 08.06.2005 12:17 :: blue_moon :: Replies: 0 :: Views: 1085
i changed the default vi text editor in cadence to jedit , how can i compile with the new editor as in vi i usually use ":wq"
Linux Software :: 16.06.2006 14:01 :: safwatonline :: Replies: 3 :: Views: 1006
i am getting DRC error as HOT NWELL while running drc for any circuit in cadence VIRTUOSO layout editor. how could i rectify this.
Analog IC Design and Layout :: 15.03.2007 01:36 :: rmadhukarthi :: Replies: 4 :: Views: 3850
I am afraid that you've got the question wrong....more appropiately I did not provide proper explaination.
I don't want to use any layout editor ....that is quite simple.
I just want ...
GDS1------> DO SOMETHING -------> GDS2 (with added texts)
DO SOMETHING : can be a script.
If i;ve a layout editor ...its quite simple to (...)
Analog IC Design and Layout :: 27.07.2007 07:37 :: truebs :: Replies: 5 :: Views: 982
What is the value of vthn, vthp, λn, λp, ?nCox, ?pCox in gpdk 180n library for simulation in cadence spectre.I am using 1.8 voltage supply.
Plz reply if anyone knows.
Its needed to start my ota design.
thanq in advance.
Added after 1 hours 40 minutes:
please reply someone.
Analog Circuit Design :: 30.10.2008 05:22 :: shweta_eda :: Replies: 1 :: Views: 789
Spectre is a whiney b!tch and cadence won't do anything
about that. It allows and requires you define a model once
and only once. Evidently tolerance of errors and redefinition
was just too difficult to code up. Strange, since they were
built by looting SPICE and CAD experts from their customers
who had witten much better user interfaces.
Analog Circuit Design :: 28.12.2010 16:05 :: dick_freebird :: Replies: 3 :: Views: 734
hi to all.....
ve a good day....
I m new to this forum....
I m making a pcb in caence16.3....
I ve idea with orcad9.1 layout....
please help me in routing in cadence with ur suggestions...i ve done manual routing taken so much time...
If I want to change the ref text font size...wat ve to do??....
how to make gerber files....??
PCB Routing Schematic Layout software and Simulation :: 09.09.2011 02:14 :: santu7885 :: Replies: 2 :: Views: 1367
I would want to create a symbol in cadence with Part developper but I can't access to the symbol editor.
I use the Part developper Tutorial (chapter 9).
Does nyone could help me ?
PCB Routing Schematic Layout software and Simulation :: 10.07.2012 14:56 :: glias :: Replies: 1 :: Views: 650
I want to do verilog-A coding in cadence,but the text editor not showing function/title bar.Can any one help me on this.
Analog Circuit Design :: 20.01.2013 08:48 :: satya193 :: Replies: 0 :: Views: 140
cadence use "home" env setting to seach the path of "pcbenv".The default setting of "home" in 2000/xp is "c:\documents and settings\%profile%\",so you need change the setting to such as "Home=C:\",then cadence will use "c:\pcbenv" to save your setting.
PCB Routing Schematic Layout software and Simulation :: 16.05.2003 05:08 :: winworm :: Replies: 1 :: Views: 1748
Probably depends on what tools you need to communicate
with - netlist output facilities, do you want to be able to
probe simulation results driven from schematic or more
"old school" (text netlists and text waveform select)?
Verification, are you going to do a SPICE:SPICE LVS
or do you need schematic to cough up some other
format (like Cad
Analog IC Design and Layout :: 17.09.2009 12:25 :: dick_freebird :: Replies: 6 :: Views: 1164
Simplest is to create a symbol (with no schematic) - Why not copy the us_8ths and then strip it?
Then add what ever features/logos you like. For this symbol you can also add all those nice text labels that you want.
To add your own logo it is sometimes easier to first draw the logo with the layout editor and then copy it into the symbol (...)
Analog IC Design and Layout :: 31.05.2011 17:03 :: jjx :: Replies: 2 :: Views: 733
Which editor can read a script from cadence in windows environment? Not run it, just read the content as normal text.
Analog IC Design and Layout :: 03.11.2011 05:09 :: dkace :: Replies: 1 :: Views: 488
if you ever start working with any place/route tools they use TCL scripting. And most of the tools do also. So yes learn... Perl is nice in a way that it runs everywhere - that said it is also one of the most confusing languages I know....
Not very confusing , but comes in very handy. If you know PERL, Tcl should come i
Analog IC Design and Layout :: 05.12.2011 22:56 :: jeevan.life :: Replies: 4 :: Views: 559
I'm taking a long transient simulation in cadence Spectre, the simulation is to calculate the BER(bit error rate) of a transistor-level circuit.
Because I have a symbol which is written in Verilog-AMS to calculate the BER and store the result in a text file outside, so I don't need the cadence to store any simulation (...)
Analog Circuit Design :: 26.06.2012 18:05 :: ccarrot :: Replies: 5 :: Views: 1071