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I'm looking for tutorials on PCell generation in cadence virtuoso. Is there any documention or tutorial that could help? Dr.Prof
cadence virtuoso Schematic Editor. Information can be found here:
Hello, I need some basic tutorials on cadence virtuoso showing step by step how to draw a schematic, it's symbol, how to attribute the symbol to the schematic and how to simulate this device. Thanks in advance.
Hi guys, I am going to do a project related to using cadence virtuoso to design a RF transmission circuit. However I dont have any RF PDK at the moment. The version I am using is cadence 6.1 . Any suggestion where I can find PDK for that, I did ask my teacher but still waiting from him. I went through some RF CMOS design (...)
Hello Happy new year :) i wish you all new year with a lot of achievements and all your dreams come true :) Actually i want to learn cadence virtuoso ...i have now a little experience with OrCAD PsPICE (Beginner level also :( ) but i want to ask about prerequisites to learn ? some advised me that i need to learn a little about Linux (I did
I've done a layout using cadence virtuoso and I want to export it to Silicon Ensemble to connect it with another design. Does anybody know how can I do it? Thanks
Does anybody know how to archive cadence virtuoso Composer projects? To be more specific, to archive for example only 1 view or to archive hierarchically trough your complete database? Tnx. S.
I don't know Encounter. But if you can export the layout to GDSII format, it can be imported to cadence.
Hi, I have designed a spiral inductor in cadence virtuoso and in the Schematics I designed the equivalent pi-circuit with lumped passive elements. I want to make LVS. The layout passes successfully the DRC check. However in after the LVS running I get the message that there is a short between the ports, which makes sense since the ports are on th
From L-Edit, export your design in GDS2 format, then stream in the GDS data into virtuoso. Please make sure that the GDS layers between Tanner and cadence are the same.
Hi I need to know how to obtain a list with all net names of a design in cadence virtuoso because I want to do a RCX-Extraction of selected nets with Assura. Thanks
At present they are promoting Assura. Other DRC tools from cadence are Dracula and Diva
who know how to use batch command "si" to cdl out netlist from cadence virtuoso editor tool?
Hi I am using cadence virtuoso XL for layout design.. When i am trying to design a layout with multiple blocks, i am facing a lot of problems while making the interconnections. While connecting the blocks many a times the block gets selected and gets moved from its place. So is there any way by which i can freeze the locations of the block so that
I mean that I install cadence virtuoso on linux. I found that there are some file in lib directory. How to use this file? Thanks
Hi guys, is there a way to import a schematic drawn using OrCad into cadence virtuoso Schematic for editing? Thanks
I need cadence virtuoso layout manual , 5033 please send a link about that. thanks
Hi, Is there any option to measure the angle in the cadence virtuoso Layout Editor without using the Tanθ calculation? Regards Sooraj S Ram
can we place and route using standard cells of gates in cadence virtuoso?????/ thanks in advance, Prasad
Hi, Is there any option to measure the angle in the cadence virtuoso Layout Editor without using the Tanθ calculation? Regards Sooraj S Ram
Hi all, I want to install cadence virtuoso for simulate and layout. But I don't known how the hardware require? and What version of Linux I need? ( Can I use Redhat8.0 or Redhat10? ) Can somenone give me some advice about my problem? Thank you very much.
Hi all, I have installed cadence virtuoso 5.0.33. I use Redhat9. And there are some error: When I start virtuoso there is a warning : ' Incorrectly built in binary which accesses errno, h_errno or_res directly. Needs to be fixed.' And some functions can not use : can't use some buttons, can't double click to chose file (must (...)
Use CETOS (a free clone of REDHAT EL), I installed cadence without any kind of problem
Hi, dear all, I'm planing to run cadence virtuoso on our unix workstation. It is installed in /usr/local/cadence2006 After I run source /usr/local/cadence2006/00setup.cdk, I can run layout &, layoutPlus &, or icfb & to run virtuoso. But I don't know how to set the configuration file, such as (...)
hope it will help you tc:D
I tried to read the virtuoso manual and spectreRF simulation manual but I can not define the parameters of the diode in cadence virtuoso ver.2004 Could you guys please fill out the blank of the parameters about any diode in cadence? I also attach the pictures including parameter.
hi everybody can any1 help me out in this que what are the good features of cadence virtuoso over others as it is use in maximum companies for full custom regards silicon_m
No! cadence virtuoso Layout Editor doesn't have this feature. I know the only layout editor that has this capability: Tanner
I am new to cadence virtuoso wat is meant by technology file? how can i import the synthesised hdl design i.e .db file (gatelevel netlist) into virtuoso. does any one has virtuso tutorials or labs? please help me.
Hi all .. can anyone suggest me how to get technology file for cadence virtuoso schematic editor? pls reply me if you know.. my email id
Hi all, Who can tell me what these options in cadence virtuoso are used to ?
I need to download cadence virtuoso but i search for it but i cannot find the source any one can help me
Hi members, I need cadence virtuoso Layout Hotkeys. Is there any document for that ? Thansk in advance.
Hi guys I intend to use cadence virtuoso in mixed-signal Design my question is about the digital part how a digital block is inserted in the workspace is it used as a block of vhdl or verilog file with I/O ports to connect with the analog parts or inserted as a synthesized netlist generated for Synopsys DC or cadence (...)
Hi, I am using cadence virtuoso to design a VCO. When generate layout from my schmatic, I am not able to see the pcell of the components. THere are only symbols with names in the layout window. How can I see the pcell of the components? Thanks.
i have to calculate power of the circuit how can i do it in cadence virtuoso spectre design flow. and how i can calculate leakage power in cadence.
how to calculate power(dynamic and leakage) in cadence virtuoso/spectre design flow.
how i can be able to invoke a high thrshold transistor in a cadence virtuoso/spectre suite. i am using ams hitkit 0.35u support. please help me.
Hi, When I am using cadence virtuoso and print the operating point of the MOS device, I notice that there are several different capacitors For example, Cgg, Cgd, Cgs and Cgb. What do these mean? Why some of them are nagetive? And seems that Cgg=Cgd+Cgs+Cgb no matter the polarity of the values. Can anybody give me some explanation plea
Hi Can anyone give link to download cadence virtuoso? plsss
Hello everyone, Is there any way I can plot Total Harmonic Distortion of the output vs. the input voltage or current or power in the cadence virtuoso environment? What I have managed to do so far is to calculate the harmonic distortion for a given input via a transient analysis and by using the thd special function in the calculator. I was wo
hi there, what is config view in cadence virtuoso environment and the difference between schematic view, thanks! regards, henry
Hello, I'm new to cadence virtuoso and I have a question that might seem trivial. Is it possible to set input as my own custom waveform to the circuit when simulating? If so how?
I don't know how to sweep the w over L ratio and couldn't find any relevant info on the web...whlinfei Find here a cadence tutorial about parametric simulation:
Hi, I used cadence virtuoso layout editor and set display X/Y snap spacing to 0.01. However, while I tried to draw rectangular layers, I could not draw what I want. It seems that snap is much bigger than 0.01, so I either get huge rectangular or nothing. How can I set to draw any size or rectangular with 0.01 as step? Thanks a lot,
anybody can tell me how to calculate the power analysis of circuits using cadence virtuoso. give the procedure and steps, both ac and dc analysis. thank you
Dear All, I'm doing the layout of a low noise differential amplifier using cadence virtuoso XL tool. I've just realize that, for better matching, I want to split the input transistors in two so that I can use a common centroid technique. I've just splitted the transistors on the schematic view but I don't know how to update this change on the
Has anybody used cadence virtuoso Schematic, which is mainly for IC design, to draw schematics, import the netlist with Allegro, and do PCB layout in Allegro? How was the experience with this flow? Thanks, kentauta
can anyone guide me on how to attach a word document to schematic designed in cadence virtuoso icfb Not just with one click, but it can be done: plot the schematic to a PostScript file (e.g. schem.ps) - this is the standard file format for plotting to a file convert your .doc into a .pdf (e.g. doc.
How to draw a round spiral inductor in cadence virtuoso?