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95 Threads found on Calibre Assura
Some more ideas: 1. Forgotten contacts between diodes and the ME1 to VDD/GND connection (or vias instead of contacts). Very unlikely - and I'd suspect that assura would have recognized it, too. 2. Try and check your calibre ERC rules' file for this very error. Perhaps you can find more info about its layer-dependent formation hi
Hi everbody, I have Installed IC610, MMSIM12, assura and calibre 4.12 x86_cal_2011.2_34.26 ON the Ubuntu 10.04 32 'bit the OS. I got a problem with calibre interactive below, 127577 *** calibre Interactive: Exporting layout for library "tsmc18rf", cell "transistor", view "layout" *** sh: pipo: not found I
Use foundry provided Density rules - as freebird stated above.. these are kind of DRC rules.. calibre, PVS, assura can do a density check. Back to Basics: Metal Density - is a point function, and therefore various functional representations are possible, {there is nothing like absolute value of density}. That means - different functional represent
Hi, I am designing a mixed signal circuit, while for the digital part I could run LVS directly using .v file from encounter with the standard cell cdl file, but for a mixed signal circuit, and I don't have the nettran from synopsys and v2lvs from calibre, we have only assura to run everything, how could I run the LVS......please give me some tip
Hello, Is seems like your extraction tool use real capacitor and resistors instead of pcapacitor and presistor. But I don't shure with it. Do you have other extraction tools? assura or calibre maybe...
Hi just make layout and perform extraction operations with assura or calibre :) Or, perhaps you have RFmos in your technology library and, in that case all parasitic capacitances of mos already included in model.
Hi, There is a option in calibre.. in which same label metals are shorted virtually while runnin LVS ,DRC and PEX. But i dont know about assura.. Thanks
Hello All, I have to generate dspf file of register file 64x17.i clear the lvs by using calibre and when i use assura to clear lvs than there is parameter error. I check the particular transistor length and width and found both parameter correct. Now, how can i remove this to generate dspf
Hi msdarvishi, My TSMC kit does not support assura, only calibre. DRC is strightforward : "runset" is not compulsory. In the kit installation directory, you should have a "calibre" directory, with "drc", "lvs" and "rcx" subdirectories. Just load calibre/drc/calibre.drc rule file for default DRC. After (...)
Hi, the foundry's DRC deck includes a minimum-area rule for all the metal layers. I would like to modify it to ignore this rule if the metal polygon has text on it (text indicates that the metal is a point to which higher levels of the hierarchy might connect). This way I can run DRC on subcells that export less-than-min-area metal as ports. At
I wanted to convert calibre rule files to assura rule files because those are the only rule files available from the foundry at the moment. Is there any script available for that? What languages/methods could one learn to perform this task? How difficult and time consuming is it? Thanks for your help.
hello everybody, i have got a problem with assura LVS.The calibre LVS run "cellA" has completed successfully without any errors.But the assura LVS has a problem.Below is the assura lvs problem. The LVS run "cellA" has completed successfully . Compare problems were detected in 3 cells. 3 cells had devices mismatches. (...)
Is it possible to use Cadence design kit (gpdk045) for calibre DRC, LVS and QRC? I can only find assura rules in gpdk045, so if possible, how? Were the answers from the Cadence forum not good enough?
calibre or assura? If you have multiple-bends resistors you need to use SBAR_Feature (or similar) swicth for assura. The second idea is to surround resistors by SwGuardRing (e.g. by multipart path)
I have a lot more experence with calibre and not so much with assura. I have a large analog block with a net that will be connected at a higher level. so lets call this net GND. in my block i have 3 lower lever blocks that have GND inside them, they are not connected at this level. but, i want LVS to vertually connect them at this level. how
Hi luca we have used TSMC 65nm (PDK v1.5a) in a few designs. calibre flow included RCX/PEX is supported with some caveats. We have never touched assura but is seems no DRC rules are provided. Let me know what the issues are with calibre and see if I can help. Cheers
Hi, I have a rule in calibre that need to be converted into assura drc. Please help me. VIA1.R.2_FSG { @ When M1 or M2 width > 1.4um, more than 1 VIA1 is required. @ if the metal has < 4 vias, vias spacing should be <= 0.71um, @ or if the metal has >=4 vias, at least 4 vias spacing should be <= 1um How can I detect via arr
hi....... Tools like calibre,hercules,assura using these we can check the depends upon the vendor 's rule deck file..They will mention the tool to be used for certain rule file.. Thanks ,we have herculus in our college computers.
You can get the netlist file of your layout only if there is a schematic corresponding to your layout. That's not quite correct, I think: The extraction tool (diva, assura, calibre) can extract a netlist from a layout -- it doesn't need a corresponding schematic for this. Only the LVS tool needs it.
you need to work with CAD. The info you gave is very little to help. calibre, assura and HERCULES have a different methods of running LVS.
Going to higher frequency, I can definite see significant difference in calibre and assura extraction. calibre extraction has been adding extra gate resistance somehow (for a tsmc kit), I don't quite understand why it does that.
Well, the correct answer is Caliber, because, the right name is calibre :) . To be serious, it depeneds on used technology: for nanometer techs, the widely used tool is Mentor calibre. Synopsys Hercules is still used, but it is enough old and replaced by Synopsys IC Validator. Regarding assura - it may be used for old technologies only, for (...)
Hi, In my design, I'm working on a very old twin tub process. so, i don't have a latchup ruledeck and so i gotta verify latchup related stuff manually. I'm using calibre for verifications. I don't have assura etup for this technology. I verified most of the latchup guidelines like region related, guard ring related. etc. The process guidelines s
Need more clarity on the question. RFMOS "device" extraction should be happening at the LVS extraction stage - what does that has any relation with RCX? If this is LVS problem - which LVS tool Which technology? layout of "big" and "small" rfmos may help, overall more details will help.
Hello Guys, Do anyone know how to configure the xRC (calibre extraction) in order to create a compact extracted netlist? In assura, we can define the minimum value of R and C, also merge resistors (and so on...), what makes the extracted view more compact and faster to be simulated. How can I do this with PEX? Thanks in advance.
Dear all i had lot of confusion will any chance to use assura for verification in SOC Encounter.(plug in)chance...or must use calibre/Cadence physical verification?? Thanks && Regards....pls give help..
I am using IC5141 and I have neither assura nor calibre installed. I am going to download one of these tools. Given a Cadence version, is there any rule in order to choose assura or calibre? If I choose assura, which are the steps to follow after installation? I know I should add some settings in my (...)
Hi there, I am using umc130nm and I am having problems in running DRC and LVS checks. First of all, I am not sure about the tool. I know that usually calibre or assura are used. Notwithstanding, when I launch the layout editor from the schematic, the only option is "Layout XL". After I lay out my circuit in Layout XL, I have
It could be a mismatch in the number of fingers, some LVS decks check for it, try changing the number of fingers in the schematic for one of the devices flagged as mismatched Otherwise provide more details: what LVS tool are you using? assura, calibre,...? what process/PDK?
Hi dipanjan, there are a few people in this forum that struggled with assura LVS in UMC18 (apparently you have problems even in DRC), I have tried some of the devices in calibre and they work just fine so I think is an issue with assura; make sure you are stamping your connection using a label/pin/textDisplay in the correct layer:purpose (...)
you are not the first person reporting issues in assura LVS with umc18 PDK, I do not have assura so my help is limited in that area. If you have calibre it works well in that PDK As of the contact problem, it is not clear: which contacts are you missing? you keep saying that you were able to use m1-pdiff; the contacts are defined in the (...)
hi all assura QRC layout or calibre PEX extraction tool is better ? What is the advantage and disadvantage? Thanks
Our foundry advises provides rule decks for all three tools. As per their notes, calibre is better at detecting width/space violations and assura is better for density checks. Nothing specific about Hercules.
calibre extraction more accurate regarding to my experiences.But it totally depends on the technology that you would use. Because extraction rules are defined by your tech. file and it is dependent on its accuracy and definitions.
Hello everyone, I am currently designing a bandgap reference (BGR) circuit in IBM cms9flp. Using assura for LVS the circuit is shown to be correct (layout schematic match, and no extraction problems) When I use calibre the result is Correct again, there are no extraction problems, BUT there is an ERC error. The description of the e
Hi serhannn, Please when posting a DRC/LVS/QRC error you should be more specific,that is you should show the exact error given by assura/calibre etc...For your case,i think that you should create a n-well contact ring around your pmos transistors and then connect this ring to Vdd.Give it a try and see if this corrects the error. N-Well contacts c
Does anyone know the price of Verification tools. assura, calibre and Hercules. The list price or the price after promotion. Thanks a lot!!
Yes, In your case - LVS & QRC QRC supports two independent flows : 1. LVS flow 2. LEF-DEF - also if design is in Open-Access, run QRC before you port to GDS or OASIS. rsf is old - ccl is new. The good thing is - same unified qrcTechFi
which DRC are you using, assura or calibre? does the error exist when you use the other one with "CHIP" design type? contact MOSIS if you are a customer MOSIS_Users_Group : MOSIS User's Group
Hello guys: I have tsmc018rf library,include technology lib, calibre/assura verify, spectre/ADC/eldo/hspice model and design kit. But I need 90nm process. we can share each other. OK?
calibre is sign-off tool
you can use calibre or hercules.. I/p's are gds or oasis database and spice netlist you can get rule deck from tsmc/umc foundary..
Hi everybody, I am doing some test design (an inverter) in order to get used to the IBM 90nm process cms9flp. I pass succesfully drc and lvs in assura and calibre and the assura qrc also ends succesfully. the problem arises when i run a DC simulation including the parasitics, using av_extracted view of the inverter. I get some curious (...)
It is possible to do LVS even if you do not have the gds/spice info of the standard cells. This is done by labeling all the cells as blackbox in calibre or assura.
I take it from the errors that you're using an IBM PDK? Insert Image_bevel, set the dimensions of your chip and make the origin (0,0). If you're not in the final stages of your design, you can do calibre and assura DRC with the "Cell" switch on so that it doesn't do checks related to CHIPEDGE.
Is there a way to convert an assura deck to calibre format, or can the calibre tool read a deck that is in assura format? If a script exists to convert the formats, where can I find it? Thanks!
Hi all, I did extraction from calibre xRC and got "calibre" view. When i simulate it by changing the config view of the testbench I get the same simulation results as that of schematics. Where I am making the mistake? I did extraction with assura and its av_extracted shows the desired behaviour, that is it shows the affect of parasitics. (...)
You can also do the same in calibre, depending on your LVS tool.
Sorry if this topic make you bored. Firstly I have the cadence done the LVS using assura, and it worked. However my partner only has calibre for doing LVS; and the problem arises. I read the discussion here: , I tried to follow the solution but not worked. I am using IBM PDK cmrf8sf V1.6.2.
a) what technology - each process is slightly different although foundries often claim that are compatible with foundry xxx b) What tool - you will probably use calibre(Mentor) or assura(cadence) c) so you should go to the PDK installation tree and look for files for DRC for any of the tool. Or go to the foundry website and look for DRC comma