134 Threads found on edaboard.com: Calibre Assura
Going to higher frequency, I can definite see significant difference in calibre and assura extraction.
calibre extraction has been adding extra gate resistance somehow (for a tsmc kit), I don't quite understand why it does that.
Analog IC Design and Layout :: 01.05.2012 19:19 :: snaildr :: Replies: 2 :: Views: 570
only cds generate the extracted view. calibre is gds->spice
Analog IC Design and Layout :: 24.03.2004 02:41 :: rfsystem :: Replies: 4 :: Views: 3726
it is obvious trend that alll foundry and design house adapt the calibre as the standarize signoff tools.
ASIC Design Methodologies and Tools (Digital) :: 23.02.2005 21:44 :: xuxia :: Replies: 20 :: Views: 3066
I like calibre more than assura. The assura have endless bugs and too many fault errors.
Analog IC Design and Layout :: 18.06.2005 12:49 :: kwkam :: Replies: 9 :: Views: 1392
why not. if you got gds (from magma), you can check it with any drc tools include calibre, assura, hercules etc.
ASIC Design Methodologies and Tools (Digital) :: 26.06.2005 21:23 :: z81203 :: Replies: 7 :: Views: 909
If you invoke calibre from Cadence Virtuoso, you may hilight error in the layout window.
Analog IC Design and Layout :: 31.07.2005 03:44 :: Hughes :: Replies: 7 :: Views: 3451
calibre gives better checks than assura
not realy, the results are same ,but is more fast and cheap . mentor tools are more cheap than cadence . my company migrate fom cadence to mentor because of the price of the license :)
Analog IC Design and Layout :: 11.03.2006 16:25 :: Sergiu_Q :: Replies: 11 :: Views: 4884
I think calibre is the best choice! Because it is the signoff tool in the world!!
ASIC Design Methodologies and Tools (Digital) :: 10.04.2006 04:28 :: kermit :: Replies: 3 :: Views: 694
After I used many years calibre and from time to time Dracula for layout parasitic extractions, now I have to do this with assura.
I find few things that put me in a difficult position, and make to untrust assura results. (Like a conffirmation that assura don't work properly)
Description case 1:
I have two (...)
Analog IC Design and Layout :: 26.06.2006 05:58 :: gabi71ro :: Replies: 0 :: Views: 567
well , lets just say i am using calibre now
Analog IC Design and Layout :: 05.07.2006 09:48 :: safwatonline :: Replies: 4 :: Views: 2840
there are interface between calibre and virtuoso,t that is means, u can get all the calibre' results information (drc, lvs, erc and attena errors).
Analog IC Design and Layout :: 18.10.2006 10:39 :: Areky_qin :: Replies: 3 :: Views: 887
My name is Raj from hyderabad ,India.I just completed Post Graduate Diploma on IC layout engineering of University of California with sound knowledge on Layout ,Place and Route,Verification,CrossTalk.I finished M.Sc(electronics) in march 2006.
EDA Jobs :: 03.12.2006 13:15 :: dsairajkiran :: Replies: 7 :: Views: 1280
My name is Raj from hyderabad ,India.I just completed Post Graduate Diploma on IC layout engineering of University of California with sound knowledge on Standard Cell Layout ,Place and Route,Verification,CrossTalk.I have good knowledge on STA and logic synthesis.I did project o
EDA Jobs :: 03.12.2006 14:27 :: dsairajkiran :: Replies: 2 :: Views: 760
Can I do RC-extraction without netlist?
I have gds file from Astro.
but I don't have netlist file of that logic.
That logic made from verilog source synthesized by Desgin complier.
Can I get extraction result?
I think it can't get result.
You need netlist to run LVS(hercules, calibre) software.
The LVS softwa
ASIC Design Methodologies and Tools (Digital) :: 24.01.2007 01:54 :: chyau :: Replies: 2 :: Views: 565
Hi, What are the difference and advantages of using the following tools??
I think all products from Cadence and they are doing similar jobs like DRC, LVS, and parasitic extractions - physical verifications.
What are the differences?? and advantages ??
how about calibre? I believe this product is from Mentor
Analog IC Design and Layout :: 21.01.2007 17:00 :: ee484 :: Replies: 4 :: Views: 2621
I used Ecounter with "saveNetlist –includePhysicalInst –excludeLeafCell CHIP_LVS.v" to write a verilog netlist in order to run a LVS.
I would like to use assura for LVS - because calibre is not available here. Could someone give me some guidance how to use the "physical" LVS-Netlist with assura for LVS against the (...)
ASIC Design Methodologies and Tools (Digital) :: 12.05.2007 06:09 :: avt :: Replies: 0 :: Views: 1040
The best would be to go to Cadence SourceLink - there is all documentation you need.
assura has its own commands which are similar to those in Dracula or Diva.
If you know how to write calibre then it is quite easy (well in my experience) to switch to assura.
Analog IC Design and Layout :: 14.06.2007 03:28 :: Teddy :: Replies: 1 :: Views: 1063
I'm not a BE engineer but calibre is the DRC sign-off tool at my company.
ASIC Design Methodologies and Tools (Digital) :: 21.08.2007 23:57 :: gliss :: Replies: 9 :: Views: 1227
I am having the calibre drc rule deck for the process, but i dont have calibre tool, but i am having the assura tool.
Can I use the calibre rule file in assura tool? Is there any option in assura to import calibre rule file?
thanks in advance...
Analog IC Design and Layout :: 21.08.2007 03:56 :: sunny153 :: Replies: 7 :: Views: 2640
Can any one tell me how can I use Cadence assura to extract parasitics while using calibre LVS in the verification flow?
Thanks in advance,
Analog IC Design and Layout :: 29.08.2007 08:31 :: ahmad_abdulghany :: Replies: 0 :: Views: 1029
I came across these names assura, Dracula, calibre, Hercules. what is the difference between them? it got me confuse. most of the time i use calibre for DRC and LVS verficication, but sometimes assura is also used.
Analog IC Design and Layout :: 01.11.2007 02:22 :: surreyian :: Replies: 12 :: Views: 6459
I don't know really assura tool but with calibre from Mentor you need basically your layout (*.gds), your source netlist (*.sp) and in option a rule file.
In the rule file your are some information like where are your file on your computer the name of your output file(extracted netlist, report file,...).
Be careful a LVS makes just a
Software Problems, Hints and Reviews :: 14.04.2008 08:19 :: bachy :: Replies: 1 :: Views: 1175
Which is the best tool for verification,userfriendly for layout
vote for ur best verfication tool.
Analog IC Design and Layout :: 28.04.2008 05:56 :: sridhar540 :: Replies: 23 :: Views: 2205
Analog IC Design and Layout :: 27.11.2010 08:28 :: juson88 :: Replies: 2 :: Views: 1129
Right now, I am doing the lvs of my circuit and layout and I always get error: in the schematic, the circuit has 3 pins and in the layout, I also create 3 pins and their labels but when I do the lvs, I get the error "different number of ports in layout and schematic" which means that calibre can not find the pins I create in the layout
PS I de
Analog IC Design and Layout :: 10.07.2008 12:54 :: aaronwlee :: Replies: 4 :: Views: 928
i had lot of confusion will any chance to use assura for verification in SOC Encounter.(plug in)chance...or must use calibre/Cadence physical verification??
Thanks && Regards....pls give help..
ASIC Design Methodologies and Tools (Digital) :: 10.01.2009 06:54 :: sarathmandepudi :: Replies: 2 :: Views: 995
Anybody experienced in BE verification can help me regarding how to link calibre LVS to assura QRC? What are the documents talking about that point in particular?
I have slight information about CCI output from calibre LVS which is a format that is somehow fed to QRC. But I need some extra details..
Thanks in advance,
Analog IC Design and Layout :: 25.03.2009 11:15 :: knack :: Replies: 1 :: Views: 1442
I am looking for a layout verification tool (DRC, LVS, extraction...) and I came across calibre Interactive. Have anyone used it before?
Does it have everything that I need (DRC, LVS, parasitic extraction)?
Is it easy to install?
How easy is it to use compare to Diva? (from what I heard, it only allows gds layou
Analog Circuit Design :: 14.04.2009 16:39 :: pokemonstation :: Replies: 2 :: Views: 1451
we jus shifted from calibre to assura......
for lvs I am facing this problem :
nwell not connected to vdd or vcc.. i xpect to be erc error.. nybody has idea how to rectify??
psub not connected to vss
thx in advance.
Analog IC Design and Layout :: 13.07.2009 03:36 :: deepak242003 :: Replies: 7 :: Views: 1912
For parasitic extraction of same circuit in calibre,we did the RC extraction in assura..... but to our surprise we are gatting large parasitics this time(assura)...... I means in terms of resistor.. it was not more that 50 ohm previously..... but wiht assura we are getting in kohms and even in M ohms for few (...)
Analog IC Design and Layout :: 15.07.2009 07:46 :: deepak242003 :: Replies: 0 :: Views: 663
for the same circuit extraction was done in calibre.... now wehn I did same extraction wiht assura,it is showing large parasitic resistance. for few nets.........
rl1482 ( dvss12\#15991 dvss12\#15386 ) resistor r=999999995904.0000
rl1492 ( dvss12\#15305 dvss12\#16867 ) resistor r=999999995904.0000
Analog IC Design and Layout :: 21.07.2009 03:29 :: deepak242003 :: Replies: 10 :: Views: 2472
For the extractoin of same circuit, I am getting different extraction parasitics for calibre and assura.....
below is the extraction for assura...
rl1482 ( dvss12\#15991 dvss12\#15386 ) resistor r=999999995904.0000
rl1492 ( dvss12\#15305 dvss12\#16867 ) resistor r=999999995904.0000
Analog Circuit Design :: 27.07.2009 04:41 :: deepak242003 :: Replies: 2 :: Views: 747
Sorry if this topic make you bored.
Firstly I have the cadence done the LVS using assura, and it worked. However my partner only has calibre for doing LVS; and the problem arises.
I read the discussion here:
I tried to follow the solution but not worked.
I am using IBM PDK cmrf8sf V1.6.2.
Analog IC Design and Layout :: 22.11.2009 11:22 :: se3 :: Replies: 4 :: Views: 1863
I did extraction from calibre xRC and got "calibre" view. When i simulate it by changing the config view of the testbench I get the same simulation results as that of schematics.
Where I am making the mistake? I did extraction with assura and its av_extracted shows the desired behaviour, that is it shows the affect of parasitics. (...)
Analog IC Design and Layout :: 30.12.2009 23:45 :: Usman Hai :: Replies: 3 :: Views: 848
While running DRC in virtuoso for umc90nm ,it gives an error as
line 320 of (DRC selected file),unable to open or access file type
and that file is ./90nm_layers.cal
I dont know why that error occurs
the restricted foundry document or the staff from UMC will give you a hint.
basically, calibre is looking for
Analog IC Design and Layout :: 09.04.2010 16:19 :: wpchan05 :: Replies: 6 :: Views: 760
Is there a way to convert an assura deck to calibre format, or can the calibre tool read a deck that is in assura format?
If a script exists to convert the formats, where can I find it?
ASIC Design Methodologies and Tools (Digital) :: 06.04.2010 20:33 :: zorori :: Replies: 0 :: Views: 541
I have tsmc018rf library,include technology lib, calibre/assura verify,
spectre/ADC/eldo/hspice model and design kit. But I need 90nm process. we can share each other. OK?
ASIC Design Methodologies and Tools (Digital) :: 16.09.2010 03:02 :: xibeizi :: Replies: 1 :: Views: 551
I am currently designing a bandgap reference (BGR) circuit in IBM cms9flp.
Using assura for LVS the circuit is shown to be correct (layout schematic match, and no extraction problems)
When I use calibre the result is Correct again, there are no extraction problems, BUT there is an ERC error. The description of the e
Analog IC Design and Layout :: 29.12.2010 08:43 :: mixaloybas :: Replies: 3 :: Views: 1185
I am new to cadence and assura. I am facing severe problem with IBM_PDK and assura. When I run avview, assura pops up and everything will be fine. But when I run the same with icfb and go to IBM_PDK tab, I am getting the following error. I checked the forum, but each has different answer and I almost tried everything. (...)
Electronic Elementary Questions :: 09.02.2011 19:00 :: giridhar_osu :: Replies: 0 :: Views: 698
calibre extraction more accurate regarding to my experiences.But it totally depends on the technology that you would use.
Because extraction rules are defined by your tech. file and it is dependent on its accuracy and definitions.
RF, Microwave, Antennas and Optics :: 06.03.2011 09:42 :: BigBoss :: Replies: 1 :: Views: 880
Our foundry advises provides rule decks for all three tools. As per their notes, calibre is better at detecting width/space violations and assura is better for density checks. Nothing specific about Hercules.
Analog IC Design and Layout :: 15.03.2011 09:33 :: oermens :: Replies: 7 :: Views: 1445
assura QRC layout or calibre PEX extraction tool is better ? What is the advantage and disadvantage? Thanks
Analog IC Design and Layout :: 08.04.2011 00:13 :: surianova :: Replies: 0 :: Views: 964
I am using IC5141 and I have neither assura nor calibre installed. I am going to download one of these tools. Given a Cadence version, is there any rule in order to choose assura or calibre?
If I choose assura, which are the steps to follow after installation? I know I should add some settings in my (...)
Analog IC Design and Layout :: 27.06.2011 05:09 :: Kicchan :: Replies: 2 :: Views: 1005
I wanted to convert calibre rule files to assura rule files because those are the only rule files available from the foundry at the moment. Is there any script available for that? What languages/methods could one learn to perform this task? How difficult and time consuming is it?
Thanks for your help.
Analog IC Design and Layout :: 15.07.2011 10:16 :: junas125 :: Replies: 4 :: Views: 757
If there is no documentation on PDK,
The simple way to choose better capacitor- is to perform parasitic extraction by calibre/assura end check extracted netlist for parasitic capacitance.
Analog IC Design and Layout :: 18.08.2011 04:19 :: AlexVD :: Replies: 3 :: Views: 736
...I've used ntiedown as substrate contact
I don't agree with this...ntiedowns are protection diodes NOT substrate contacts.
You must use subc for substrate contacts instantiation in schematic and layout instead!
I have no experience with calibre so if possible try with assura and give me the repsective error report.Also che
Analog IC Design and Layout :: 22.08.2011 06:22 :: jimito13 :: Replies: 33 :: Views: 2784
I have a problem when I am doing LVS check using calibre tool. I am using IBM 10LPE technology, in the layout, I have a MIMCAP and also put a few transistors underneath. The transistors are RF device so I circle the device by "SXCUT (lable)" and put "sub!" label in the free substrate. Withou mimcap it passes DRC and LVS,
but when I put mim
Analog IC Design and Layout :: 24.09.2011 23:00 :: rickgchen :: Replies: 9 :: Views: 1465
Do anyone know how to configure the xRC (calibre extraction) in order to create a compact extracted netlist?
In assura, we can define the minimum value of R and C, also merge resistors (and so on...), what makes the extracted view more compact and faster to be simulated.
How can I do this with PEX?
Thanks in advance.
Analog IC Design and Layout :: 10.11.2011 07:01 :: palmeiras :: Replies: 0 :: Views: 890
Need more clarity on the question. RFMOS "device" extraction should be happening at the LVS extraction stage - what does that has any relation with RCX?
If this is LVS problem - which LVS tool Which technology? layout of "big" and "small" rfmos may help, overall more details will help.
Analog IC Design and Layout :: 22.11.2011 17:19 :: sat :: Replies: 2 :: Views: 630
you need to work with CAD. The info you gave is very little to help. calibre, assura and HERCULES have a different methods of running LVS.
ASIC Design Methodologies and Tools (Digital) :: 09.06.2012 23:39 :: vikadik :: Replies: 5 :: Views: 603