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260 Threads found on edaboard.com: Calibre Layout
Dears I am trying to do calibre extraction for inverter but i am facing this problem ERROR: Could not find cell mapping for device nch. Ignoring instance M0. ERROR: Could not find cell mapping for device pch. Ignoring instance M1. However the LVS passed successfully, could you please help me in that. I am using TSMC65n
Hello All, I designed a layout in SoC Encounter using NangateOpenCellLibrary 45nm which had zero geometry and connectivity violations. I then exported GDS file and verilog netlist from Encounter. I went to calibre to run LVS and afterwards PEX for post-layout simulations. Here are my steps: 1) run v2lvs command "v2lvs -v (...)
Hello All, I designed a layout in SoC Encounter using NangateOpenCellLibrary 45nm which had zero geometry and connectivity violations. I then exported GDS file and verilog netlist from Encounter. I went to calibre to run LVS and afterwards PEX for post-layout simulations. Here are my steps: 1) run v2lvs command "v2lvs -v (...)
That could be it. When you say there were zero geometry and connectivity violations in Encounter, are you sure you ran the checks at the top level? For the calibre issues, it is odd to have over 12,000 ports in the layout, and also odd that the top level port names are not valid for netlisting. These hint at a problem in the layer mapping. You m
I'd need more details to recommend the best way (see the section "Best Way to Resize Designs" in the xrc_user manual) but you could try adding "layout USE DATABASE PRECISION YES" to the SVRF rule file. (That is supposed to be the default for xRC and xL if it isn't specified in the rule file. It is possible the foundry has reasons for wanting you t
SPF and DSPF stand for the same thing - its an acronym for "Detailed Standard Parasitic Format". DSPF (or SPF) file is the output of extraction tool (StarRC, QRC/Quantus, calibrePEX / XRC, F3D,...) - a text file containing post-layout netlist. It contains information about design elements (MOSFETs, diodes, BJTs, resistors, capacitors, inductors,...
Hi guys! When i copy the layout of the triple well mosfet nfet33tw from the pdk (ibm 130nm) as it is and ran lvs on this single device without any modification or connections, the calibre is unable to recognize the device. Am i missing anything here? Thanks
Hi Guys, I'm developing layouts circuits using FreePdk45nm and the NCSU just released DRC rules checker to calibre.. Is there any free version of the software or any option to analyse the errors? Thanks in advance!!
I was error "missing port VDD,GND,IN,OUT" in process layout lvs calibre cadence I need help Thank all 134050134051
Hi, I am new to post layout simulation. I am having trouble in interpreting the extracted netlist. Can someone please translate the statements to English language!!! *|NET in 2.04548e-17 *|I (XI5:A XI5 A X 0.0 0.2867 0.945) *|I (XI9:Z XI9 Z X 0.0 6.562 0.945) *|P (in X 0.0 6.562 0.945) cin|0 XI5:A VSS 0.0204548f rin|1 XI5:A in 2.4762
Hello all, I am currently working on layout in cadence virtuoso having calibre tool. In inverter while doing DRC,I am getting the following error which I am unable to solve since 1 month and I didn't found in google. 1. Offgrid error 2. Orthogonal corners are not allowed at die edge. 3. related to M1,M2,GC coverage. (GC coverage less than 0.2
I was using cadence virtuoso for my entire career(last 10 years) and never worked in any mentor layout tool(except calibre verification) Now my new project is going to start in Mentor Pyxis, I am not at all familiar with this tool. I am feeling very difficult in doing layout and modifying layout with this tool, is there is (...)
Hi everbody, I have Installed IC610, MMSIM12, Assura and calibre 4.12 x86_cal_2011.2_34.26 ON the Ubuntu 10.04 32 'bit the OS. I got a problem with calibre interactive below, 127577 *** calibre Interactive: Exporting layout for library "tsmc18rf", cell "transistor", view "layout" *** sh: pipo: (...)
This is perhaps too basic, but... is IC6 set to export the layout to calibre? Is the pcell listed in an LVS Box statement as something to be ignored?
Hi, I am using clibre for pex. I want to avoid double extraction of rf models e.g. nfet_rf I have declared xcell file as follows: nfet_rf* nfet_rf The problem is when I use Outputs>Get net names from schematic, this does not work and double extraction happens. When I use get names from layout, it works but my cellmap gives me error and
hi guys, anyone can help me between calibre and hercules using their option?? in calibre, can use 'layout POLYGON' option.. but in Hercules i can find out how to using like calibre... i saw manual and ask other people, found some of hercules option.. : POLYGON_FEATURES and RECTANGLES. but is was not same like (...)
Dear All i have design a transconductance amplifier. done with layout of it.. cleared DRC and LVS and PEX. in PEX i m getting some warning. i m not able to understand those warning but because of these warning i m able to generate config view. i m attaching the error file
I see there is a "blank" between inverterlayout. & calibre.gds Guess calibre cannot cope with blanks in file_names.
Hello all, I have a strange problem running DRC check using calibre. When I start Virtuoso, license "111" is succesfully checked out and everything works fine (Schematic, layout, MMSIM). I implemented the calibre skill interface in the .cdsinit and the drop down menu in layout editor appears. When I start (...)
Hello, Is seems like your extraction tool use real capacitor and resistors instead of pcapacitor and presistor. But I don't shure with it. Do you have other extraction tools? Assura or calibre maybe...
hi, i just installed the Mentor Graphics Pyxis tool, not sure it shares the licence of calibre or not. Can you tell me what's the command to start the GUI of the tool from terminal? Thanks!
Hi just make layout and perform extraction operations with assura or calibre :) Or, perhaps you have RFmos in your technology library and, in that case all parasitic capacitances of mos already included in model.
Dear all, I have a problem with post layout. I have already created the file: "myCyrcuit.pex.netlist" due calibre/pex. For output I chose "Gate Level", "R+C+CC": ======================================================================== calibre xRC WARNING / ERROR Summary (...)
There is an error in calibre DRC It says that I should not have any device in the corner of area... Then I think I should use a layer to define the area of layout. But I don't know which layer I can/should use? Thank you
hi i want to plot the IDDQ of a simple design. i have two ways help me to choose one. hear are the ways 1. make a layout using soc encounter and convert it to spice model using calibre 2. synthesize the design using design compiler and using command v2s to extract the spice model help me plz
Hi all: I'm facing a problem about the calibre LVS/PEX, I will describe it using this simple current mirror shown below, X and Y are same MOSFETs with width=16, nfing=2, m=1: 101041 When I just do the layout with only one finger for both X and Y (w=16, nfing=1, m=1), and do the post-layout simulation, I injected 100
Hi! I have a problem with calibre Interactive. When I try to run DRC for my layout verification ,it gives the error ' The following products could not be licensed sufficiently". Hope somebody can help me please..
I have a Cadence schematic view and its layout. I also have a calibre RC extracted view. There is a pmos device M20 in my schematic and I would like to see the voltage on the gate of M20. How do I map the gate of M20 from the schematic view to that in the calibre RC extracted view ??? Can someone help ?
Hello all, I'm preparing for my graduation project which is (a Verilog implementation of the all digital phase locked loop ) and asking if you can recommend me any good books or references about this topic, and any tutorials on how to make the chip layout on cadence and calibre . (i really don't have any experience on how to get the chip lay
Hi all. I am trying to do LVS using std. cells from foundry. I am using Cadence tools with calibre LVS. I am currently using an inverter (with input and output pins) as a test case. 1. Anyone know how to handle inherited gnd/vdd in layout? I see them in the schematic netlist, but I dont know how to include them in the layout. Are (...)
Hi all I want to run LVS through calibre tab in cadence environment. But I cannot do it because calibre needs the schematic view of my design and I don?t have the schematic view. Could anybody help me to solve this problem ( i mean running lvs without schematic view)? Best Regards
I'll try to check this cell tomorrow on IBM PDK v1.8. Are You sure about using a correct calibre settings for LVS? On the first look it could be good... In IBMCMOS8RF I using "multiple partpath" to making a well/substrate contacts and surrounded whole transistor with it. I am using cmrf8sf v1.8, too.
I don't think so. calibre basically doesn't support feedthrough nets -- if two top-level ports are connected by a long wire calibre will totally ignore the wire resistance. The only way around this is to actually change your both your layout (ugh!) and schematic -- you have to remove the wire from your layout, replace it (...)
Hi, Is there a way to automatically generate a Hcell file for calibre hier LVS run. I know the format needs to be source layout Thanks.
Hi Manoj, calibre needs layout ( in GDS format ) & Source ( Verilog netlist ), which are dumped from the Implementation tools. Later, Verilog Netlist is converted into SPICE format ( CDL ). Now the calibre has GDS & CDL, it starts comparing the connectivity based on the Rules defined in the Rule Deck ( From Foundry ). Coming to ICC, (...)
Lets say i convert prelayout netlist to post layout using calibre , so Is there any mapping between nodes in top subckt in pre layout netlist and post layout netlist?
Hi , I ran calibre lvs .I saw some ports/nets mismatched. After Transformation: ports ----layout source Net GND GND 13 ------- cells :AND1D AND1D in1:a in1:a in2:b in2:b in3:1 in3:GND[/C
I prefer klayout because you can import the tech file from Cadence to get the same colors and shapes as Virtuoso, but on Windows, Mac and Linux... for free. It because very convenient on Windows to double click on a GDS file and get the same view as in Cadence. It also import calibre DRC results ... easy to see on Windows.
As far as I know, you can not suppress these warning message from externally. This warning message is reported because calibre does not find the CELL NAME used in operation in your layout. If you have write access to calibre runset, then you can add an exception in starting of calibre. You can refer to Mentor user manual for (...)
Do you know exactly where can i do it in the layout? No, sorry; no access to C@dence/Mentor tools any more. Try the options/extra. Or in the control options of calibre.
Hello I have a problem when I do a LVS check using calibre. Aparently it shows LVS clean my layout for a older version of calibre, but when I update for a latest version there seems to some errors in LVS. Could anyone tell me how is that errors do not exist for older versions of calibre and it shows errosthe latest (...)
use calibre pex, the calibreview shcematic has lots of warnings:floating nets. The floating nets are all related to the extracted parasitic. DRC and LVS are both okay. Is it related to the layout? Will layout pin or label affect the result?
I recommend to run GND line in distance of 1-2um left/right from your CLK line This will shiled nicely the signals parallel with CLK and also minimizes the capacitive load oon CLK line. THEN run PEX with calibre and run simulation. You should see very well how the shielding works. I do not like to put metal above/bellow CLK line due to added capac
Hello, my friends:-) I am extracting parasitics of my layout using calibre. However, I have a problem related to calibre PEX MOS finger For example : Fingers of transistors in my schematic & layout are W=90, L=1, NF= 15. However, The result is that in calibreview(calibre) I'm (...)
Hi, I am doing post layout simulations in cadence spectre using generated parasitic file from calibre PEX tool. Simulation results show different results than compared with pre-layout simulations. Therefore, i need to tune the layout to make the circuit working with parasitics. Previously, i used to edit the (...)
Hi, I am generating calibre view file from calibre PEX for extracted simulations. However, my extracted and non-extracted simulation results for low noise amplifier show a huge gain loss of 15dB. After manually analyzing the layout parasitics, i think that such big loss is not possible from just layout parasitics. I (...)
when i run lvs using calibre,i met : ************************************************************************************************************** INCORRECT INSTANCES DISC# layout NAME SOURCE NAME ************************************************************************************************************** 1 X16/C2765(19.435,17.290) C(mim_1p0) X
Hi, I have two simple question to ask why doesn't the layout instance of MOS from CIC library(0.35um) have bulk contact? I have only see diff and nimp for nmos but no pimp and how do I choose the contact type in calibre? ex: M1_POLY1 ,M1N,M1P... thank you
Hi, I have two questions: 1. Why for some cells, IBM_PDK and calibre is not shows on Virtuoso menubar? 2 Why I get "RROR: Specified primary cell XXX is not located within the input layout database" error message while doing DRC on some cells? Where is the "input layout database" and how can I add other cells to this database? Regards
Hi I am generating calibre view file for post layout simulations from calibre PEX tool. I am seeing following errors (shown in screenshot attached) Can somebody suggest the reason of error and how to correct them to generate proper calibreview