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6 Threads found on edaboard.com: Capacitance Output Cadence
Measure the delay for 2 or more known load capacitances. Plot delay vs. capacitance and extrapolate for Cload=0 .
hai, i am designing VCO in cadence-virtuoso ADE L(180nm) topology is attached below where i have to know how to plot graph C Vs Voltage. capacitance is parallel combination of two PMOS varactors (PM2 and PM3) and also when i simulated the ckt with 1.2V i am getting low peak to peak voltage swing how to increase the output voltage peak to (...)
i want to find-calculate the total load capacitance at the output node (Vout1 as shown in the image). Connect a unit current source (analogLib/idc or analogLib/isin) with AC magnitude=1 and any Frequency between Vout1 and gnd. Then run an ac analysis, sweeping the frequency between your points of
I doubt you have a much bigger capacitance at your output node?? Calculate carefully your required load. Generally it will not be more than 1 pF in normal applications. About your doubt on plotting.....after plotting in the wavescan double click on the x-axis at the bottom. A pop window will appear and you can choose other waveforms instead of t
Let say I have a combinational logic gates which have 1 input node and 1 output node. In cadence, what method to use to measure the input capacitance (Cin) and output capacitance (Cout) of these two nodes?
Hi, I have problem in doing Assura RC extraction. When I finished layout and did the RC extraction, I found there was a large capacitance between input and output. I thought that it might be some misunderstanding in setting the environment. the schematic and layout are shown below. Is there somebody can help me the solve the problem? tha